ON Semiconductor FDG6304P User Manual

Digital FET, Dual P-Channel
FDG6304P
General Description
These dual PChannel logic level enhancement mode field effect transistors are produced using ON Semiconductor proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize onstate resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs.
Features
25 V, 0.41 A Continuous, 1.5 A Peak
RR
Very Low Level Gate Drive Requirements Allowing Direct
Operation in 3 V Circuits (V
GateSource Zener for ESD Ruggedness (>6 kV Human Body
Model)
Compact Industry Standard SC706 Surface Mount Package
These Devices are PbFree and are RoHS Compliant
ABSOLUTE MAXIMUM RATINGS (T
Symbol Parameter FDG6304P Units
V
DSS
V
GSS
I
D
P
D
TJ, T
STG
ESD Electrostatic Discharge Rating
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
= 1.1 W @ VGS = 4.5 V
DS(ON)
= 1.5 W @ VGS = 2.7 V
DS(ON)
< 1.5 V)
GS(th)
= 25°C unless otherwise noted)
A
DrainSource Voltage 25 V
GateSource Voltage −8 V
Drain/Output Current
Maximum Power Dissipation (Note 1) 0.3 W
Operating and Storage Temperature Range
MILSTD883D Human Body Model (100 pF / 1500 W)
Continuous 0.41
Pulsed 1.5
55 to +150 °C
6.0 kV
A
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G2
G2
D1
D2
G1
S1
SC88/SC706/SOT363
CASE 419B02
MARKING DIAGRAM
04M
04 = Specific Device Code M = Assembly Operation Month
PIN CONNECTIONS
1 or 4*
2 or 5
3 or 6
*The pinouts are symmetrical; pin 1 and 4 are
interchangeable. Units inside the carrier can be of either orientation and will not affect the functionality of the device.
6 or 3
5 or 2
4 or 1*
© Semiconductor Components Industries, LLC, 2000
June, 2020 Rev. 6
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of this data sheet.
1 Publication Order Number:
FDG6304P/D
FDG6304P
THERMAL CHARACTERISTICS
Symbol Parameter Ratings Unit
R
q
1. R
q
JA
mounting surface of the drain pins. R minimum pad mounting on FR−4 board in still air.
Thermal Resistance, Junction−to−Ambient (Note 1) 415
JA
is the sum of the junctiontocase and casetoambient thermal resistance where the case thermal reference is defined as the solder
is guaranteed by design while R
q
JC
is determined by the user’s board design. R
q
CA
= 415°C/W on
q
JA
_C/W
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Unit
OFF CHARACTERISTICS
DBV
BV
DSS
I
DSS
I
GSS
DSS
DrainSource Breakdown Voltage
Breakdown Voltage Temperature
/ DT
J
Coefficient
Zero Gate Voltage Drain Current
VGS=0V, ID= 250 mA
ID= 250 mA, Referenced to 25_C
VDS= 20 V, VGS=0V −1
VDS= 20 V, VGS=0V, TJ = 55_C
GateBody Leakage Current VGS= 8V, VDS=0V 100 nA
25 V
22
mV/_C
10
mA
mA
ON CHARACTERISTICS (Note 2)
DV
V
GS(th)
GS(th)
R
DS(on)
Gate Threshold Voltage
Gate Threshold Voltage
/ DT
J
Temperature Coefficient
Static DrainSource OnResistance
VDS=VGS, ID= 250 mA
ID= 250 mA, Referenced to 25_C
VGS= 4.5 V, ID= 0.41 A 0.85 1.1 W
VGS= 4.5 V, ID= 0.41 A,
= 125_C
T
J
0.65 0.82 1.5 V
2
mV/_C
1.2 1.9
VGS= 2.7 V, ID= 0.25 A 1.15 1.5
I
D(on)
g
FS
OnState Drain Current VGS= 4.5 V, VDS= 5V 1.5 A
Forward Transconductance VDS= 5V, ID= 0.41 A 0.9 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 34 pF
Reverse Transfer Capacitance 10 pF
VDS=10V, VGS= 0 V, f = 1.0 MHz
62 pF
SWITCHING CHARACTERISTICS (Note 2)
t
D(on)
t
t
D(off)
t
Q
Q
Q
Turn-On Delay Time
r
Turn-On Rise Time 8 16 ns
Turn-Off Delay Time 55 80 ns
f
g
gs
gd
Turn-Off Fall Time 35 60 ns
Total Gate Charge
GateSource Charge 0.31 nC
GateDrain Charge 0.29 nC
VDD= 5V, ID= 0.5 A, V
GS
= 4.5 V, R
GEN
=6W
VDS= 5V, ID= 0.41 A, V
= 4.5 V
GS
7 15 ns
1.1 1.5 nC
DRAINSOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Maximum Continuous Source Current 0.25 A
DrainSource Diode Forward
VGS=0V, IS= 0.25 A (Note 2) 0.85 1.2 V
Voltage
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2.0%
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FDG6304P
TYPICAL PERFORMANCE CHARACTERISTICS
1.2
0.9
0.6
V = 4.5 V
GS
3.0 V
2.7 V
2.5 V
2.0 V
2.5
1.5
2
V = 2.0 V
GS
2.5 V
2.7 V
, NORMALIZED
0.3
0
, DRAINSOURCE CURRENT (A)
01234
D
I
VDS, DRAIN−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
1.5 V
1
DS(ON)
R
0.5
00.2 11.2
DRAINSOURCE ONRESISTANCE
0.4
Figure 1. OnRegion Characteristics Figure 2. OnResistance Variation with
Drain Current and Gate Voltage
1.6 I
= 0.41 A
D
= 4.5 V
V
GS
1.4
1.2
1
, NORMALIZED
0.8
DS(ON)
R
0.6
50 25 0 25 50 75 100 125 150
DRAINSOURCE ONRESISTANCE
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. OnResistance Variation with
Temperature
5
W
4
3
2
, ONRESISTANCE ( )
1
DS(ON)
0
R
12345
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 4. OnResistance Variation with
GatetoSource Voltage
3.0 V
0.80.6
3.5 V
TJ = 125°C
4.5 V
ID = 0.2 A
25°C
1
VDS = 5 V
0.8
0.6
0.4
0.2
, DRAIN CURRENT (A)
D
I
0
0.5 1 1.5 2 2.5 3
= 55°C
T
J
25 C
°
125
VGS, GATE TO SOURCE VOLTAGE (V)
°
C
1
V
= 5 V
GS
0.1
0.01
0.001
0.0001
, REVERSE DRAIN CURRENT (A)
0.2 0.4 0.6 0.8 1 1.2
S
I
VSD, BODY DIODE FORWARD VOLTAGE (V)
T
= 125°C
J
25 C
°
°
55 C
Figure 5. Transfer Characteristics Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature
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3
FDG6304P
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
5
I = 0.41 A
D
4
3
2
1
, GATESOURCE VOLTAGE (V)
0
0 0.4 0.8 1.2 1.6
GS
V
Qg, GATE CHARGE (nC)
V = 5 V
DS
10 V
15 V
200
80
30
10
CAPACITANCE (pF)
f = 1 MHz
5
V
= 0 V
GS
3
0.1 0.3 1 10 25
25
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics Figure 8. Capacitance Characteristics
3
1
R
LIMIT
DS(ON)
0.5
0.1
VGS = 4.5 V
0.05 SINGLE PULSE
, DRAIN CURRENT (A)
D
R
= 415°C/W
q
I
JA
T
= 25°C
A
0.01
0.1 0.2 0.5 12 510 25 40
DC
10 ms
100 ms
1 s
10 s
VDS, DRAINSOURCE VOLTAGE (V)
1 ms
50
40
30
20
POWER (W)
10
0
0.0001 0.001 0.01 0.1 1 10 200
SINGLE PULSE TIME (sec)
C
iss
C
oss
C
rss
SINGLE PULSE
= 415°C/W
R
q
JA
= 25°C
T
A
Figure 9. Maximum Safe Operating Area
1
D = 0.5
0.5
0.2
0.2
0.1
0.1
0.05
0.02
0.01
0.005
0.002
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
0.05
0.02
0.01 Single Pulse
0.0001 0.0 01 0.01 0. 1 1 10 100 200
Thermal characterization performed using the conditions described in Note 1. Transient thermal response will change depending on the circuit board design.
Figure 11. Transient Thermal Response Curve
Figure 10. Single Pulse Maximum Power
t , TIME (sec)
1
Dissipation
R R
P(pk)
T
J
Duty Cycle, D = t
(t) = r(t) * R
q
JA
= 415°C/W
q
JA
t
1
t
2
− TA = P * R
q
JA
(t)
q
JA
/ t
1
2
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4
FDG6304P
ORDERING INFORMATION
Device Order Number Device Marking Package Type Shipping
FDG6304P 04 SC88/SC706/SOT363
(PbFree)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
3000 / Tape & Reel
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC88/SC706/SOT363
1
SCALE 2:1
D
A
654
E
123
2X
bbb H
D
e
B
TOP VIEW
6X
ccc
C
SIDE VIEW END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.30
0.65
PITCH
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
2X
aaa H D
D
E1
L2
aaa C
2X 3 TIPS
b
6X
M
A2
A
A1
C
6X
0.66
SEATING PLANE
2.50
DIMENSIONS: MILLIMETERS
Cddd
A-B D
DETAIL A
CASE 419B02
ISSUE Y
H
L
DETAIL A
GAGE PLANE
DATE 11 DEC 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU­SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI­TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT.
MILLIMETERS
DIM MIN NOM MAX
A −−− −−− 1.10 A1 0.00 −−− 0.10 A2 0.70 0.90 1.00 0.027 0.035 0.039
b 0.15 0.20 0.25
C 0.08 0.15 0.22
D 1.80 2.00 2.20
E
2.00 2.10 2.20
E1 1.15 1.25 1.35
e 0.65 BSC
L 0.26 0.36 0.46 L2 0.15 BSC 0.006 BSC
aaa 0.15 0.006
bbb 0.30 0.012
ccc 0.10 0.004
ddd
c
0.10 0.004
INCHES
MIN NOM MAX
−−− −−− 0.043
0.000 −−− 0.004
0.006 0.008 0.010
0.003 0.006 0.009
0.070 0.078 0.086
0.078 0.082 0.086
0.045 0.049 0.053
0.026 BSC
0.010 0.014 0.018
GENERIC
MARKING DIAGRAM*
6
XXXMG
G
1
XXX = Specific Device Code M = Date Code* G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
*This information is generic. Please refer to
device data sheet for actual part marking. PbFree indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
98ASB42985B
SC88/SC706/SOT363
Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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SC88/SC706/SOT363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 7:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
4. SOURCE 1
5. DRAIN 1
6. GATE 2
STYLE 13:
PIN 1. ANODE
2. N/C
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 19:
PIN 1. I OUT
2. GND
3. GND
4. V CC
5. V EN
6. V REF
STYLE 25:
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
5. EMITTER
6. COLLECTOR 1
STYLE 2:
CANCELLED
STYLE 8:
CANCELLED
STYLE 14:
PIN 1. VREF
2. GND
3. GND
4. IOUT
5. VEN
6. VCC
STYLE 20:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 3:
CANCELLED
STYLE 9:
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
5. BASE 2
6. COLLECTOR 2
STYLE 15:
PIN 1. ANODE 1
2. ANODE 2
3. ANODE 3
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
STYLE 21:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. N/C
6. CATHODE 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
6. ANODE
STYLE 10:
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
4. DRAIN 1
5. DRAIN 2
6. GATE 2
STYLE 16:
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
5. EMITTER 1
6. COLLECTOR 1
STYLE 22:
PIN 1. D1 (i)
2. GND
3. D2 (i)
4. D2 (c)
5. VBUS
6. D1 (c)
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
Note: Please refer to datasheet for style callout. If style type is not called out in the datasheet refer to the device datasheet pinout or pin assignment.
STYLE 5:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 11:
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
STYLE 17:
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
5. EMITTER 2
6. COLLECTOR 1
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
4. N/C
5. CH2
6. N/C
STYLE 29:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
STYLE 6:
PIN 1. ANODE 2
2. N/C
3. CATHODE 1
4. ANODE 1
5. N/C
6. CATHODE 2
STYLE 12:
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
STYLE 18:
PIN 1. VIN1
2. VCC
3. VOUT2
4. VIN2
5. GND
6. VOUT1
STYLE 24:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
STYLE 30:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
98ASB42985B
SC88/SC706/SOT363
Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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