ON Semiconductor EZAIRO 7150 SL HYBRID Instructions

EZAIRO 7150 SL HYBRID

Wireless-Enabled Audio
Processor for Digital
Hearing Aids

Introduction

EZAIRO® 7150 SL is an open−programmable DSP−based hybrid
specifically designed for use in wirelessly connected,
high−performance hearing aids and hearing implant devices. The
Ezairo 7150 SL hybrid includes the Ezairo 7100 System−on−Chip
(SoC) with its high−precision quad−core architecture that delivers 375
MIPS, without sacrificing power consumption.

The highly−integrated Ezairo 7100 includes an optimized,
dual−Harvard CFX Digital Signal Processor (DSP) core and HEAR
Configurable Accelerator signal processing engine. It also features an

®

Arm

Cortex®−M3 Processor Subsystem that supports various types
of protocols for wireless communication. This block combines an
open−programmable controller with hardware accelerators for audio
coding and error correction support.

Ezairo 7100 also includes a programmable Filter Engine that
enables time domain filtering and supports an ultra−low−delay audio
path. When combined with non−volatile memory and wireless
transceivers, Ezairo 7100 forms a complete hardware platform.

The Ezairo 7150 SL hybrid includes the nRF51822 wireless
transceiver from Nordic Semiconductor. The nRF51822 is a powerful,
highly flexible multi−protocol SoC ideally suited for Bluetooth
Energy (BLE) and 2.4 GHz ultra−low−power wireless applications.

Ezairo 7150 SL also contains 2 Mb EEPROM storage and the
necessary passive components to directly interface with the
transducers required in a hearing aid.

®

Low

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EZAIRO

CASE 127DQ

MARKING DIAGRAM

E7150−102

XXXXXX

(Top View)

E7150−102 = Specific Device Code
XXXXXX = Work Order Number

ORDERING INFORMATION

Device Package Shipping

E7150−102A49−AG SIP49

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†

250 / Tape &

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December, 2017 − Rev. 5

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
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1 Publication Order Number:

E7150/D

EZAIRO 7150 SL HYBRID

Key Features

• Programmable Flexibility: the open−programmable

DSP−based system can be customized to the specific
signal processing needs of manufacturers. Algorithms
and features can be modified or completely new
concepts implemented without having to modify the
chip.

• Fully Integrated Hybrid: includes the Ezairo 7100

SoC, nRF51822 radio IC, 2 Mb EEPROM storage, and
the necessary passive components to directly interface
with the transducers required in a hearing aid.

• Quad−core Architecture: includes a CFX DSP, a

HEAR Configurable Accelerator, an ARM Cortex−M3
Processor Subsystem, and a programmable Filter
Engine. The system also includes an efficient
Input/Output Controller (IOC), system memories, input
and output stages, along with a full complement of
peripherals and interfaces.

• CFX DSP: a highly cycle−efficient, programmable

core that uses a 24−bit fixed−point, dual−MAC,
dual−Harvard architecture.

• HEAR Configurable Accelerator: a highly optimized

signal processing engine designed to perform common
signal processing operations and complex standard
filterbanks.

• ARM Cortex−M3 Processor Subsystem: a complete

subsystem that supports efficient data transfer to and
from the wireless transceiver or multiple transceivers.
The subsystem includes hardwired CODECS (G.722,
CVSD) and Error Correction support (Reed−Solomon,
Hamming), as well as a fully programmable ARM
Cortex−M3 processor and dedicated interfaces.

• Programmable Filter Engine: a filtering system that

allows applying a various range of pre− or post−
processing filtering, such as IIR, FIR and biquad filters.

• Configurable System Clock Speeds: 1.28 MHz, 1.92

MHz, 2.56 MHz, 3.84 MHz, 5.12 MHz, 6.4 MHz, 7.68
MHz, 8.96 MHz, 9.60 MHz, 10.24 Mhz (default clock
calibration), 12.80MHz and 15.36MHz to optimize the
computing performance versus power consumption
ratio. The calibration entires for these 12 clock speeds
are stored in the manufacturing area of the EEPROM.

• Ultra−low Delay: programmable Filter Engine

supports an ultra−low−delay audio path of 0.044 ms (44
ms) for superior performance of features such as
occlusion management.

• Ultra−high Fidelity: 85 dB system dynamic range with

up to 110 dB input signal dynamic range,
exceptionally−low system noise and low group delay.

• Ultra−low Power Consumption: <0.7 mA @ 10.24

MHz system clock (executing a tight MAC−loop in the
CFX DSP core plus a typical hearing aid filterbank on
the HEAR Configurable Accelerator).

• High Output Level: output levels of ~139 dB SPL

possible with low impedance receiver (measured using
IEC 711 coupler).

• Diverse Memory Architecture: a total of 40 kwords of

program memory and 44 kwords of data memory,
shared between the four cores included on the Ezairo
7100 chip.

• Data Security: sensitive program data can be

encrypted for storage in EEPROM to prevent
unauthorized parties from gaining access to proprietary
algorithm intellectual property.

• Signal Detection Unit: ultra−low−power detection

system for signals on any analog inputs.

• High Speed Communication Interface: fast

2

C−based interface for quick download, debugging and

I
general communication.

• Highly Configurable Interfaces: two PCM interfaces,

2

C interfaces, two SPI interfaces, a UART

two I
interface as well as multiple GPIOs can be used to
stream configuration, control or signal data into and out
of the Ezairo 7150 SL hybrid.

• On−chip PLL: support for communication

synchronization with wireless transceiver.

• Glueless MMI: link to various analog and digital user

interfaces such as analog or digital volume control
potentiometers, push buttons for program selection and
microphone/telecoil switching.

• Fitting Support: support for Microcard, HI−PRO 2,

HI−PRO USB, QuickCom, and NOAHlinkt, including
NOAHlink’s audio streaming feature.

• Development Tools: The Ezairo Preconfigured Suite

provides a software application to fine−tune and
customize the firmware bundle pre−loaded on Ezairo
7150 SL. A cross−platform Software Development Kit
(SDK) to develop fitting software and wireless
applications is also provided. To program the Ezairo
7150 SL with your own firmware, the Ezairo 7100
Evaluation and Development Kit (EDK) includes
optimized hardware, programming interface, and a
comprehensive Integrated Development Environment
(IDE).

• These Devices are Pb−Free, Halogen Free/BFR Free

and are RoHS Compliant

.

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EZAIRO 7150 SL HYBRID

Table 1. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Min Max Unit

VBAT Power supply voltage 2 V

VBATOD Output drivers power supply voltage 2 V

VDDO

1,2,3

Vin Voltage at any input pin GNDC−0.3 VDDO + 0.3 V

DGND, AGND, HGND Digital and Analog Grounds 0 − V

T functional Functional temperature range (Note 2) −40 85 °C

T operational Operational temperature range (Note 2) 0 50 °C

T storage Storage temperature range −40 85 °C

Caution: Class 2 ESD Sensitivity, JESD22*A114*B (2000 V)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

1. In some applications, VDDO can be higher than 2.1 V (maximum 3.3 V). In such cases, the user must set the VDDM voltage at a minimum

of 1.1 V

2. Electrical Specification may exceed listed tolerances when out of the temperature range 0 to 50°C

The tests were performed at 20°C with a 1.25 V supply voltage and 4.7 W series resistor to simulate a nominal hearing aid
battery. The system clock (SYS_CLK) was set to 5.12 MHz and an audio input sampling frequency of 16 kHz was used.
Parameters marked as screened are tested on each chip.

I/O supply voltage 3.3 (Note 1) V

Electrical Performance Specifications

Table 2. ELECTRICAL SPECIFICATIONS

Description Symbol Conditions Min Typ Max Units Screened

OVERALL

Supply Voltage VBAT Supply voltage measured

at the VBAT pin

I/O Supply Voltage
Domain 1,2

I/O Supply Voltage
Domain 3

Current consumption I

VDDO

VDDO

VBAT

1,2

3

Filterbank: 30% load CFX:
100% load SYS_CLK:

10.24 MHz. No activity on
the nRF51822

Ezairo Pre Suite firmware
bundle running at 10.24
MHz, all algorithms active,
no transducers connected,
no activity on the nRF51822.

Stand by current I

stb

Using ON’s macro to put
the Ezairo 7100 DSP in
Standby Mode. Include
30 mA coming from the
nRF51822 standby current.

VREG

Regulated voltage output
Regulator PSRR VREG
Load current I
Load regulation LOAD
Line regulation LINE

VREG

PSRR

LOAD

REG

REG

I

=100 mA

load

1 kHz, VBAT=1.25 V 76 80 − dB

5 mA < Iload < 2 mA
Iload = 1 mA − 2 5 mV/V

VDDA

Output voltage trimming
range

Regulator PSRR VDDA

VDDA Control register configured,

typical values

PSRR

1 kHz, VBAT=1.25V 40 50 − dB

1.05 1.25 2.0 V

1.05 − 3.3 V

1.05 − Vbat V

− 700 −

− 1090 −

70 150

0.96 0.97 0.98 V

− − 2 mA

− 4 10 mV/mA

1.8 2.0 2.1 V

mA

mA

mA

n

n

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EZAIRO 7150 SL HYBRID

Table 2. ELECTRICAL SPECIFICATIONS

Description ScreenedUnitsMaxTypMinConditionsSymbol

VDDA

Load current
Load regulation LOAD

Line regulation LINE

I

LOAD

REG

REG

VBAT = 1.2 V; 100 _A <
Iload < 1 mA

1.2 V < VBAT < 1.86 V;
Iload = 100 uA

VDBL

Output voltage trimming
range

Regulator PSRR VDBL
Load current I

Load regulation LOAD

Line regulation LINE

VDBL Control register configured,

typical values, unloaded

PSRR

LOAD

REG

REG

1 kHz, VBAT=1.25 V 30 40 − dB
ITRIM (A_CP_VDBL_CTRL)

= 0x7
VBAT = 1.2 V; 100 mA <

Iload < 3 mA

VBAT > 1.2 V; Iload = 100 mA

VDDC

Digital supply output volt­age trimming range

VDDC output level adjust­ment

Regulator PSRR VDDC
Load current I
Load regulation LOAD
Line regulation LINE

VDDC Control register configured,

typical values, unloaded

VDDC

STEP

PSRR

LOAD

REG

REG

1 kHz, VBAT=1.25 V 25 30 − dB
Delivered by LDO − − 5 mA

VDDM

Memory supply output volt­age trimming range

VDDM output level adjust­ment

Regulator PSRR VDDM
Load current I
Load regulation LOAD
Line regulation LINE

VDDM Control register configured,

typical values, unloaded

VDDM

STEP

PSRR

LOAD

REG

REG

1 kHz, VBAT=1.25 V 25 30 − dB
Delivered by LDO − − 5 mA

POWER−ON−RESET

POR startup voltage

VBAT

STARTUP

POR shutdown voltage VBAT

SHUTDOWN

INPUT STAGE

Analog input voltage range V

IN

Preamplifier gain PAG 3 dB steps 0 − 36 dB
Preamplifier gain accuracy PAG acc 1 kHz, PAG from 0 to 36 dB −1.5 0 1.5 dB
Input impedance R

IN

Non−0dB preamplifier gains 370 500 725

− − 1 mA

− 4 10 mV/mA

− 6 20 mV/V

1.6 2.0 2.2 V

− − 15 mA

− 4 10 mV/mA

− 6 20 mV/V

0.72 −

1.32 V

(Note 3)

1.5 2.5 3 mV

− 5 10 mV/mA

− 6 12 mV/V

0.82 −

1.32 V

(Note 4)

1.5 2.5 3 mV

− 5 10 mV/mA

− 6 12 mV/V

− 0.9 − V

− 0.88 − V

0 − 2 V

n

n

n

n

n

n (Note 5)
n (Note 6)

n

n

kW n

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Table 2. ELECTRICAL SPECIFICATIONS

Description ScreenedUnitsMaxTypMinConditionsSymbol

INPUT STAGE

Input referred noise

Input Dynamic Range
(Note 7)

Input peak THD+N IN

OUTPUT DRIVER

Maximum peak current I
Output impedance R
Output impedance R
Output dynamic range DO
Output THD+N DO

10−BIT LOW−SPEED A/D

Input voltage range LSAD
INL LSAD
DNL LSAD
Sampling frequency LSAD
Channel sampling frequency LSAD

SIGNAL DETECTION UNIT

Preamplifier gain SDU

IN

IRN

IN

DR

THD+N

DO

DO
DO

THDN

RANGE

CH_SF

DR

INL

DNL

SF

PAG

EZAIRO 7150 SL HYBRID

AIR connected to AGND
Unweighted, 100 Hz to

10 kHz BW
Preamplifier settings:

0 dB 53 −
12 dB 13 −
15 dB 9 −
18 dB 6.6 10.6
21 dB 4.9 −
24 dB 4.3 −
27 dB 3.7 −
30 dB 3.2 −
33 dB 3.2 −
36 dB 3.2 −
AIR connected to AGND

Unweighted, 100 Hz to 10
kHz BW

Preamplifier settings:
0 dB − 86
12 dB − 86
15 dB − 86
18 dB 81 86
21 dB − 85
24 dB − 82
27 dB − 82
30 dB − 80
33 dB − 77
36 dB − 74
Any preamplifier gain

− − −68 dB

−10 dBFS signal at preamp
output, 1kHz.

High Power mode − − 25 mA
Normal mode, Iload = 1 mA − 4.5 5.5
High Power mode − 2.5 4
Normal mode, VBAT=1.25V 90 − − dB
At 1 kHz, −6 dBFS, 8 kHz

− −78 −76 dB
bandwidth, VBAT=1.25V,
normal mode

Peak input voltage 0 − 1.94 V
From GND to 2*VREG −4 − +4 LSB
From GND to 2*VREG −2 − +2 LSB
All channels sequentially − 12.8 − kHz

− 1.6 − kHz

3 dB steps 0 − 36 dB

mVrms

dB

W

W

n

n

n

n

n

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EZAIRO 7150 SL HYBRID

Table 2. ELECTRICAL SPECIFICATIONS

Description ScreenedUnitsMaxTypMinConditionsSymbol

SIGNAL DETECTION UNIT

Equivalent IRN

SDU

IRN

Input impedance SDU
Low Pass Filter Bandwidth SDU
ADC input signal range SDU
ADC resolution SDU
ADC sampling frequency SDU

LPF

RANGE

RES

SF

DIGITAL

Voltage level for high input

Voltage level for low input V
Voltage level for high output V

Voltage level for low output V
Oscillator frequency trim-

V

IH

IL

OH

OL

SYS_CLK −1 − +1 %

ming precision
Oscillator frequency stabili-

SYS_CLK Over temperature range of

ty over temperature
Recommended working

SYS_CLK For recommended VDDC

frequency
Oscillator period jitter RMS at System clock: 1.28

PLL lock time For an input phase error

PLL tracking range −2 − 2 %

LOW DELAY PATH

Group Delay Using the low delay path of

EEPROM

EEPROM burn cycles Per EA2M datasheet 1’000

Current consumption –
writing to EEPROM

Current consumption –
read from EEPROM

I

W

I

R

RADIO ANTENNA MATCHING NETWORK

Optimum differential im­pedance at 2.4 Ghz seen

ZANT1,

ANT2
into the matching network
from pin ANT1 and ANT2

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

3. Recommended VDDC values depend on the system clock (SYS_CLK) frequency. Table 3 gives the recommended VDDC values for different
system clocks.

4. The minimum VDDM value required for proper system functioning is 0.90V

5. Pass fail test with 0.855 V and 0.945 V

6. Pass fail test with 0.835 V and 0.925 V

7. The audio performance might be slightly impacted when the nRF51822 radio is turned on. Degradation depends on the duty cycle of the
communication, on the external components,...

Non−weighted, 30 dB gain,

− − 20

100 Hz − 10 kHz

R

370 500 725 kOhm

50 kHz

Referred to VREG −1 +1 V

12 bits

At slow_clock = 1.28 MHz 1 64 kHz

VDD

− − V

O*0.8

− − VDDO*0.2 V

2 mA source current VDD

− V

O*0.8

2 mA sink current − − VDDO*0.2 V

−1.5 − +1.5 %

0 to 50°C

1.28 − 15.36 MHz

and VDDM

− − 400 ps

MHz, before multiplication

− − 10 ms
<2%, input reference clock
of 128 kHz, output clock of

2.56MHz

− 44 −
the Filter Engine

− − Cycles

000

0.7 mA

0.4 mA

− 12.6 +

j106

mVrms n

n

n

n

n

n

n

n

ms

−

W

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