ON Semiconductor ESDL1531 User manual

ESDL1531

3.3V ESD Protection Diodes

Ultra Low Capacitance ESD Protection
Diode for High Speed Data Line

The ESDL1531 ESD protection diodes are designed to protect high
speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines.

Features

• Low Capacitance (0.15 pF Typ, I/O to GND)

• Protection for the Following IEC Standards:

IEC 61000−4−2 (Level 4)

• Low ESD Clamping Voltage

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

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ESDL1531

X4DFN2 (01005)

CASE 718AA

J = Device Code
M = Date Code

MARKING
DIAGRAM

JM

Typical Applications

• USB 2.0/3.x

• Thunderbolt

• MHL 2.0

• eSATA

MAXIMUM RATINGS (T

Rating

Operating Junction Temperature Range T

Storage Temperature Range T

Lead Solder Temperature −
Maximum (10 Seconds)

IEC 61000−4−2 Contact
IEC 61000−4−2 Air

Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.

See Application Note AND8308/D for further description of
survivability specs.

= 25°C unless otherwise noted)

J

Symbol Value Unit

J

stg

T

L

ESD ±30

−55 to +150 °C

−55 to +150 °C

260 °C

±30

kV
kV

PIN CONFIGURATION

AND SCHEMATIC

12

=

ORDERING INFORMATION

See detailed ordering and shipping information on page 5 of
this data sheet.

© Semiconductor Components Industries, LLC, 2016

May, 2019 − Rev. 0

1 Publication Order Number:

ESDL1531/D

ESDL1531

I

HOLD

I

I

PP

R

DYN

I

T

I

R

I

R

I

T

I

HOLD

−I

PP

DYN

V

)

HOLD

V

RWM

V

V

V

BR

C

ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol Parameter

V

V

V

I

HOLD

R

RWM

HOLD

I

V

Working Peak Voltage

I

Maximum Reverse Leakage Current @ V

R

Breakdown Voltage @ I

BR

I

Test Current

T

Holding Reverse Voltage

Holding Reverse Current

Dynamic Resistance

DYN

Maximum Peak Pulse Current

PP

Clamping Voltage @ I

C

VC = V

HOLD

+ (IPP * R

PP

DYN

T

)

ELECTRICAL CHARACTERISTICS (T

RWM

= 25°C unless otherwise specified)

A

V

BR

V

CVRWMVHOLD

VC = V

R

HOLD

DYN

+ (IPP * R

Parameter Symbol Conditions Min Typ Max Unit

Reverse Working Voltage V

Breakdown Voltage V

Reverse Leakage Current I

Reverse Holding Voltage V

Holding Reverse Current I

Clamping Voltage
TLP (Note 1)

RWM

HOLD

HOLD

V

I/O Pin to GND 3.3 V

IT = 1 mA, I/O Pin to GND 5.5 8.6 V

BR

V

R

= 3.3 V, I/O Pin to GND 1.0

RWM

I/O Pin to GND 2.1 V

I/O Pin to GND 17 mA

IPP = 8 A IEC 61000−4−2 Level 2 equivalent

C

6.5

(±4 kV Contact, ±4 kV Air)

IPP = 16 A

IEC 61000−4−2 Level 2 equivalent

10.2

(±8 kV Contact, ±15 kV Air)

Reverse Peak Pulse Cur­rent

Clamping Voltage (8/20 ms)

Dynamic Resistance R

Junction Capacitance C

I

PP

V

DYN

IEC61000−4−5 (8/20 ms)

IPP = 5.7 A 5.6 6.5 V

C

5.7 7.5 A

I/O Pin to GND 0.46

VR = 0 V, f = 1 MHz 0.15 0.3 pF

J

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

1. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z

= 50 W, tp = 100 ns, tr = 1 ns, averaging window; t1 = 70 ns to t2 = 90 ns.

0

mA

V

W

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2

ESDL1531

TYPICAL CHARACTERISTICS

110

100

90

80

70

60

50

40

VOLTAGE (V)

30
20

10

0

−10

−20 0 20 40 60 80 100 120

TIME (ns)

Figure 1. ESD Clamping Voltage − Pin 1 to Pin 2

8 kV Contact per IEC61000−4−2

10

0

−10

−20

−30

−40

−50

−60

VOLTAGE (V)

−70

−80

−90

−100

−110

−20 0 20 40 60 80 100 120140

TIME (ns)

Figure 2. ESD Clamping Voltage − Pin 2 to Pin 1

8 kV Contact per IEC61000−4−2

140

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3

ESDL1531

TYPICAL CHARACTERISTICS

20

18

16

14

12

(A)

10

TLP

I

8

6

4

2

0

02 4 12

610 6 16

V

(V)

CTLP

(A)

TLP

I

20

18

16

14

12

10

8

6

4

2

0

2812148 16 4 10 140

V

(V)

CTLP

Figure 3. 100 ns TLP I−V Curve − Pin 1 to Pin 2 Figure 4. 100 ns TLP I−V Curve − Pin 2 to Pin 1

10

9

8

7

6

(V)

PK

5

@ I

4

C

V

3

2

1

0

0568

1234

7

IPK (A)

10

(V)

PK

@ I

C

V

9

8

7

6

5

4

3

2

1

0

12 3 40678

5

IPK (A)

Figure 5. Clamping Voltage vs. Peak Pulse

Current − Pin 1 to Pin 2 (t

1E−03

1E−04

1E−05

1E−06

1E−07

(A)

1E−08

R

I

1E−09

1E−10

1E−11

1E−12
1E−13

= 8/20 ms)

p

Figure 7. Reverse Leakage Current

VR (V)

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4

Figure 6. Clamping Voltage vs. Peak Pulse

Current − Pin 2 to Pin 1 (t

842−8 −40−2

6−6

= 8/20 ms)

p

ESDL1531

TYPICAL CHARACTERISTICS

0

−0.2

−0.6

−1.0

−1.4

−1.8

−2.2

S(2,1) MAGNITUDE (dB)

−2.6

−3.0

1E+08

1E+09 1E+10 1E+101E+08 1E+09

FREQUENCY (Hz)

Figure 8. Insertion Loss

0.40

0.35

0.30

0.25

0.20

C (pF)

0.15

0.10

0.05

0

FREQUENCY (Hz)

Figure 9. Capacitance Over Frequency

ORDERING INFORMATION

Device Package Shipping

ESDL1531MX4T5G X4DFN2

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

10,000 / Tape & Reel

†

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5

ESDL1531

IEC 61000−4−2 Spec.

Test Volt-

Level

age (kV)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

First Peak

Current

(A)

Current at

30 ns (A)

Current at

60 ns (A)

Figure 10. IEC61000−4−2 Spec

Transmission Line Pulse (TLP) Measurement

Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 11. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 12 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.

IEC61000−4−2 Waveform

I

peak

100%

90%

I @ 30 ns

I @ 60 ns

10%

tP = 0.7 ns to 1 ns

L

Attenuator

S

50 W Coax

Cable

÷

50 W Coax

Cable

10 MW

V

C

Figure 11. Simplified Schematic of a Typical TLP

System

I

M

V

M

Oscilloscope

DUT

Figure 12. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms

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6

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 10:1

X4DFN2, 0.445x0.24, 0.27P

CASE 718AA

ISSUE A

DATE 21 MAR 2017

PIN 1

REFERENCE

0.03 C

0.03 C

D

TOP VIEW

A1

SIDE VIEW

e

e/2

PIN 1

L2X

BOTTOM VIEW

A
B

E

A

SEATING

C

PLANE

b

2X

2

A0.10 BC

NOTE 3

0.05

C

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. EXPOSED COPPER ALLOWED AS SHOWN.

MILLIMETERS

DIM MIN NOM

A 0.15 0.18

A1 −−− −−−

b 0.170 0.185
D 0.415 0.445
E 0.210 0.240
e 0.270 BSC
L 0.105 0.120

MAX

0.21

0.03

0.200

0.475

0.270

0.135

GENERIC

MARKING DIAGRAMS*

X

X = Specific Device Code

*This information is generic. Please refer to

device data sheet for actual part marking.
Some products may not follow the Generic

X

Marking.

RECOMMENDED

MOUNTING FOOTPRINT*

0.27

PITCH

1

2X

0.21

2X

0.13

DIMENSIONS: MILLIMETERS

See Application Note AND8398/D for more mounting details

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

98AON29067G

X4DFN2, 0.445X0.24, 0.27P

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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© Semiconductor Components Industries, LLC, 2019

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