ON Semiconductor ESD7383 User Manual

ESD7383

ESD Protection

3−Line, Very Low Capacitance

Product Description

The ESD7383 is a 4−bump very low capacitance ESD protection
device in 0.4 mm CSP form factor. It is fully compliant with IEC
61000−4−2. The ESD7383 is RoHS II compliant.

Features

• These Devices are Pb−Free and are RoHS Compliant

Applications

• ESD protection for USB (including USB OTG)

♦ USB compliance

High Speed USB port
Up to 480 Mb/s according to USB 2.0 high speed specification

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ELECTRICAL SCHEMATIC

CH2 (B1)CH1 (A1) CH3 (B2)

GND (A2)

MARKING
DIAGRAM

MAXIMUM RATINGS (T

Rating

Peak Pulse Power Dissipation, 8 x 20 ms

Maximum Peak Pulse Current, 8 x 20 ms

Operating Junction Temperature Range T

Storage Temperature Range T

IEC 61000−4−2 Contact (ESD) ESD ±8000 V

Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.

= 25°C unless otherwise noted)

A

Symbol Value Unit

P

pk

I

PP

J

stg

50 W

2.5 A

−40 to +85 °C

−55 to +150 °C

WLCSP4

CASE 567CB

7 = Specific Device Code
M = Date Code

7M

PINOUT

B1

B

A1

A

12

BOTTOM VIEW

B2

A2

PIN DESCRIPTIONS

Pin Description

A1 ESD Channel 1

A2 Device Ground

B1 ESD Channel 2

B2 ESD Channel 3

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.

© Semiconductor Components Industries, LLC, 2011

October, 2017 − Rev. 1

1 Publication Order Number:

EMD7383/D

ESD7383

ELECTRICAL SPECIFICATIONS AND CONDITIONS

ELECTRICAL OPERATING CHARACTERISTICS (Note 1)

Symbol

V

IN

V

BR

I

R

C

IN

DC

IN

V

CL

Input Operating Supply Voltage 3.0 5.5 V

Breakdown Voltage I

Reverse Leakage Current V

Channel Input Capacitance At 1 MHz, VIN = 0 V 1.5 pF

Channel Input Capacitance Matching At 1 MHz, VIN = 0 V 0.02 pF

Channel Clamp Voltage
Positive Transients

Parameter Conditions

= 8 mA 6 V

T

= 3 V 100 nA

RM

I

= 1 A, tP = 8/20 ms

PP

Negative Transients

R

Dynamic Resistance

DYN

Positive Transients

I

= 1 A, tP = 8/20 ms

PP

Any I/O pin to Ground

Negative Transients

1. All parameters specified at TA = 25°C unless otherwise noted.

ORDERING INFORMATION

Part Number Bumps Variation Part Marking Package Shipping

ESD7383 4 WLCSP4 7 CSP

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

(Pb−Free)

Min Typ Max Unit

+10

−1.5

0.6

0.5

†

5000 / Tape & Reel

V

W
W

Figure 1. ESD Clamping Voltage Screenshot

Positive 8 kV Contact per IEC61000−4−2

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Figure 2. ESD Clamping Voltage Screenshot

Negative 8 kV Contact per IEC61000−4−2

2

ESD7383

IEC61000−4−2 Spec.

Test Volt-

Level

age (kV)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

ESD Gun

First Peak

Current

(A)

Current at

30 ns (A)

Device

Under

Test

50 W

Cable

IEC61000−4−2 Waveform

I

peak

Current at

60 ns (A)

100%

90%

I @ 30 ns

I @ 60 ns

10%

Figure 3. IEC61000−4−2 Spec

Oscilloscope

50 W

tP = 0.7 ns to 1 ns

Figure 4. Diagram of ESD Clamping Voltage Test Setup

The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger

100

t

r

90

80

70

60

50

40

30

20

% OF PEAK PULSE CURRENT

10

0

020406080

PEAK VALUE I

t

P

Figure 5. 8 x 20 ms Pulse Waveform

systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.

@ 8 ms

RSM

PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms

HALF VALUE I

t, TIME (ms)

/2 @ 20 ms

RSM

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3

ESD7383

Figure 6. Positive TLP I−V Curve Figure 7. Negative TLP I−V Curve

Transmission Line Pulse (TLP) Measurement

Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. A typical TLP I−V
curve for the ESD7383 is shown in Figures 6 and 7.

L

Attenuator

S

50 W Coax

Cable

÷

50 W Coax

Cable

Figure 8. Simplified Schematic of a Typical TLP

10 MW

V

C

System

I

M

V

M

Oscilloscope

DUT

Figure 9. Comparison Between 8 kV IEC61000−4−2 and 8 A and 16 A TLP Waveforms

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4

ESD7383

Figure 10. 480 Mb/s USB Source

Clears USB 2.0 Hi Speed Mask

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5

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 4:1

PIN A1

REFERENCE

2X

2X

0.05 C

0.05

0.05 C

D

C

TOP VIEW

A

B

E

A2

WLCSP4, 0.8x0.8

CASE 567CB−01

ISSUE O

DATE 26 JUL 2010

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.

MILLIMETERS

DIMAMIN MAX

A1
A2 0.41 REF

b 0.24 0.29

D 0.80 BSC

E
e 0.40 BSC

0.63

0.57

0.17 0.24

0.80 BSC

NOTE 3

0.03

0.05 C

4X

A0.05 BC

C

A1

SIDE VIEW

b

B

A

12

BOTTOM VIEW

A

RECOMMENDED

SOLDERING FOOTPRINT*

C

SEATING
PLANE

A1

e

e

0.40
PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

0.40
PITCH

PACKAGE
OUTLINE

4X

0.25

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019

98AON50305E

WLCSP4, 0.8X0.8

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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