ON Semiconductor ESD7361, SZESD7361 User Manual

ESD7361, SZESD7361

ESD Protection Diode

Low Capacitance ESD Protection Diode for High Speed Data Line

The ESD7361 Series ESD protection diodes are designed to protect high speed data lines from ESD. Ultra−low capacitance make this device an ideal solution for protecting voltage sensitive high speed data lines.

Features

• Low Capacitance (0.55 pF Max, I/O to GND)

• Protection for the Following IEC Standards:

♦ IEC61000−4−2 (ESD): Level 4 ±15 kV Contact ♦ IEC61000−4−4 (EFT): 40 A −5/50 ns ♦ IEC61000−4−5 (Lightning): 1 A (8/20 ms)

• ISO 10605 (ESD) 330 pF/2 kW ±15 kV Contact

• SZ Prefix for Automotive and Other Applications Requiring Unique

Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

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MARKING

DIAGRAMS

SOD−323

CASE 477

SOD−523

CASE 502

SOD−923

CASE 514AB

2 M

Typical Applications

• Wireless Charger

• Near Field Communications

MAXIMUM RATINGS (T

Rating

Operating Junction Temperature Range T Storage Temperature Range T Lead Solder Temperature −

Maximum (10 Seconds) IEC 61000−4−2 Contact (ESD)

IEC 61000−4−2 Air (ESD) ISO 10605 330 pF/2 kW Contact (ESD)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

= 25°C unless otherwise noted)

Symbol Value Unit

stg

ESD ESD ESD

−55 to +125 °C

−55 to +150 °C 260 °C

±15 ±15 ±15

kV kV kV

X, XX = Specific Device Code M = Date Code

PIN CONFIGURATION

AND SCHEMATIC

Cathode

Anode

ORDERING INFORMATION

See detailed ordering and shipping information on page 6 o this data sheet.

August, 2018 − Rev. 5

1 Publication Order Number:

ESD7361/D

ESD7361, SZESD7361

ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol

RWM

Maximum Reverse Peak Pulse Current Clamping Voltage @ I

Working Peak Reverse Voltage Maximum Reverse Leakage Current @ V

Breakdown Voltage @ I

Test Current

*See Application Note AND8308/D for detailed explanations of

datasheet parameters.

Parameter

RWM

VCV

RWM

Uni−Directional

RWM

BR R

C C

DYN

= 25°C unless otherwise specified)

5 16 V IT = 1 mA; pin 1 to pin 2 16.5 V V

RWM RWM

= 5.0 V = 15 V

<1 20

1000

1000 IPP = 8 A 31 V IPP = 16 A 34 V VR = 0 V, f = 1 MHz

= 0 V, f < 1 GHz

0.55

TLP Pulse 0.735

0.01

f = 5 GHz

ELECTRICAL CHARACTERISTICS (T

Parameter

Reverse Working Voltage V Breakdown Voltage V Reverse Leakage Current I

Clamping Voltage (Note 2) V Clamping Voltage (Note 2) V Junction Capacitance C

Dynamic Resistance R Insertion Loss f = 1 MHz

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

1. For test procedure see Figures 9 and 10 and application note AND8307/D.

2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z

= 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.

Symbol Conditions Min Typ Max Unit

nA nA

1.E−03

1.E−04

1.E−05

1.E−06

1.E−07

1.E−08

1.E−09

CURRENT (A)

1.E−10

1.E−11

1.E−12

1.E−13 0 5 10 15 20 25 30

0.8

0.6

0.4

CAPACITANCE (pF)

0.2

VOLTAGE (V)

61012

(V)

Bias

14 182

Figure 1. Typical IV Characteristics Figure 2. Typical CV Characteristics

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ESD7361, SZESD7361

0.5 0

−0.5

−1

−1.5

S21 (dB)

−2

−2.5

−3

−3.5

−4

1.E+07 1.E+08 1.E+09 FREQUENCY (Hz)

Figure 3. Typical Insertion Loss

ESD7361HT1G (SOD323)

0.5 0

−0.5

−1

−1.5

−2

S21 (dB)

−2.5

−3

−3.5

−4

1.E+07 1.E+08 1.E+09 FREQUENCY (Hz)

Figure 5. Typical Insertion Loss

ESD7361XV2T1G (SOD523)

0.9

0.8

0.7

0.6

0.5

0.4

0.3

CAPACITANCE (pF)

0.2

0.1 0

1.E+07 5.E+08 1.E+09 2.E+09 2.E+09 3.E+09

FREQUENCY (Hz)

Figure 4. Typical Capacitance Over Frequency

ESD7361HT1G (SOD323)

0.9

0.8

0.7

0.6

0.5

0.4

0.3

CAPACITANCE (pF)

0.2

0.1 0

1.E+07 1.E+09 2.E+09 3.E+09

FREQUENCY (Hz)

4.E+09

Figure 6. Typical Capacitance Over Frequency

ESD7361XV2T1G (SOD523)

−0.5

−1.5

S21 (dB)

−2.5

−3.5

0.5 0

−1

−2

−3

−4

1.E+07

1.E+08 1.E+09 FREQUENCY (Hz)

Figure 7. Typical Insertion Loss

ESD7361P2T5G (SOD923)

0.9

0.8

0.7

0.6

0.5

0.4

CURRENT (A)

0.3

0.2

0.1 0

1.E+07 1.E+09 2.E+09 3.E+09 4.E+09

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FREQUENCY (Hz)

Figure 8. Typical Capacitance Over Frequency

ESD7361P2T5G (SOD923)

ESD7361, SZESD7361

IEC 61000−4−2 Spec.

Test Volt-

Level

age (kV)

1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8

ESD Gun

First Peak

Current

(A)

Current at

30 ns (A)

Device

Under

Test

50 W Cable

IEC61000−4−2 Waveform

peak

Current at

60 ns (A)

100%

90%

I @ 30 ns

I @ 60 ns

10%

Figure 9. IEC61000−4−2 Spec

Oscilloscope

50 W

tP = 0.7 ns to 1 ns

Figure 10. Diagram of ESD Clamping Voltage Test Setup

The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D.

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ESD7361, SZESD7361

TLP CURRENT (A)

040353051015 2520

VC, VOLTAGE (V)

Figure 11. Positive TLP I−V Curve

NOTE: TLP parameter: Z

stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description below for more information.

= 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. V

Transmission Line Pulse (TLP) Measurement

Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 13. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 14 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels.

−25

−20

−15

−10

TLP CURRENT (A)

−5

0 −14−12−10−2 −4 −6 −8

VC, VOLTAGE (V)

Figure 12. Negative TLP I−V Curve

is the equivalent voltage

IEC

Attenuator

50 W Coax

Cable

10 MW

Figure 13. Simplified Schematic of a Typical TLP

System

Oscilloscope

50 W Coax

Cable

DUT

Figure 14. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms

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ESD7361, SZESD7361

ORDERING INFORMATION

Device Package Shipping

ESD7361HT1G SZESD7361HT1G* ESD7361XV2T1G SZESD7361XV2T1G* ESD7361XV2T5G SZESD7361XV2T5G* ESD7361P2T5G SZESD7361P2T5G*

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP

Capable.

SOD−323 (Pb−Free)

SOD−523 (Pb−Free)

SOD−923 (Pb−Free)

3000 / Tape & Reel

8000 / Tape & Reel

†

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

STYLE 1 STYLE 2

SCALE 4:1

NOTE 3

NOTE 5

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

0.63

0.025

1.60

0.063

2.85

0.112

SOD−323

CASE 477−02

ISSUE H

0.83

0.033

DATE 13 MAR 2007

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. LEAD THICKNESS SPECIFIED PER L/F DRAWING WITH SOLDER PLATING.

4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

5. DIMENSION L IS MEASURED FROM END OF RADIUS.

MILLIMETERS

DIM MIN NOM MAX

A 0.80 0.90 1.00 A1 0.00 0.05 0.10 A3 0.15 REF

b 0.25 0.32 0.4 C 0.089 0.12 0.177 D 1.60 1.70 1.80

E 1.15 1.25 1.35

0.08

2.30 2.50 2.70

INCHES

MIN NOM MAX

0.031 0.035 0.040

0.000 0.002 0.004

0.006 REF

0.010 0.012 0.016

0.003 0.005 0.007

0.062 0.066 0.070

0.045 0.049 0.053

0.003

0.090 0.098 0.105

GENERIC

MARKING DIAGRAM*

XX M

STYLE 1 STYLE 2

XX = Specific Device Code M = Date Code

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present.

STYLE 1:

PIN 1. CATHODE (POLARITY BAND)

2. ANODE

XX M

STYLE 2:

NO POLARITY

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB17533C

SOD−323

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

STYLE 1 STYLE 2

SCALE 4:1

b2X

0.08 X Y

−X−

−Y−

TOP VIEW

SIDE VIEW

SOD−523

CASE 502−01

ISSUE E

DATE 28 SEP 2010

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.

DIM MIN NOM MAX

A 0.50 0.60 0.70 b 0.25 0.30 0.35 c 0.07 0.14 0.20 D 1.10 1.20 1.30 E 0.70 0.80 0.90

H 1.50 1.60 1.70

L 0.30 REF

L2 0.15 0.20 0.25

MILLIMETERS

GENERIC

MARKING DIAGRAM*

STYLE 1 STYLE 2

BOTTOM VIEW

RECOMMENDED

SOLDERING FOOTPRINT*

0.48

PACKAGE

OUTLINE

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

DOCUMENT NUMBER:

DESCRIPTION:

1.80

0.40

DIMENSION: MILLIMETERS

98AON11524D

SOD−523

XX = Specific Device Code M Date Code

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present.

STYLE 1:

PIN 1. CATHODE (POLARITY BAND)

2. ANODE

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

STYLE 2:

NO POLARITY

PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

STYLE 1 STYLE 2

SCALE 8:1

0.08 XY

b2X

TOP VIEW

SIDE VIEW

−X−

−Y−

SOD−923

CASE 514AB

ISSUE D

DATE 03 SEP 2020

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.

5. DIMENSION L WILL NOT EXCEED 0.30mm.

MILLIMETERS

DIM MIN NOM MAX

A 0.34 0.37 0.40 b 0.15 0.20 0.25 c 0.07 0.12 0.17 D 0.75 0.80 0.85 E 0.55 0.60 0.65

0.95 1.00 1.05

L 0.19 REF

L2 0.05 0.10 0.15 0.002 0.004 0.006

INCHES

MIN NOM MAX

0.013 0.015 0.016

0.006 0.008 0.010

0.003 0.005 0.007

0.030 0.031 0.033

0.022 0.024 0.026

0.037 0.039 0.041

0.007 REF

GENERIC

MARKING DIAGRAM*

BOTTOM VIEW

SOLDERING FOOTPRINT*

0.36

PACKAGE

OUTLINE

See Application Note AND8455/D for more mounting details

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

1.20

0.25

DIMENSIONS: MILLIMETERS

X M

STYLE 1 STYLE 2

X = Specific Device Code M = Date Code

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present.

STYLE 1:

PIN 1. CATHODE (POLARITY BAND)

2. ANODE

STYLE 2:

NO POLARITY

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98AON23284D

SOD−923, 1.0X0.6X0.37, MAX HEIGHT 0.40

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

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ON Semiconductor ESD7361, SZESD7361 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual