ESD7351, SZESD7351
Series
ESD Protection Diode
The ESD7351 Series is designed to protect voltage sensitive
components that require ultra−low capacitance from ESD and
transient voltage events. Excellent clamping capability, low
capacitance, low leakage, and fast response time, make these parts
ideal for ESD protection on designs where board space is at a
premium. Because of its low capacitance, it is suited for use in high
frequency designs such as USB 2.0 high speed and antenna line
applications.
Features
• Low Capacitance (0.6 pF Max, I/O to GND)
• Low Clamping Voltage
• Stand−off Voltage: 3.3 V
• Low Leakage
• Response Time is < 1 ns
• Low Dynamic Resistance < 1 W
• IEC61000−4−2 Level 4 ESD Protection
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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2
1
1
SOD−323
CASE 477
2
SOD−523
CASE 502
SOD−923
CASE 514AB
X, XX = Specific Device Code
M = Date Code
MARKING
DIAGRAMS
AF
M
AE
M
12
AD M
Typical Applications
• RF Signal ESD Protection
• RF Switching, PA, and Antenna ESD Protection
• Near Field Communications
MAXIMUM RATINGS
Rating Symbol Value Unit
IEC 61000−4−2 (ESD) Contact
Total Power Dissipation on FR−5 Board
(Note 1) @ T
Junction and Storage Temperature Range TJ, T
Lead Solder Temperature − Maximum
(10 Second Duration)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
= 25°C
A
Air
°PD° 150 mW
stg
T
L
See Application Note AND8308/D for further description of survivability specs.
±20
±20
−55 to +150 °C
260 °C
kV
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
PIN CONFIGURATION
AND SCHEMATIC
1
Cathode
ORDERING INFORMATION
2
Anode
© Semiconductor Components Industries, LLC, 2014
November, 2018 − Rev. 5
1 Publication Order Number:
ESD7351/D
ESD7351, SZESD7351 Series
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol
V
I
PP
V
RWM
I
V
I
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
C
Working Peak Reverse Voltage
Maximum Reverse Leakage Current @ V
R
Breakdown Voltage @ I
BR
Test Current
T
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
Parameter
PP
RWM
T
VCV
BR
V
RWM
I
I
F
I
V
R
F
I
T
I
PP
V
Uni−Directional
ELECTRICAL CHARACTERISTICS (T
Parameter
Reverse Working Voltage V
Breakdown Voltage (Note 2) V
Reverse Leakage Current I
Clamping Voltage (Note 3) V
Clamping Voltage (Note 3) V
Junction Capacitance C
Dynamic Resistance R
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Breakdown voltage is tested from pin 1 to 2.
3. Non−repetitive current pulse at T
Symbol Conditions Min Typ Max Unit
A
= 25°C unless otherwise specified)
A
RWM
IT = 1 mA 5.0 V
BR
V
R
C
C
J
DYN
= 25°C, per IEC61000−4−5 waveform.
= 3.3 V < 1.0 50 nA
RWM
IPP = 1 A 8.0 V
IPP = 3 A 10 V
VR = 0 V, f = 1 MHz
V
= 0 V, f < 1 GHz
R
TLP Pulse 0.35
0.43
0.43
3.3 V
0.6
0.6
pF
W
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2
ESD7351, SZESD7351 Series
1.E−03
1.E−04
1.E−05
1.E−06
1.E−07
I (A)
1.E−08
1.E−09
1.E−10
1.E−11
1.E−12
dB
−10
−12
−14
012345678
V (V)
Figure 1. IV Characteristics Figure 2. CV Characteristics
2
0
−2
−4
−6
−8
1.E+08 1.E+09 1.E+10
TBD
FREQUENCY (Hz)
Figure 3. RF Insertion Loss Figure 4. Capacitance over Frequency
1.0
0.8
0.6
0.4
CAPACITANCE (pF)
0.2
0
0 0.5 1 1.5 2 2.5 3 3.5
VBias (V)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
CAPACITANCE (pF)
0.4
0.2
0.0
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5
FREQUENCY (GHz)
16
14
12
10
8
6
TLP CURRENT (A)
4
2
0
02468101214161820
VC, VOLTAGE (V)
Figure 5. Positive TLP I−V Curve
NOTE: TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. V
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
8
−14
6
−12
(kV)
−10
IEC
4
−8
−6
TLP CURRENT (A)
2
−4
EQUIVALENT V
−2
0
0
02468101214161820
VC, VOLTAGE (V)
Figure 6. Negative TLP I−V Curve
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3
is the equivalent voltage
IEC
8−16
6
4
2
0
(kV)
IEC
EQUIVALENT V
ESD7351, SZESD7351 Series
IEC 61000−4−2 Spec.
Test Volt-
Level
age (kV)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
ESD Gun
First Peak
Current
(A)
Current at
30 ns (A)
Device
Under
Test
50 W
Cable
IEC61000−4−2 Waveform
I
peak
Current at
60 ns (A)
100%
90%
I @ 30 ns
I @ 60 ns
10%
Figure 7. IEC61000−4−2 Spec
Oscilloscope
50 W
tP = 0.7 ns to 1 ns
Figure 8. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 9. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 10 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
L
Attenuator
S
50 W Coax
Cable
÷
50 W Coax
Cable
10 MW
V
C
Figure 9. Simplified Schematic of a Typical TLP
System
I
M
V
M
Oscilloscope
DUT
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4
ESD7351, SZESD7351 Series
Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
ORDERING INFORMATION
Device Package Shipping
ESD7351HT1G,
SZESD7351HT1G*
ESD7351XV2T1G,
SZESD7351XV2T1G*
ESD7351XV2T5G,
SZESD7351XV2T5G*
ESD7351P2T5G,
SZESD7351P2T5G*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
SOD−323
(Pb−Free)
SOD−523
(Pb−Free)
SOD−523
(Pb−Free)
SOD−923
(Pb−Free)
3000 / Tape & Reel
3000 / Tape & Reel
8000 / Tape & Reel
8000 / Tape & Reel
†
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
2
1
1
STYLE 1 STYLE 2
SCALE 4:1
1
b
C
NOTE 3
NOTE 5
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
2
H
E
D
E
2
L
A1
0.63
0.025
1.60
0.063
2.85
0.112
SOD−323
CASE 477−02
ISSUE H
0.83
0.033
A3
DATE 13 MAR 2007
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. LEAD THICKNESS SPECIFIED PER L/F DRAWING
WITH SOLDER PLATING.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
5. DIMENSION L IS MEASURED FROM END OF RADIUS.
MILLIMETERS
DIM MIN NOM MAX
A 0.80 0.90 1.00
A1 0.00 0.05 0.10
A3 0.15 REF
b 0.25 0.32 0.4
C 0.089 0.12 0.177
D 1.60 1.70 1.80
A
E 1.15 1.25 1.35
0.08
L
H
2.30 2.50 2.70
E
INCHES
MIN NOM MAX
0.031 0.035 0.040
0.000 0.002 0.004
0.006 REF
0.010 0.012 0.016
0.003 0.005 0.007
0.062 0.066 0.070
0.045 0.049 0.053
0.003
0.090 0.098 0.105
GENERIC
MARKING DIAGRAM*
XX M
STYLE 1 STYLE 2
XX = Specific Device Code
M = Date Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
STYLE 1:
PIN 1. CATHODE (POLARITY BAND)
2. ANODE
XX M
STYLE 2:
NO POLARITY
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
98ASB17533C
SOD−323
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
2
1
1
STYLE 1 STYLE 2
SCALE 4:1
b2X
M
0.08 X Y
c
2
−X−
D
−Y−
E
12
TOP VIEW
A
H
E
SIDE VIEW
2X
L
SOD−523
CASE 502−01
ISSUE E
DATE 28 SEP 2010
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.
DIM MIN NOM MAX
A 0.50 0.60 0.70
b 0.25 0.30 0.35
c 0.07 0.14 0.20
D 1.10 1.20 1.30
E 0.70 0.80 0.90
H 1.50 1.60 1.70
L 0.30 REF
L2 0.15 0.20 0.25
MILLIMETERS
E
GENERIC
MARKING DIAGRAM*
XX
M
12
STYLE 1 STYLE 2
XX
M
12
2X
L2
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
2X
0.48
PACKAGE
OUTLINE
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
1.80
2X
0.40
DIMENSION: MILLIMETERS
98AON11524D
SOD−523
XX = Specific Device Code
M Date Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
STYLE 1:
PIN 1. CATHODE (POLARITY BAND)
2. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
STYLE 2:
NO POLARITY
PAGE 1 OF 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
STYLE 1 STYLE 2
SCALE 8:1
0.08 XY
b2X
TOP VIEW
c
H
SIDE VIEW
−X−
D
−Y−
E
21
A
E
2X
L
SOD−923
CASE 514AB
ISSUE D
DATE 03 SEP 2020
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
5. DIMENSION L WILL NOT EXCEED 0.30mm.
MILLIMETERS
DIM MIN NOM MAX
A 0.34 0.37 0.40
b 0.15 0.20 0.25
c 0.07 0.12 0.17
D 0.75 0.80 0.85
E 0.55 0.60 0.65
H
0.95 1.00 1.05
E
L 0.19 REF
L2 0.05 0.10 0.15 0.002 0.004 0.006
INCHES
MIN NOM MAX
0.013 0.015 0.016
0.006 0.008 0.010
0.003 0.005 0.007
0.030 0.031 0.033
0.022 0.024 0.026
0.037 0.039 0.041
0.007 REF
GENERIC
MARKING DIAGRAM*
2X
L2
BOTTOM VIEW
SOLDERING FOOTPRINT*
2X
0.36
PACKAGE
OUTLINE
See Application Note AND8455/D for more mounting details
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
1.20
2X
0.25
DIMENSIONS: MILLIMETERS
X M
X M
STYLE 1 STYLE 2
X = Specific Device Code
M = Date Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
STYLE 1:
PIN 1. CATHODE (POLARITY BAND)
2. ANODE
STYLE 2:
NO POLARITY
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
98AON23284D
SOD−923, 1.0X0.6X0.37, MAX HEIGHT 0.40
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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