ESD7205
ESD Protection Diode
Low Capacitance ESD Protection Diodes
for High Speed Data Line
The ESD7205 ESD protection diode array is designed to protect
high speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines. The small form factor,
flow−through style package allows for easy PCB layout and matched
trace lengths necessary to maintain consistent impedance between
high speed differential lines such as Ethernet and LVDS present in
automotive camera modules.
Features
• Low Capacitance (0.4 pF Typical, I/O to GND)
• Diode capacitance matching
• Protection for the Following IEC Standards:
IEC 61000−4−2 Level 4 (ESD)
• Low ESD Clamping Voltage (12 V Typical, +16 A TLP, I/O to GND)
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• 100BASE−T1 / OPEN Alliance BroadR−Reach Automotive Ethernet
• 10/100/1000BASE−T1 Ethernet
• LVDS
• Automotive USB 2.0/3.0
• High Speed Differential Pairs
www.onsemi.com
MARKING
DIAGRAMS
SOT−723
CASE 631AA
EA = Specific Device Code
M = Date Code
SC−70
CASE 419
EC = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONFIGURATION
AND SCHEMATIC
Pin 1 Pin 2
EA M
1
ECMG
1
G
MAXIMUM RATINGS (T
Rating Symbol Value Unit
Operating Junction Temperature Range T
Storage Temperature Range T
Lead Solder Temperature −
Maximum (10 Seconds)
IEC 61000−4−2 Contact
IEC 61000−4−2 Air
ISO 10605 330 pF / 330 W Contact
ISO 10605 330 pF / 2 kW Contact
ISO 10605 150 pF / 2 kW Contact
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2016
January, 2019 − Rev. 6
= 25°C unless otherwise noted)
J
J
stg
T
L
ESD ±25
−55 to +150 °C
−55 to +150 °C
260 °C
kV
±25
±20
±30
±30
1 Publication Order Number:
Pin 3
=
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 6 of this data sheet.
ESD7205/D
ESD7205
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol
V
I
PP
V
RWM
I
V
I
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
C
Working Peak Reverse Voltage
Maximum Reverse Leakage Current @ V
R
Breakdown Voltage @ I
BR
Test Current
T
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
Parameter
PP
RWM
T
VCV
BR
V
RWM
I
I
F
I
V
R
F
I
T
I
PP
Uni−Directional
ELECTRICAL CHARACTERISTICS (T
Parameter
Reverse Working
Voltage
Breakdown Voltage V
Reverse Leakage
Current
Clamping Voltage
(Note 1)
Clamping Voltage TLP
(Note 2)
Junction Capacitance
Match
Junction Capacitance C
3dB Bandwidth f
1. For test procedure see Figures 5 and 6 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z
0
Symbol Conditions Min Typ Max Unit
V
RWM
BR
I
R
V
C
V
C
DC
J
J
BW
= 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
= 25°C unless otherwise specified)
A
I/O Pin to GND 5.0 V
I
= 1 mA, I/O Pin to GND 5.2 6.0 8.0 V
T
V
= 5.0 V, I/O Pin to GND 1
RWM
IEC61000−4−2, ±8 kV Contact See Figures 3 and 4
IPP = 8 A
I
= 16 A
PP
= −8 A
I
PP
IPP = −16 A
VR = 0 V, f = 1 MHz between I/O1 to GND and I/O
2 to GND
VR = 0 V, f = 1 MHz between I/O Pins and GND
ESD7205DT5G
ESD7205WTT1G
VR = 0 V, f = 1 MHz between I/O Pins
ESD7205DT5G
ESD7205WTT1G
RL = 50 W
12.5
−4.0
−8.0
0.34
0.47
0.20
0.23
V
mA
10
5 10 %
pF
0.55
0.85
0.35
0.40
5 GHz
V
www.onsemi.com
2
ESD7205
1.E−02
1.E−03
1.E−04
1.E−05
1.E−06
1.E−07
I (A)
1.E−08
1.E−09
1.E−10
1.E−11
1.E−12
−10 1 2 3 4 5 6 7
−2104
V (V)
1.0
0.9
0.8
0.7
0.6
0.5
C (pF)
0.4
0.3
0.2
0.1
I/O−GND
0
0123 589
VBias (V)
Figure 1. IV Characteristics Figure 2. CV Characteristics
90
80
70
60
50
40
30
VOLTAGE (V)
20
10
0
−10
−20
0
20 40 60 80 100 120 140
TIME (ns)
Figure 3. IEC61000−4−2 +8 kV Contact ESD
Clamping Voltage
10
0
−10
−20
−30
−40
−50
VOLTAGE (V)
−60
−70
−80
−90
−20
0 20 40 80 120 140
TIME (ns)
10060
Figure 4. IEC61000−4−2 −8 kV Contact ESD
Clamping Voltage
www.onsemi.com
3
ESD7205
IEC 61000−4−2 Spec.
Test Volt-
Level
age (kV)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
ESD Gun
First Peak
Current
(A)
Current at
30 ns (A)
Device
Under
Test
50 W
Cable
IEC61000−4−2 Waveform
I
peak
Current at
60 ns (A)
100%
90%
I @ 30 ns
I @ 60 ns
10%
Figure 5. IEC61000−4−2 Spec
Oscilloscope
50 W
tP = 0.7 ns to 1 ns
Figure 6. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
www.onsemi.com
4
ESD7205
20
18
16
14
12
10
8
6
TLP CURRENT (A)
4
2
0
02 1816141246810
VOLTAGE (V)
Figure 7. Positive TLP IV Curve
NOTE: TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns.
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
20
10
−20
−18
8
−16
−14
(kV)
IEC
6
−12
−10
4
−8
−6
TLP CURRENT (A)
EQUIVALENT V
−4
2
−2
0
0
02 1816141246810 20
VOLTAGE (V)
Figure 8. Negative TLP IV Curve
L
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
50 W Coax
Cable
10 MW
system is shown in Figure 9. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
V
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 10 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
Figure 9. Simplified Schematic of a Typical TLP
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
Attenuator
S
C
System
÷
I
M
Oscilloscope
50 W Coax
Cable
V
M
DUT
10
8
6
4
2
0
(kV)
IEC
EQUIVALENT V
Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
www.onsemi.com
5
ESD7205
1
0
−1
−2
−3
−4
dB
−5
−6
−7
−8
−9
−10
1.E+06 1.E+07 1.E+08 1.E+09 1.E+10
FREQUENCY (Hz)
0.6
0.5
0.4
0.3
0.2
CAPACITANCE (pF)
0.1
0.0
0.E+00 5.E+08 1.E+09 2.E+09 2.E+09 3.E+09 3.E+09
0 V
3.3 V
FREQUENCY
Figure 11. RF Insertion Loss Figure 12. Capacitance over Frequency
ORDERING INFORMATION
Device Package Shipping
ESD7205DT5G SOT−723
(Pb−Free)
SZESD7205DT5G* SOT−723
(Pb−Free)
ESD7205WTT1G SOT−323
(Pb−Free)
SZESD7205WTT1G* SOT−323
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
8000 / Tape & Reel
8000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
†
www.onsemi.com
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SCALE 4:1
D
e1
3
E
b
A
0.05 (0.002)
H
E
12
e
A1
SC−70 (SOT−323)
CASE 419−04
ISSUE N
A2
DATE 11 NOV 2008
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIMAMIN NOM MAX MIN
A1 0.00 0.05 0.10 0.000
A2 0.70 REF
b 0.30 0.35 0.40 0.012
c 0.10 0.18 0.25 0.004
D 1.80 2.10 2.20 0.071
E 1.15 1.24 1.35 0.045
e 1.20 1.30 1.40 0.047
e1
L
H
E
MILLIMETERS
0.80 0.90 1.00 0.032
0.65 BSC
0.38
0.20 0.56
2.00 2.10 2.40 0.079 0.083 0.095
INCHES
NOM MAX
0.035 0.040
0.002 0.004
0.028 REF
0.014 0.016
0.007 0.010
0.083 0.087
0.049 0.053
0.051 0.055
0.026 BSC
0.015
0.008 0.022
c
GENERIC
L
MARKING DIAGRAM
SOLDERING FOOTPRINT*
0.65
0.65
0.025
0.9
0.035
0.7
0.028
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLE 1:
STYLE 6:
PIN 1. EMITTER
2. BASE
3. COLLECTOR
CANCELLED
STYLE 2:
PIN 1. ANODE
2. N.C.
3. CATHODE
STYLE 7:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
0.025
1.9
0.075
SCALE 10:1
STYLE 3:
PIN 1. BASE
STYLE 8:
PIN 1. GATE
2. SOURCE
3. DRAIN
ǒ
inches
2. EMITTER
3. COLLECTOR
mm
Ǔ
STYLE 4:
STYLE 9:
PIN 1. CATHODE
2. CATHODE
3. ANODE
PIN 1. ANODE
2. CATHODE
3. CATHODE-ANODE
XX MG
G
1
XX = Specific Device Code
M = Date Code
G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
STYLE 5:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. ANODE-CATHODE
STYLE 11:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
98ASB42819B
SC−70 (SOT−323)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SCALE 4:1
−X−
D
2X
b1
3
1
e
TOP VIEW
1
−Y−
E
2
b
2X
X0.08 Y
3X
L
SOT−723
CASE 631AA−01
ISSUE D
A
H
E
C
SIDE VIEW
DATE 10 AUG 2009
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MILLIMETERS
DIM MIN NOM MAX
A 0.45 0.50 0.55
b 0.15 0.21 0.27
b1 0.25 0.31 0.37
C 0.07 0.12 0.17
D 1.15 1.20 1.25
E 0.75 0.80 0.85
e
H 1.15 1.20 1.25
L
L2 0.15 0.20 0.25
0.40 BSC
E
0.29 REF
3X
L2
BOTTOM VIEW
STYLE 1:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
STYLE 2:
PIN 1. ANODE
2. N/C
3. CATHODE
STYLE 3:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 4:
RECOMMENDED
SOLDERING FOOTPRINT*
2X
0.40
2X
0.27
PACKAGE
OUTLINE
1.50
3X
0.52
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
0.36
DIMENSIONS: MILLIMETERS
PIN 1. CATHODE
2. CATHODE
3. ANODE
STYLE 5:
PIN 1. GATE
2. SOURCE
3. DRAIN
GENERIC
MARKING DIAGRAM*
XX M
1
XX = Specific Device Code
M = Date Code
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
98AON12989D
SOT−723
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
www.onsemi.com
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
. ON Semiconductor reserves the right to make changes without further notice to any products herein.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
◊
www.onsemi.com
1
Loading...