ON Semiconductor ESD7016, SZESD7016 User Manual

ESD7016, SZESD7016

ESD Protection Diode

Low Capacitance, USB 3.0

The ESD7016 surge protection is specifically designed to protect
USB3.0 interfaces by integrating two Superspeed pairs, D+, D−, and
Vbus lines into a single protection product. Ultra−low capacitance and
low ESD clamping voltage make this device an ideal solution for
protecting voltage sensitive high speed data lines. The flow−through
style package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines.

Features

• Low Capacitance (0.15 pF Typical, I/O to GND)

• Protection for the Following IEC Standards:

IEC 61000−4−2 (Level 4)

• Low ESD Clamping Voltage

• SZ Prefix for Automotive and Other Applications Requiring Unique

Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable

• This is a Pb−Free Device

Typical Applications

• USB 3.0

MAXIMUM RATINGS (T

Rating

Operating Junction Temperature Range T

Storage Temperature Range T

Lead Solder Temperature −
Maximum (10 Seconds)

IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)

Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.

= 25°C unless otherwise noted)

J

Symbol Value Unit

J

stg

T

L

ESD
ESD

−55 to +125 °C

−55 to +150 °C

260 °C

±15
±15

kV
kV

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UDFN8

CASE 517CB

1

6M = Specific Device Code
M = Date Code
G = Pb−Free Package

(Note: Microdot may be in either location)

PIN CONFIGURATION

AND SCHEMATIC

I/O 1

I/O 2

N/C

N/C

Vbus or Ground

I/O 3

I/O 4

I/O 5

I/O 6

ORDERING INFORMATION

Device Package Shipping

ESD7016MUTAG UDFN8

(Pb−Free)

MARKING
DIAGRAM

6M MG

G

3000 / Tape &

Reel

© Semiconductor Components Industries, LLC, 2013

October, 2017 − Rev. 4

SZESD7016MUTAG UDFN8

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

1 Publication Order Number:

3000 / Tape &

Reel

ESD7016/D

ESD7016, SZESD7016

RWM

BR

R

C

C

V

C

J

= 25°C unless otherwise specified)

A

I/O Pin to GND 5.0 V

IT = 1 mA, I/O Pin to GND 5.5 V

V

= 5 V, I/O Pin to GND 1.0

RWM

IPP = 1 A, I/O Pin to GND (8 x 20 ms pulse)

IEC61000−4−2, ±8 kV Contact See Figures 1 and 2 V

IPP = ±8 A
I

= ±16 A

PP

14.6

20.5

VR = 0 V, f = 1 MHz between I/O Pins and GND 0.15 0.20 pF

VR = 0 V, f = 1 MHz between I/O Pins and GND 0.03 pF

J

ELECTRICAL CHARACTERISTICS (T

Parameter

Reverse Working Voltage V

Breakdown Voltage V

Reverse Leakage Current I

Clamping Voltage (Note 1) V

Clamping Voltage (Note 2) V

Clamping Voltage
TLP (Note 3)
See Figures 6 through 9

Junction Capacitance C

Junction Capacitance
Difference

Symbol Conditions Min Typ Max Unit

DC

1. Surge current waveform per Figure 5.

2. For test procedure see Figures 3 and 4 and application note AND8307/D.

3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z

= 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.

0

90

80

70

60

50

40

30

VOLTAGE (V)

20

10

0

−10

−20 0 20 40 60 80 100 120 140

0

−10

−20

−30

−40

−50

−60

VOLTAGE (V)

−70

−80

−90

−100

−20 0 20 40 60 80 100 120 140

TIME (ns) TIME (ns)

Figure 1. IEC61000−4−2 +8 KV Contact

Clamping Voltage

Figure 2. IEC61000−4−2 −8 KV Contact

Clamping Voltage

mA

10 V

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2

ESD7016, SZESD7016

IEC 61000−4−2 Spec.

Test Volt-

Level

age (kV)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

ESD Gun

First Peak

Current

(A)

Current at

30 ns (A)

Device

Under

Test

50 W

Cable

IEC61000−4−2 Waveform

I

peak

Current at

60 ns (A)

100%

90%

I @ 30 ns

I @ 60 ns

10%

Figure 3. IEC61000−4−2 Spec

Oscilloscope

50 W

tP = 0.7 ns to 1 ns

Figure 4. Diagram of ESD Clamping Voltage Test Setup

The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger

100

t

r

90

80

70

60

50

40

30

20

% OF PEAK PULSE CURRENT

10

0

020406080

PEAK VALUE I

t

P

Figure 5. 8 x 20 ms Pulse Waveform

systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D and AND8308/D.

@ 8 ms

RSM

PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms

HALF VALUE I

t, TIME (ms)

/2 @ 20 ms

RSM

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