ESD7016, SZESD7016
ESD Protection Diode
Low Capacitance, USB 3.0
The ESD7016 surge protection is specifically designed to protect
USB3.0 interfaces by integrating two Superspeed pairs, D+, D−, and
Vbus lines into a single protection product. Ultra−low capacitance and
low ESD clamping voltage make this device an ideal solution for
protecting voltage sensitive high speed data lines. The flow−through
style package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines.
Features
• Low Capacitance (0.15 pF Typical, I/O to GND)
• Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
• Low ESD Clamping Voltage
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• This is a Pb−Free Device
Typical Applications
• USB 3.0
MAXIMUM RATINGS (T
Rating
Operating Junction Temperature Range T
Storage Temperature Range T
Lead Solder Temperature −
Maximum (10 Seconds)
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
= 25°C unless otherwise noted)
J
Symbol Value Unit
J
stg
T
L
ESD
ESD
−55 to +125 °C
−55 to +150 °C
260 °C
±15
±15
kV
kV
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UDFN8
CASE 517CB
1
6M = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONFIGURATION
AND SCHEMATIC
I/O 1
I/O 2
N/C
N/C
Vbus or Ground
I/O 3
I/O 4
I/O 5
I/O 6
ORDERING INFORMATION
Device Package Shipping
ESD7016MUTAG UDFN8
(Pb−Free)
MARKING
DIAGRAM
6M MG
G
3000 / Tape &
Reel
© Semiconductor Components Industries, LLC, 2013
October, 2017 − Rev. 4
SZESD7016MUTAG UDFN8
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1 Publication Order Number:
3000 / Tape &
Reel
ESD7016/D
ESD7016, SZESD7016
RWM
BR
R
C
C
V
C
J
= 25°C unless otherwise specified)
A
I/O Pin to GND 5.0 V
IT = 1 mA, I/O Pin to GND 5.5 V
V
= 5 V, I/O Pin to GND 1.0
RWM
IPP = 1 A, I/O Pin to GND (8 x 20 ms pulse)
IEC61000−4−2, ±8 kV Contact See Figures 1 and 2 V
IPP = ±8 A
I
= ±16 A
PP
14.6
20.5
VR = 0 V, f = 1 MHz between I/O Pins and GND 0.15 0.20 pF
VR = 0 V, f = 1 MHz between I/O Pins and GND 0.03 pF
J
ELECTRICAL CHARACTERISTICS (T
Parameter
Reverse Working Voltage V
Breakdown Voltage V
Reverse Leakage Current I
Clamping Voltage (Note 1) V
Clamping Voltage (Note 2) V
Clamping Voltage
TLP (Note 3)
See Figures 6 through 9
Junction Capacitance C
Junction Capacitance
Difference
Symbol Conditions Min Typ Max Unit
DC
1. Surge current waveform per Figure 5.
2. For test procedure see Figures 3 and 4 and application note AND8307/D.
3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z
= 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
0
90
80
70
60
50
40
30
VOLTAGE (V)
20
10
0
−10
−20 0 20 40 60 80 100 120 140
0
−10
−20
−30
−40
−50
−60
VOLTAGE (V)
−70
−80
−90
−100
−20 0 20 40 60 80 100 120 140
TIME (ns) TIME (ns)
Figure 1. IEC61000−4−2 +8 KV Contact
Clamping Voltage
Figure 2. IEC61000−4−2 −8 KV Contact
Clamping Voltage
mA
10 V
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2
ESD7016, SZESD7016
IEC 61000−4−2 Spec.
Test Volt-
Level
age (kV)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
ESD Gun
First Peak
Current
(A)
Current at
30 ns (A)
Device
Under
Test
50 W
Cable
IEC61000−4−2 Waveform
I
peak
Current at
60 ns (A)
100%
90%
I @ 30 ns
I @ 60 ns
10%
Figure 3. IEC61000−4−2 Spec
Oscilloscope
50 W
tP = 0.7 ns to 1 ns
Figure 4. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
100
t
r
90
80
70
60
50
40
30
20
% OF PEAK PULSE CURRENT
10
0
020406080
PEAK VALUE I
t
P
Figure 5. 8 x 20 ms Pulse Waveform
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D and AND8308/D.
@ 8 ms
RSM
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I
t, TIME (ms)
/2 @ 20 ms
RSM
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3
ESD7016, SZESD7016
6
22
20
18
16
14
12
10
8
CURRENT (A)
6
4
2
0
024681012141618
VOLTAGE (V)
2220 24 26
Figure 6. Positive TLP I−V Curve Figure 7. Negative TLP I−V Curve
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
−22
−20
−18
−16
−14
−12
−10
−8
CURRENT (A)
−6
−4
−2
0
024681012141618 2220 24 2
VOLTAGE (V)
L
Attenuator
S
50 W Coax
÷
50 W Coax
Cable
10 MW
V
C
Figure 8. Simplified Schematic of a Typical TLP
System
I
M
V
M
Oscilloscope
Cable
DUT
Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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4
ESD7016, SZESD7016
With ESD7016Without ESD7016
Figure 10. USB3.0 Eye Diagram with and without ESD7016, 5 Gb/s
4
2
0
−2
−4
−6
S21 INSERTION LOSS (dB)
−8
−10
1.E+06 1.E+07 1.E+08 1.E+09 1.E+10
FREQUENCY (Hz)
ESD7016
IO−GND
Figure 11. ESD7016 Insertion Loss
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5
I/O
Pin 1
I/O
Pin 2
I/O
Pin 4
I/O
Pin 5
I/O
Pin 7
ESD7016, SZESD7016
I/O
Pin 8
Pinout Option 1:
2 Ground connections between high
speed pairs to minimize crosstalk.
USB 3.0 Type A
Connector
StdA_SSTX+
Vbus
StdA_SSTX−
D−
I/O
Pin 1
I/O
Pin 2
GND
Pin 3
VBUS
Pin 3
=
I/O
Pin 4
GND
Pin 6
I/O
Pin 5
I/O
Pin 7
I/O
Pin 8
Single ground connection and Vbus
Pinout Option 2:
protection for fully integrated solution.
GND_DRAIN
D+
StdA_SSRX+
GND
StdA_SSRX−
USB 3.0 Type A
Connector
StdA_SSTX+
Vbus
StdA_SSTX−
Vbus
GND_DRAIN
GND
Pin 6
StdA_SSRX+
=
StdA_SSRX−
D−
D+
GND
Figure 12. USB3.0 Type A Connector Layout Diagrams
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6
ESD7016, SZESD7016
USB 3.0 Micro B
Connector
Vbus
ESD9X
N/C
N/C
ESD7016
ID
Figure 13. USB3.0 Micro B Connector Layout Diagram
D−
D+
ID
GND
MicB_SSTX−
MicB_SSTX+
GND_DRAIN
MicB_SSRX−
MicB_SSRX+
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
1
SCALE 4:1
B
A
E
A
(A3)
A1
b
8X
0.10 BC
8
0.05 C
PIN ONE
REFERENCE
2X
2X
0.10 C
0.10 C
0.05 C
0.05 C
DETAIL A
TOP VIEW
DETAIL B
SIDE VIEW
e/2
e
1
D
UDFN8, 3.3x1.0, 0.4P
CASE 517CB
ISSUE O
L1
DETAIL A
ALTERNATE
CONSTRUCTIONS
DETAIL B
ALTERNATE
C
M
M
SEATING
PLANE
NOTE 3
CONSTRUCTION
A
DATE 27 SEP 2011
NOTES:
L
MOLD CMPDEXPOSED Cu
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
MILLIMETERS
DIM MIN MAX
A 0.45 0.55
A1 0.00 0.05
A3 0.13 REF
b 0.15 0.25
D 3.30 BSC
D2 0.25 0.45
E 1.00 BSC
E2 0.45 0.55
e 0.40 BSC
G2 1.19 BSC
L 0.20 0.30
L1 −−− 0.15
L2 0.30 0.40
GENERIC
MARKING DIAGRAM*
L2
2X
E2
G2
BOTTOM VIEW
7X
L
2X
D2
M
0.10 BC
M
0.05 C
A
RECOMMENDED
SOLDERING FOOTPRINT*
7X
0.40
2X
0.65
1.20
1.66
0.40
PITCH
DIMENSION: MILLIMETERS
0.50
2X
0.50
8X
0.25
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
XX MG
G
XX = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
98AON59259E
UDFN8, 3.3X1.0, 0.4P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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