ON Semiconductor ESD7002, SZESD7002 SPECIFICATIONS

ESD7002, SZESD7002

ESD Protection Diode

Low Capacitance ESD Protection Diode
for High Speed Data Line

The ESD7002 surge protection device is designed to protect high
speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines. The flow−through style
package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines such as USB 3.0 and HDMI.

Features

• Low Capacitance (0.3 pF Typical, I/O to GND)

• Diode capacitance matching

• Protection for the Following IEC Standards:

• IEC 61000−4−2 (Level 4)

• Low ESD Clamping Voltage

• SZ Prefix for Automotive and Other Applications Requiring Unique

Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable

• These Devices are Pb−Free and are RoHS Compliant

Typical Applications

• USB2.0/3.0

• LVDS

• HDMI

• High Speed Differential Pairs

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onsemi.com

MARKING
DIAGRAM

SC−70

CASE 419

STYLE 4

72 = Specific Device Code
M = Date Code
G = Pb−Free Package

(Note: Microdot may be in either location)

PIN CONFIGURATION

AND SCHEMATIC

Pin 1 Pin 2

Pin 3

72 MG

1

G

MAXIMUM RATINGS (T

Rating Symbol Value Unit

Operating Junction Temperature Range T
Storage Temperature Range T
Lead Solder Temperature −

Maximum (10 Seconds)
IEC 61000−4−2 Contact (ESD)

IEC 61000−4−2 Air (ESD)

Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.

© Semiconductor Components Industries, LLC, 2014

July, 2017 − Rev. 4

= 25°C unless otherwise noted)

J

J

stg

T

L

ESD
ESD

−55 to +125 °C

−55 to +150 °C
260 °C

±8

±15

kV
kV

1 Publication Order Number:

=

ORDERING INFORMATION

See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.

ESD7002/D

ESD7002, SZESD7002

1.0

1E−02

CURRENT (A)

VOLTAGE (V)

0

ELECTRICAL CHARACTERISTICS (T

Parameter

Reverse Working
Voltage

Breakdown Voltage V
Reverse Leakage

Current
Clamping Voltage

(Note 1)
Clamping Voltage TLP

(Note 2)

Junction Capacitance
Match

Junction Capacitance C
Junction Capacitance C
3dB Bandwidth f

Symbol Conditions Min Typ Max Unit

V

RWM

BR

I

R

V

C

V

C

DC

J

J
J

BW

= 25°C unless otherwise specified)

A

I/O Pin to GND 16 V

I

= 1 mA, I/O Pin to GND 16.5 23 V

T

V

= 5 V, I/O Pin to GND 1

RWM

IEC61000−4−2, ±8 kV Contact See Figures 3 and 4

IPP = 8 A

I

= 16 A

PP

IPP = −8 A

IPP = −16 A

VR = 0 V, f = 1 MHz between I/O1 to GND and I/O

31.2

33.9

−5.5

−10.8
5 10 %

2 to GND

VR = 0 V, f = 1 MHz between I/O Pins 0.2 0.4 pF

VR = 0 V, f = 1 MHz between I/O Pins and GND 0.3 0.5 pF

RL = 50 W

5 GHz

1. For test procedure see Figures 5 and 6 and application note AND8307/D.

2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z

1E−03
1E−04
1E−05
1E−06
1E−07
1E−08
1E−09
1E−10

1E−11
1E−12
1E−13

0

2

= 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.

0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

CAPACITANCE (pF)

0.2

0.1
0

468101214 2422201816

02468101214

VOLTAGE (V) VBias (V)

Figure 1. Typical IV Characteristic Curve Figure 2. Typical CV Characteristic Curve

150
140
130
120
110
100

90
80
70
60
50
40
30
20
10

0

−10

−50

50 100 150 200 400250 300 350

0

TIME (ns)

Figure 3. IEC61000−4−2 +8 kV Contact ESD

Clamping Voltage

10

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

VOLTAGE (V)

−110

−120

−130

−140

−150

−20

0 20 40 80 120 20

10060

TIME (ns)

Figure 4. IEC61000−4−2 −8 kV Contact ESD

Clamping Voltage

mA

V

140 160 180

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2

ESD7002, SZESD7002

IEC 61000−4−2 Spec.

Test Volt-

Level

age (kV)

1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8

ESD Gun

First Peak

Current

(A)

Current at

30 ns (A)

DUT

50 W

Cable

IEC61000−4−2 Waveform

I

peak

Current at

60 ns (A)

Figure 5. IEC61000−4−2 Spec

100%

90%

I @ 30 ns

I @ 60 ns

10%

Oscilloscope

50 W

tP = 0.7 ns to 1 ns

Figure 6. Diagram of ESD Clamping Voltage Test Setup

The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.

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