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ESD7002
SPECIFICATIONS
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ON Semiconductor ESD7002, SZESD7002 SPECIFICATIONS

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ESD7002, SZESD7002
ESD Protection Diode
Low Capacitance ESD Protection Diode for High Speed Data Line
Features
• Low Capacitance (0.3 pF Typical, I/O to GND)
• Diode capacitance matching
• Protection for the Following IEC Standards:
• IEC 61000−4−2 (Level 4)
• Low ESD Clamping Voltage
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• USB2.0/3.0
• LVDS
• HDMI
• High Speed Differential Pairs
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onsemi.com
MARKING DIAGRAM
SC−70
CASE 419
STYLE 4
72 = Specific Device Code M = Date Code G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONFIGURATION
AND SCHEMATIC
Pin 1 Pin 2
Pin 3
72 MG
1
G
MAXIMUM RATINGS (T
Rating Symbol Value Unit
Operating Junction Temperature Range T Storage Temperature Range T Lead Solder Temperature −
Maximum (10 Seconds) IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2014
July, 2017 − Rev. 4
= 25°C unless otherwise noted)
J
J
stg
T
L
ESD ESD
−55 to +125 °C
−55 to +150 °C 260 °C
±8
±15
kV kV
1 Publication Order Number:
=
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet.
ESD7002/D
ESD7002, SZESD7002
1.0
1E−02
CURRENT (A)
VOLTAGE (V)
0
ELECTRICAL CHARACTERISTICS (T
Parameter
Reverse Working Voltage
Breakdown Voltage V Reverse Leakage
Current Clamping Voltage
(Note 1) Clamping Voltage TLP
(Note 2)
Junction Capacitance Match
Junction Capacitance C Junction Capacitance C 3dB Bandwidth f
Symbol Conditions Min Typ Max Unit
V
RWM
BR
I
R
V
C
V
C
DC
J
J J
BW
= 25°C unless otherwise specified)
A
I/O Pin to GND 16 V
I
= 1 mA, I/O Pin to GND 16.5 23 V
T
V
= 5 V, I/O Pin to GND 1
RWM
IEC61000−4−2, ±8 kV Contact See Figures 3 and 4
IPP = 8 A
I
= 16 A
PP
IPP = −8 A
IPP = −16 A
VR = 0 V, f = 1 MHz between I/O1 to GND and I/O
31.2
33.9
−5.5
−10.8 5 10 %
2 to GND
VR = 0 V, f = 1 MHz between I/O Pins 0.2 0.4 pF
VR = 0 V, f = 1 MHz between I/O Pins and GND 0.3 0.5 pF
RL = 50 W
5 GHz
1. For test procedure see Figures 5 and 6 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z
1E−03 1E−04 1E−05 1E−06 1E−07 1E−08 1E−09 1E−10
1E−11 1E−12 1E−13
0
2
= 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
CAPACITANCE (pF)
0.2
0.1 0
468101214 2422201816
02468101214
VOLTAGE (V) VBias (V)
Figure 1. Typical IV Characteristic Curve Figure 2. Typical CV Characteristic Curve
150 140 130 120 110 100
90 80 70 60 50 40 30 20 10
0
−10
−50
50 100 150 200 400250 300 350
0
TIME (ns)
Figure 3. IEC61000−4−2 +8 kV Contact ESD
Clamping Voltage
10
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
VOLTAGE (V)
−110
−120
−130
−140
−150
−20
0 20 40 80 120 20
10060
TIME (ns)
Figure 4. IEC61000−4−2 −8 kV Contact ESD
Clamping Voltage
mA
V
140 160 180
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2
ESD7002, SZESD7002
IEC 61000−4−2 Spec.
Test Volt-
Level
age (kV)
1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8
ESD Gun
First Peak
Current
(A)
Current at
30 ns (A)
DUT
50 W
Cable
IEC61000−4−2 Waveform
I
peak
Current at
60 ns (A)
Figure 5. IEC61000−4−2 Spec
100%
90%
I @ 30 ns
I @ 60 ns
10%
Oscilloscope
50 W
tP = 0.7 ns to 1 ns
Figure 6. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D.
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3
ESD7002, SZESD7002
18 16 14 12 10
8 6
CURRENT (A)
4 2 0
040353051015 2520
VOLTAGE (V)
Figure 7. Positive TLP IV Curve
NOTE: TLP parameter: Z
= 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns.
0
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 9. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 10 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels.
−18
−16
−14
−12
−10
−8
−6
CURRENT (A)
−4
−2 0
0 −14−2 −4 −6 −8 −12−10
VOLTAGE (V)
Figure 8. Negative TLP IV Curve
L
50 W Coax
Cable
Figure 9. Simplified Schematic of a Typical TLP
10 MW
V
C
System
Attenuator
S
÷
I
M
Oscilloscope
50 W Coax
Cable
V
M
DUT
Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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4
ESD7002, SZESD7002
With ESD7002Without ESD7002
Figure 11. USB3.0 Eye Diagram with and without ESD7002 at 5 Gb/s
1
0.5 0
−0.5
−1
−1.5
S21 (dB)
−2
−2.5
−3
−3.5
−4
1.E+06 1.E+07 1.E+08 1.E+09 FREQUENCY (Hz)
Figure 12. Typical Insertion Loss
ORDERING INFORMATION
Device Package Shipping
ESD7002WTT1G SC−70
(Pb−Free)
SZESD7002WTT1G* SC−70
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
3000 / Tape & Reel
3000 / Tape & Reel
†
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SCALE 4:1
D
e1
3
E
b
A
0.05 (0.002)
H
E
12
e
A1
SC−70 (SOT−323)
CASE 419−04
ISSUE N
A2
DATE 11 NOV 2008
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIMAMIN NOM MAX MIN
A1 0.00 0.05 0.10 0.000 A2 0.70 REF
b 0.30 0.35 0.40 0.012
c 0.10 0.18 0.25 0.004 D 1.80 2.10 2.20 0.071 E 1.15 1.24 1.35 0.045
e 1.20 1.30 1.40 0.047
e1
L
H
E
MILLIMETERS
0.80 0.90 1.00 0.032
0.65 BSC
0.38
0.20 0.56
2.00 2.10 2.40 0.079 0.083 0.095
INCHES
NOM MAX
0.035 0.040
0.002 0.004
0.028 REF
0.014 0.016
0.007 0.010
0.083 0.087
0.049 0.053
0.051 0.055
0.026 BSC
0.015
0.008 0.022
c
GENERIC
L
MARKING DIAGRAM
SOLDERING FOOTPRINT*
0.65
0.65
0.025
0.9
0.035
0.7
0.028
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
STYLE 1:
STYLE 6:
PIN 1. EMITTER
2. BASE
3. COLLECTOR
CANCELLED
STYLE 2:
PIN 1. ANODE
2. N.C.
3. CATHODE
STYLE 7:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
0.025
1.9
0.075
SCALE 10:1
STYLE 3:
PIN 1. BASE
STYLE 8:
PIN 1. GATE
2. SOURCE
3. DRAIN
ǒ
inches
2. EMITTER
3. COLLECTOR
mm
Ǔ
STYLE 4:
STYLE 9:
PIN 1. CATHODE
2. CATHODE
3. ANODE
PIN 1. ANODE
2. CATHODE
3. CATHODE-ANODE
XX MG
G
1
XX = Specific Device Code M = Date Code G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present.
STYLE 5:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. ANODE-CATHODE
STYLE 11:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
98ASB42819B
SC−70 (SOT−323)
Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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