The ESD5581 is designed to protect voltage sensitive components
that require low capacitance from ESD and transient voltage events.
Excellent clamping capability, low capacitance, low leakage, and fast
response time, make these parts ideal for ESD protection on designs
where board space is at a premium.
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Features
• Low Clamping Voltage
• Small Body Outline Dimensions: 0.62 mm x 0.32 mm
• Low Body Height: 0.3 mm
• Stand−off Voltage: 5 V
• IEC61000−4−2 Level 4 ESD Protection
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• mSD Card Protection
• Audio Line Protection
• GPIO
MAXIMUM RATINGS
RatingSymbolValueUnit
IEC 61000−4−2 (ESD)Contact
Total Power Dissipation on FR−5 Board
(Note 1) @ TA = 25°C
Thermal Resistance, Junction−to−Ambient
Junction and Storage Temperature RangeTJ, T
Lead Solder Temperature − Maximum
(10 Second Duration)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
Air
°P
R
°
D
q
JA
stg
T
L
±30
±30
250
400
−55 to +150°C
260°C
kV
mW
°C/W
1
X3DFN2
CASE 152AF
5= Specific Device Code
M = Date Code
X2DFN2
CASE 714AB
YC = Specific Device Code
M= Date Code
ORDERING INFORMATION
DevicePackageShipping
ESD5581MXT5GX3DFN2
(Pb−Free)
ESD5581N2T5GX2DFN2
(Pb−Free)
2
MARKING
DIAGRAM
PIN 1
5
M
YC M
10000 / Tape &
Reel
8000 / Tape &
Reel
†
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD801 1/D.
See Application Note AND8308/D for further description of survivability specs.
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
C
Working Peak Reverse Voltage
Maximum Reverse Leakage Current @ V
R
Breakdown Voltage @ I
BR
Test Current
T
*See Application Note AND8308/D for detailed explanations of
Parameter
PP
RWM
T
VCV
V
RWM
BR
Bi−Directional
I
I
PP
I
T
I
R
I
V
RWM
V
R
I
T
I
PP
BR
V
V
C
datasheet parameters.
ELECTRICAL CHARACTERISTICS (T
Parameter
Reverse Working VoltageV
Breakdown Voltage (Note 2)V
Reverse Leakage CurrentI
Clamping Voltage (Note 3)V
Clamping Voltage (Note 3)V
Clamping Voltage (Note 3)V
Clamping Voltage (Note 4)V
Peak Pulse Current (Note 3)I
Clamping Voltage
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.
3. Non−repetitive current pulse at T
4. For test procedure see Figure 10 and application note AND8307/D.
= 25°C, per IEC61000−4−5 waveform. (See Figure 12)
A
5. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
100
t
r
90
80
70
60
50
40
30
20
% OF PEAK PULSE CURRENT
10
0
020406080
PEAK VALUE I
t
P
Figure 12. 8 X 20 ms Pulse Waveform
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
@ 8 ms
RSM
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I
t, TIME (ms)
RSM
/2 @ 20 ms
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5
ESD5581
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 13. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 14 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP requirements, and how to interrupt them, please
refer to AND9007/D.
L
Attenuator
S
50 W Coax
Cable
÷
50 W Coax
Cable
Figure 13. Simplified Schematic of a Typical TLP
10 MW
V
C
System
I
M
V
M
Oscilloscope
DUT
Figure 14. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
X3DFN2, 0.62x0.32, 0.355P, (0201)
SCALE 8:1
A1
2
A B
2X
E
A
C
b
0.05BC
SEATING
PLANE
M
INDICATOR
(OPTIONAL)
2X
0.05BC
PIN 1
0.05 C
0.05 C
L22X
M
A
BOTTOM VIEW
D
TOP VIEW
SIDE VIEW
e
1
CASE 152AF
ISSUE A
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
MILLIMETERS
DIM MIN MAX
A 0.250.33
A1 −−−0.05
b0.22 0.28
D 0.580.66
E0.28 0.36
e0.355 BSC
L2 0.170.23
GENERIC
MARKING DIAGRAM*
PIN 1
XM
X = Specific Device Code
M = Date Code
RECOMMENDED
MOUNTING FOOTPRINT*
0.74
2X
0.30
DATE 17 FEB 2015
DOCUMENT NUMBER:
DESCRIPTION:
*For additional information on our Pb−Free strategy and soldering
98AON56472E
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
X3DFN2, 0.62X0.32, 0.355P, (0201)
1
2X
0.31
DIMENSIONS: MILLIMETERS
See Application Note AND8398/D for more mounting details
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
PAGE 1 OF 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. EXPOSED COPPER ALLOWED AS SHOWN.
MILLIMETERS
DIM MIN NOM
C
A 0.340.37
A1 −−−0.03
b0.45 0.50
D
0.95 1.00
E
0.55 0.60
e0.65 BSC
L0.20 0.25
MAX
0.40
0.05
0.55
1.05
0.65
0.30
GENERIC
MARKING DIAGRAM*
XX M
XX = Specific Device Code
A
M= Date Code
RECOMMENDED
SOLDER FOOTPRINT*
A
2X
0.47
PIN 1
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
1.20
2X
0.60
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
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