ON Semiconductor CS5171, CS5172, CS5173, CS5174 Technical data

查询CS5171供应商

CS5171, CS5172, CS5173,
CS5174

1.5 A 280 kHz/560 kHz
Boost Regulators

The CS5171/2/3/4 products are 280 kHz/560 kHz switching
regulators with a high efficiency, 1.5 A integrated switch. These parts
operate over a wide input voltage range, from 2.7 V to 30 V. The
flexibility of the design allows the chips to operate in most power
supply configurations, including boost, flyback, forward, inverting,
and SEPIC. The ICs utilize current mode architecture, which allows
excellent load and line regulation, as well as a practical means for
limiting current. Combining high frequency operation with a highly
integrated regulator circuit results in an extremely compact power
supply solution. The circuit design includes provisions for features
such as frequency synchronization, shutdown, and feedback controls
for either positive or negative voltage regulation. These parts are
pin−to−pin compatible with LT1372/1373.

Part Number Frequency Feedback Voltage Polarity

CS5171 280 kHz positive
CS5172 280 kHz negative
CS5173 560 kHz positive
CS5174 560 kHz negative

Features

• Pb−Free Packages are Available

• Integrated Power Switch: 1.5 A Guaranteed

• Wide Input Range: 2.7 V to 30 V

• High Frequency Allows for Small Components

• Minimum External Components

• Easy External Synchronization

• Built in Overcurrent Protection

• Frequency Foldback Reduces Component Stress During an

Overcurrent Condition

• Thermal Shutdown with Hysteresis

• Regulates Either Positive or Negative Output Voltages

• Shut Down Current: 50 A Maximum

• Pin−to−Pin Compatible with LT1372/1373

• Wide Temperature Range

♦ Industrial Grade: −40°C to 125°C
♦ Commercial Grade: 0°C to 125°C

http://onsemi.com

SOIC−8

D SUFFIX

CASE 751

PIN CONNECTIONS AND

MARKING DIAGRAM

CS5171/3

1

V

C

SS

CS5172/4

1

V

C

SS

x = 1, 2, 3, or 4
x = E, G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week

See detailed ordering and shipping information in the
package dimensions section on page 17 of this data sheet.

ORDERING INFORMATION

ALYW

ALYW

517xx

517xx

8

V

SW

PGNDFB
AGNDTest
V

CC

8

V

SW

PGNDTest
AGNDNFB
V

CC

 Semiconductor Components Industries, LLC, 2004

June, 2004 − Rev. 20

1 Publication Order Number:

CS5171/D

0.01 F

SS

3.3 V

C1

CS5171, CS5172, CS5173, CS5174

R2

3.72 k

1

V

C

2

FB

3

Test

45

SS

PGND

AGND

CS5171/3

8

V

SW

7

6

L1

V

CC

22 H

D1

MBRS120T3

+

V

OUT

C3
22 F

5 V

R1
5 k

R3

1.28 k

+

C2

22 F

Figure 1. Applications Diagram

MAXIMUM RATINGS

Rating Value Unit

Junction Temperature Range, T
Storage Temperature Range, T

J

STORAGE

Package Thermal Resistance: Junction−to−Case, R

Junction−to−Ambient, R



JC



JA

−40 to +150 °C

−65 to +150 °C
45

165

°C/W
°C/W

Lead Temperature Soldering: Reflow (Note 1) 230 Peak °C
ESD, Human Body Model 1.2 kV

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously . If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.

1. 60 second maximum above 183°C.

MAXIMUM RATINGS

Pin Name Pin Symbol V

IC Power Input V

CC

MAX

30 V −0.3 V N/A 200 mA

Shutdown/Sync SS 30 V −0.3 V 1.0 mA 1.0 mA

V

MIN

I

SOURCE

I

SINK

Loop Compensation V
Voltage Feedback Input FB

C

6.0 V −0.3 V 10 mA 10 mA
10 V −0.3 V 1.0 mA 1.0 mA

(CS5171/3 only)

Negative Feedback Input
(transient, 10 ms)

NFB

(CS5172/4 only)

−10 V 10 V 1.0 mA 1.0 mA

Test Pin Test 6.0 V −0.3 V 1.0 mA 1.0 mA
Power Ground PGND 0.3 V −0.3 V 4 A 10 mA
Analog Ground AGND 0 V 0 V N/A 10 mA
Switch Input V

SW

40 V −0.3 V 10 mA 3.0 A

http://onsemi.com

2

CS5171, CS5172, CS5173, CS5174

ELECTRICAL CHARACTERISTICS (2.7 V< V

Commercial Grade: 0°C < T

Characteristic

< 125°C; For all CS5171/2/3/4 specifications unless otherwise stated.)

J

< 30 V; Industrial Grade: −40°C < TJ < 125°C;

CC

Test Conditions Min Typ Max Unit

Positive and Negative Error Amplifiers

FB Reference Voltage (CS5171/3 only) VC tied to FB; measure at FB 1.246 1.276 1.300 V
NFB Reference Voltage (CS5172/4 only) VC = 1.25 V −2.55 −2.45 −2.35 V
FB Input Current (CS5171/3 only) FB = V

REF

NFB Input Current (CS5172/4 only) NFB = NV
FB Reference Voltage Line Regulation

VC = FB − 0.01 0.03 %/V

REF

−1.0 0.1 1.0 A

−16 −10 −5.0 A

(CS5171/3 only)
NFB Reference Voltage Line Regulation

VC = 1.25 V − 0.01 0.05 %/V

(CS5172/4 only)
Positive Error Amp Transconductance IVC = ± 25 A 300 550 800 Mho
Negative Error Amp Transconductance IVC = ± 5 A 115 160 225 Mho
Positive Error Amp Gain (Note 2) 200 500 − V/V
Negative Error Amp Gain (Note 2) 100 180 320 V/V
VC Source Current FB = 1.0 V or NFB = −1.9 V, VC = 1.25 V 25 50 90 A
VC Sink Current FB = 1.5 V or NFB = −3.1 V, VC = 1.25 V 200 625 1500 A
VC High Clamp Voltage FB = 1.0 V or NFB = −1.9 V;

V

sources 25 A

C

1.5 1.7 1.9 V

VC Low Clamp Voltage FB = 1.5 V or NFB = −3.1 V, VC sinks 25 A 0.25 0.50 0.65 V
VC Threshold Reduce VC from 1.5 V until switching stops 0.75 1.05 1.30 V

Oscillator

Base Operating Frequency CS5171/2, FB = 1 V or NFB = −1.9 V 230 280 310 kHz
Reduced Operating Frequency CS5171/2, FB = 0 V or NFB = 0 V 30 52 120 kHz
Maximum Duty Cycle CS5171/2 90 94 − %
Base Operating Frequency CS5173/4, FB = 1 V or NFB = −1.9 V 460 560 620 kHz
Reduced Operating Frequency CS5173/4, FB = 0 V or NFB = 0 V 60 104 160 kHz
Maximum Duty Cycle CS5173/4 82 90 − %
NFB Frequency Shift Threshold Frequency drops to reduced operating frequency −0.80 −0.65 −0.50 V
FB Frequency Shift Threshold Frequency drops to reduced operating frequency 0.36 0.40 0.44 V

Sync/ Shutdown

Sync Range CS5171/2 320 − 500 kHz
Sync Range CS5173/4 640 − 1000 kHz
Sync Pulse Transition Threshold Rise time = 20 ns 2.5 − − V
SS Bias Current SS = 0 V

SS = 3.0 V

−15−−3.0

3.0

8.0

−

A
A

Shutdown Threshold − 0.50 0.85 1.20 V
Shutdown Delay 2.7 V ≤ VCC ≤ 12 V

12 V < V

≤ 30 V

CC

12
12

80
36

350
200

s
s

2. Guaranteed by design, not 100% tested in production.

http://onsemi.com

3

CS5171, CS5172, CS5173, CS5174

ELECTRICAL CHARACTERISTICS (continued) (2.7 V< V

Commercial Grade: 0°C < T

< 125°C; For all CS5171/2/3/4 specifications unless otherwise stated.)

J

< 30 V; Industrial Grade: −40°C < TJ < 125°C;

CC

Characteristic UnitMaxTypMinTest Conditions

Power Switch

I

Switch Saturation Voltage

= 1.5 A, (Note 3)

SWITCH

I

= 1.0 A, 0°C ≤ TJ ≤ 85°C

SWITCH

I

= 1.0 A, −40°C ≤ TJ ≤ 0°C

SWITCH

I

= 10 mA

SWITCH

Switch Current Limit 50% duty cycle, Note 3

80% duty cycle, Note 3

1.6

1.5

−

−

−

−

0.8

0.55

0.75

0.09

1.9

1.7

1.4

−

−

0.45

2.4

2.2
Minimum Pulse Width FB = 0 V or NFB = 0 V, ISW = 4.0 A, (Note 3) 200 250 300 ns
ICC/ IV

SW

2.7 V ≤ VCC ≤ 12 V, 10 mA ≤ISW ≤ 1.0 A
12 V < V

2.7 V ≤ V
12 V < V

≤ 30 V, 10 mA ≤ISW ≤ 1.0 A

CC

≤ 12 V, 10 mA ≤ISW ≤ 1.5 A, (Note 3)

CC

≤ 30 V, 10 mA ≤ISW ≤ 1.5 A, (Note 3)

CC

−

−

−

−

10

17

30

−

100

30

−

100

Switch Leakage VSW = 40 V, VCC = 0V − 2.0 100 A

General

Operating Current
Shutdown Mode Current VC < 0.8 V, SS = 0 V, 2.7 V ≤ VCC ≤ 12 V

Minimum Operation Input Voltage VSW switching, maximum I

ISW = 0 − 5.5 8.0 mA

V

< 0.8 V, SS = 0 V, 12 V ≤ VCC ≤ 30 V

C

10 mA − 2.45 2.70 V

SW =

−

−

12

60

−

100

Thermal Shutdown (Note 3) 150 180 210 °C
Thermal Hysteresis (Note 3) − 25 − °C

3. Guaranteed by design, not 100% tested in production.

V
V
V
V

A
A

mA/A
mA/A
mA/A
mA/A

A

PACKAGE PIN DESCRIPTION

Package

Pin #

1 V

2

(CS5171/3

only)

2

(CS5172/4)

3

(CS5171/3)

3

(CS5172/4)

4 SS Synchronization and shutdown pin. This pin may be used to synchronize the part to nearly twice the base

5 V

6 AGND Analog ground. This pin provides a clean ground for the controller circuitry and should not be in the path of

7 PGND Power ground. This pin is the ground connection for the emitter of the power switching transistor. Connection

8 V

Pin

Symbol

C

Loop compensation pin. The V
current limit and soft start. Loop compensation can be implemented by a simple RC network as shown in the

pin is the output of the error amplifier and is used for loop compensation,

C

Function

application diagram on page 2 as R1 and C1.

FB Positive regulator feedback pin. This pin senses a positive output voltage and is referenced to 1.276 V. When

the voltage at this pin falls below 0.4 V, chip switching frequency reduces to 20% of the nominal frequency.

Test These pins are connected to internal test logic and should either be left floating or tied to ground. Connection

to a voltage between 2 V and 6 V shuts down the internal oscillator and leaves the power switch running.

NFB Negative feedback pin. This pin senses a negative output voltage and is referenced to −2.5 V. When the volt-

age at this pin goes above −0.65 V, chip switching frequency reduces to 20% of the nominal frequency.

frequency. A TTL low will shut the part down and put it into low current mode. If synchronization is not used,
this pin should be either tied high or left floating for normal operation.

Input power supply pin. This pin supplies power to the part and should have a bypass capacitor connected to

CC

AGND.

large currents. The output voltage sensing resistors should be connected to this ground pin. This pin is con­nected to the IC substrate.

to a good ground plane is essential.
High current switch pin. This pin connects internally to the collector of the power switch. The open voltage

SW

across the power switch can be as high as 40 V. To minimize radiation, use a trace as short as practical.

http://onsemi.com

4

V

CC

SS

NFB

CS5172/4

only

FB

CS5171/3

only

250 k

Shutdown

Delay
Timer

200 k

2.0 V

1.276 V

CS5171, CS5172, CS5173, CS5174

Thermal

Shutdown

2.0 V

Regulator

PWM

S

Latch

+

Sync

Negative
Error Amp

+

−

−0.65 V Detector

0.4 V Detector

−
+

Positive
Error Amp

Oscillator

Frequency

Shift 5:1

Q

R

Slope
Compensation

PWM
Comparator

−

Driver

Ramp
Summer

×5

Switch

63 m

V

SW

PGND

AGND

V

C

Figure 2. Block Diagram

http://onsemi.com

5

CS5171, CS5172, CS5173, CS5174

TYPICAL PERFORMANCE CHARACTERISTICS

7.2

7.0

6.8

6.6

6.4

6.2

6.0

Current (mA)

5.8

5.6
0

Temperature (°C)

50 100

Figure 3. ICC (No Switching) vs. Temperature

1200
1000

800

(mV)

600

CE(SAT)

400

V

200

0

500 1000

I

SW

(mA)

VCC = 30 V

VCC = 12 V

VCC = 2.7 V

−40 °C
85 °C

25 °C

70
60
50

40

(mA/A)

30
20

10

0

1.9

1.8

(V)

1.7

IN

V

1.6

1.5

VCC = 30 V

ISW = 1.5 A

VCC = 12 V

VCC = 2.7 V

0

Temperature (°C)

50 100

Figure 4. ICC/ IVSW vs. Temperature

0 10050

Temperature (°C)

285
280
275
270

(kHz)

OSC

265

f

260
255

Figure 5. V

0 10050

Temperature (°C)

CE(SAT)

vs. I

SW

Figure 7. Switching Frequency vs. Temperature

(CS5171/2 only)

Figure 6. Minimum Input V oltage vs. Temperature

570
565

560
555

550

(kHz)

545

OSC

f

540
535
530
525
520

0 10050

Temperature (°C)

Figure 8. Switching Frequency vs. Temperature

(CS5173/4 only)

http://onsemi.com

6

CS5171, CS5172, CS5173, CS5174

TYPICAL PERFORMANCE CHARACTERISTICS

VCC = (12 V)

100

−40°C

75

50

(% of Typical)

OSC

25

f

0

350

25°C

380 400 420 450

V

(mV)

FB

Figure 9. Switching Frequency vs. V

(CS5171/3 only)

1.280

1.278

1.276

1.274

Voltage (V)

1.272

1.270

1.268

VCC = 2.7 V

0 10050

Temperature (°C)

Figure 11. Reference Voltage vs. Temperature

(CS5171/3 only)

85°C

FB

VCC = 12 V

VCC = 30 V

VCC = (12 V)

100

85°C

75

50

(% of Typical)

OSC

f

25

25°C

0

−550

−660

V

(mV)

NFB

Figure 10. Switching Frequency vs. V

(CS5172/4 only)

−2.42

−2.43

−2.44

−2.45

Voltage (V)

−2.46

−2.47

−2.48

= 12 V

V

CC

0 10050

Temperature (°C)

V

CC

Figure 12. Reference Voltage vs. Temperature

(CS5172/4 only)

−40°C

−725

NFB

= 30 V

VCC = 2.7 V

0.20

0.18

0.16

(A)

0.14

FB

I

0.12

0.10

0.08

Figure 13. I

= 12 V

V

CC

V

= 2.7 V

CC

0 10050

Temperature (°C)

vs. Temperature (CS5171/3 only)

FB

−7

−8

−9

−10

(A)

−11

NFB

I

−12

−13

−14

Figure 14. I

http://onsemi.com

7

0 50 100

Temperature (°C)

vs. Temperature (CS5172/ 4 only)

NFB

CS5171, CS5172, CS5173, CS5174

TYPICAL PERFORMANCE CHARACTERISTICS

2.60

2.50

2.40

Current (A)

2.30

2.20

1.7

1.5

1.3

1.1

Voltage (V)

0.9

0.7

VCC = 2.7 V

VCC = 12 V

0 10050

Temperature (°C)

VCC = 30 V

Figure 15. Current Limit vs. Temperature

VC High Clamp Voltage

VC Threshold

0 10050

Temperature (°C)

Figure 17. V

Threshold and High Clamp

C

Voltage vs. Temperature

99
98

97
96
95

Duty Cycle (%)

94
93

0 10050

Temperature (°C)

VCC = 30 V

Figure 16. Maximum Duty Cycle vs. T emperature

1.1

1.0

0.9

0.8

0.7

Voltage (V)

0.6

0.5

0.4
0

Temperature (°C)

50

Figure 18. Shutdown Threshold vs. Temperature

VCC = 12 V

VCC = 2.7 V

100

160
140

120
100

Delay (s)

80
60
40

0 10050

Temperature (°C)

Figure 19. Shutdown Delay vs. Temperature

VCC = 2.7 V

VCC = 12 V

VCC = 30 V

40

30

20

(A)

SS

10

I

0

−10

http://onsemi.com

8

175

39

VSS (V)

Figure 20. I

SS

vs. V

25°C

85°C

−40°C

SS

CS5171, CS5172, CS5173, CS5174

TYPICAL PERFORMANCE CHARACTERISTICS

40

30

(A)

20

CC

I

10

190
180
170
160
150

(mho)

140

m

g

130
120
110
100

0

Figure 21. ICC vs. V

0 10050

Temperature (°C)

10

VIN (V)

During Shutdown

IN

−40°C

25°C

85°C

Figure 23. Negative Error Amplifier

Transconductance vs. Temperature (CS5172/4 only)

600

550

(mho)

m

g

500

450

0 10050

Temperature (°C)

Figure 22. Error Amplifier Transconductance

vs. Temperature (CS5171/3 only)

100

60

(A)

20

OUT

I

−20

−60

−125−175−255
V

REF

− VFB (mV)

Figure 24. Error Amplifier I

(CS5171/3 only)

OUT

0

vs. V

25−25−75

FB

100

80
60
40

(A)

20

OUT

I

−20

−40

−60

0

Figure 25. Error Amplifier I

(CS5172/4 only)

2.6

2.5

2.4

2.3

Current (A)

2.2

2.1

−100−150−200

V

− V

NFB

(mV)

REF

OUT

0

vs. V

50−50

NFB

2.0
0 10050

Temperature (°C)

Figure 26. Switch Leakage vs. T emperature

http://onsemi.com

9

CS5171, CS5172, CS5173, CS5174

APPLICATIONS INFORMATION

THEORY OF OPERATION

Current Mode Control

V

Oscillator

−

V

C

+

PWM
Comparator

SUMMER

Slope Compensation

S
R

Q

X5

Power Switch

In Out

Driver

63 m



CC

L

V

SW

D1

C

O

R

LOAD

Figure 27. Current Mode Control Scheme

The CS517x family incorporates a current mode control
scheme, in which the PWM ramp signal is derived from the
power switch current. This ramp signal is compared to the
output of the error amplifier to control the on−time of the
power switch. The oscillator is used as a fixed−frequency
clock to ensure a constant operational frequency. The
resulting control scheme features several advantages over
conventional voltage mode control. First, derived directly
from the inductor, the ramp signal responds immediately to
line voltage changes. This eliminates the delay caused by the
output filter and error amplifier, which is commonly found
in voltage mode controllers. The second benefit comes from
inherent pulse−by−pulse current limiting by merely
clamping the peak switching current. Finally, since current
mode commands an output current rather than voltage, the
filter offers only a single pole to the feedback loop. This
allows both a simpler compensation and a higher
gain−bandwidth over a comparable voltage mode circuit.

Without discrediting its apparent merits, current mode
control comes with its own peculiar problems, mainly,
subharmonic oscillation at duty cycles over 50%. The
CS517x family solves this problem by adopting a slope
compensation scheme in which a fixed ramp generated by
the oscillator is added to the current ramp. A proper slope
rate is provided to improve circuit stability without
sacrificing the advantages of current mode control.

Oscillator and Shutdown

Sync

Current

Ramp

V

SW

Figure 28. Timing Diagram of Sync and Shutdown

The oscillator is trimmed to guarantee an 18% frequency
accuracy. The output of the oscillator turns on the power
switch at a frequency of 280 kHz (CS5171/2) or 560 kHz
(CS5173/4), as shown in Figure 27. The power switch is
turned off by the output of the PWM Comparator.

A TTL−compatible sync input at the SS pin is capable of
syncing up to 1.8 times the base oscillator frequency. As
shown in Figure 28, in order to sync to a higher frequency,
a positive transition turns on the power switch before the
output of the oscillator goes high, thereby resetting the
oscillator. The sync operation allows multiple power
supplies to operate at the same frequency.

A sustained logic low at the SS pin will shut down the IC
and reduce the supply current.

An additional feature includes frequency shift to 20% of
the nominal frequency when either the NFB or FB pins
trigger the threshold. During power up, overload, or short
circuit conditions, the minimum switch on−time is limited
by the PWM comparator minimum pulse width. Extra
switch off−time reduces the minimum duty cycle to protect
external components and the IC itself.

As previously mentioned, this block also produces a ramp
for the slope compensation to improve regulator stability.

Error Amplifier

NFB

FB

250 k

200 k

CS5172/4

negative error−amp

1.276 V

CS5171/3

2.0 V

+

−

+

−

positive error−amp

1M

120 pF

Voltage
Clamp

V

C

C1

0.01 F
R1

5 k

Figure 29. Error Amplifier Equivalent Circuit

For CS5172/4, the NFB pin is internally referenced to

−2.5 V with approximately a 250 k input impedance. For
CS5171/3, the FB pin is directly connected to the inverting
input of the positive error amplifier, whose non−inverting
input is fed by the 1.276 V reference. Both amplifiers are
transconductance amplifiers with a high output impedance
of approximately 1 M, as shown in Figure 29. The V

C

pin
is connected to the output of the error amplifiers and is
internally clamped between 0.5 V and 1.7 V. A typical
connection at the V

pin includes a capacitor in series with

C

a resistor to ground, forming a pole/zero for loop
compensation.

An external shunt can be connected between the VC pin
and ground to reduce its clamp voltage. Consequently, the
current limit of the internal power transistor current is
reduced from its nominal value.

http://onsemi.com

10

CS5171, CS5172, CS5173, CS5174

Switch Driver and Power Switch

The switch driver receives a control signal from the logic
section to drive the output power switch. The switch is
grounded through emitter resistors (63 m total) to the
PGND pin. PGND is not connected to the IC substrate so that
switching noise can be isolated from the analog ground. The
peak switching current is clamped by an internal circuit. The
clamp current is guaranteed to be greater than 1.5 A and
varies with duty cycle due to slope compensation. The
power switch can withstand a maximum voltage of 40 V on
the collector (V

pin). The saturation voltage of the switch

SW

is typically less than 1 V to minimize power dissipation.

Short Circuit Condition

When a short circuit condition happens in a boost circuit,
the inductor current will increase during the whole
switching cycle, causing excessive current to be drawn from
the input power supply. Since control ICs don’t have the
means to limit load current, an external current limit circuit
(such as a fuse or relay) has to be implemented to protect the
load, power supply and ICs.

In other topologies, the frequency shift built into the IC
prevents damage to the chip and external components. This
feature reduces the minimum duty cycle and allows the
transformer secondary to absorb excess energy before the
switch turns back on.

I

L

approximately 1.5 V, the internal power switch briefly turns
on. This is a part of the CS517x’s normal operation. The
turn−on of the power switch accounts for the initial current
swing.

When the V

pin voltage rises above the threshold, the

C

internal power switch starts to switch and a voltage pulse can
be seen at the V

pin. Detecting a low output voltage at the

SW

FB pin, the built−in frequency shift feature reduces the
switching frequency to a fraction of its nominal value,
reducing the minimum duty cycle, which is otherwise
limited by the minimum on−time of the switch. The peak
current during this phase is clamped by the internal current
limit.

When the FB pin voltage rises above 0.4 V, the frequency
increases to its nominal value, and the peak current begins
to decrease as the output approaches the regulation voltage.
The overshoot of the output voltage is prevented by the
active pull−on, by which the sink current of the error
amplifier is increased once an overvoltage condition is
detected. The overvoltage condition is defined as when the
FB pin voltage is 50 mV greater than the reference voltage.

COMPONENT SELECTION

Frequency Compensation

The goal of frequency compensation is to achieve
desirable transient response and DC regulation while
ensuring the stability of the system. A typical compensation
network, as shown in Figure 31, provides a frequency
response of two poles and one zero. This frequency response
is further illustrated in the Bode plot shown in Figure 32.

V

OUT

V

CC

V

C

Figure 30. Startup Waveforms of Circuit Shown in

the Application Diagram. Load = 400 mA.

The CS517x can be activated by either connecting the
VCC pin to a voltage source or by enabling the SS pin.
Startup waveforms shown in Figure 30 are measured in the
boost converter demonstrated in the Application Diagram
on the page 2 of this document. Recorded after the input
voltage is turned on, this waveform shows the various
phases during the power up transition.

When the V

voltage is below the minimum supply

CC

voltage, the VSW pin is in high impedance. Therefore,
current conducts directly from the input power source to the
output through the inductor and diode. Once VCC reaches

V

C

R1

CS5171

C1

GND

Figure 31. A Typical Compensation Network

C2

The high DC gain in Figure 32 is desirable for achieving
DC accuracy over line and load variations. The DC gain of
a transconductance error amplifier can be calculated as
follows:

GainDC GM R

O

where:

GM = error amplifier transconductance;

RO = error amplifier output resistance ≈ 1 M.

The low frequency pole, f

is determined by the error

P1,

amplifier output resistance and C1 as:



1

2C1R

O

f

P1

http://onsemi.com

11

CS5171, CS5172, CS5173, CS5174









The first zero generated by C1 and R1 is:



2C1R1

1

f

Z1

The phase lead provided by this zero ensures that the loop

has at least a 45° phase margin at the crossover frequency.
Therefore, this zero should be placed close to the pole
generated in the power stage which can be identified at
frequency:

2COR

1

LOAD

f



P

where:

C

= equivalent output capacitance of the error amplifier

O

≈120pF;

R

= load resistance.

LOAD

The high frequency pole, fP2, can be placed at the output
filter’s ESR zero or at half the switching frequency. Placing
the pole at this frequency will cut down on switching noise.
The frequency of this pole is determined by the value of C2
and R1:



2C2R1

1

f

P2

One simple method to ensure adequate phase margin is to
design the frequency response with a −20 dB per decade
slope, until unity−gain crossover. The crossover frequency
should be selected at the midpoint between fZ1 and fP2 where
the phase margin is maximized.

−V

OUT

R1

NFB

R2

Figure 33. Negative Error Amplifier and NFB Pin

R

IN

250 k

2 V

R

P

200 k

+

−

Negative Error−Amp

It is shown that if R1 is less than 10 k, the deviation from
the design target will be less than 0.1 V. If the tolerances of
the negative voltage reference and NFB pin input current are
considered, the possible offset of the output V

OFFSET

varies

in the range of:

0.0.5 (R1  R2)



VSW Voltage Limit

R2



 (15 A  R1)  V

0.0.5 (R1  R2)



R2

OFFSET

 (5 A  R1)

In the boost topology, VSW pin maximum voltage is set by
the maximum output voltage plus the output diode forward
voltage. The diode forward voltage is typically 0.5 V for
Schottky diodes and 0.8 V for ultrafast recovery diodes

f

P1

DC Gain

f

Z1

f

P2

Gain (dB)

Frequency (LOG)

Figure 32. Bode Plot of the Compensation Network

Shown in Figure 31

Negative Voltage Feedback

Since the negative error amplifier has finite input
impedance as shown in Figure 33, its induced error has to be
considered. If a voltage divider is used to scale down the
negative output voltage for the NFB pin, the equation for
calculating output voltage is:

V

OUT

2.5 (R1  R2)



R2

10 A  R1

V

SW(MAX)

 V

OUT(MAX)VF

where:

VF = output diode forward voltage.
In the flyback topology, peak VSW voltage is governed by:

V

SW(MAX)

 V

CC(MAX)

(V

OUTVF

)  N

where:

N = transformer turns ratio, primary over secondary.

When the power switch turns off, there exists a voltage
spike superimposed on top of the steady−state voltage.
Usually this voltage spike is caused by transformer leakage
inductance charging stray capacitance between the V
PGND pins. To prevent the voltage at the V

SW

and

SW

pin from
exceeding the maximum rating, a transient voltage
suppressor in series with a diode is paralleled with the
primary windings. Another method of clamping switch
voltage is to connect a transient voltage suppressor between
the V

pin and ground.

SW

http://onsemi.com

12

CS5171, CS5172, CS5173, CS5174

Magnetic Component Selection

When choosing a magnetic component, one must consider
factors such as peak current, core and ferrite material, output
voltage ripple, EMI, temperature range, physical size and
cost. In boost circuits, the average inductor current is the
product of output current and voltage gain (V

OUT/VCC

assuming 100% energy transfer efficiency. In continuous
conduction mode, inductor ripple current is

I

RIPPLE



VCC(V

(f)(L)(V

OUT

 VCC)

OUT)

where:

f = 280 kHz for CS5171/2 and 560 kHz for CS5173/4.

The peak inductor current is equal to average current plus
half of the ripple current, which should not cause inductor
saturation. The above equation can also be referenced when
selecting the value of the inductor based on the tolerance of
the ripple current in the circuits. Small ripple current
provides the benefits of small input capacitors and greater
output current capability. A core geometry like a rod or
barrel is prone to generating high magnetic field radiation,
but is relatively cheap and small. Other core geometries,
such as toroids, provide a closed magnetic loop to prevent
EMI.

Input Capacitor Selection

In boost circuits, the inductor becomes part of the input
filter, as shown in Figure 35. In continuous mode, the input
current waveform is triangular and does not contain a large
pulsed current, as shown in Figure 34. This reduces the
requirements imposed on the input capacitor selection.
During continuous conduction mode, the peak to peak
inductor ripple current is given in the previous section. As
we can see from Figure 34, the product of the inductor
current ripple and the input capacitor’s effective series
resistance (ESR) determine the V

ripple. In most

CC

applications, input capacitors in the range of 10 F to 100 F
with an ESR less than 0.3  work well up to a full 1.5 A
switch current.

I

IN

+

V

CC

),

−

Figure 35. Boost Circuit Effective Input Filter

C

IN

R

ESR

I

L

The situation is different in a flyback circuit. The input
current is discontinuous and a significant pulsed current is
seen by the input capacitors. Therefore, there are two
requirements for capacitors in a flyback regulator: energy
storage and filtering. T o maintain a stable voltage supply to
the chip, a storage capacitor larger than 20 F with low ESR
is required. To reduce the noise generated by the inductor,
insert a 1.0 F ceramic capacitor between V

and ground

CC

as close as possible to the chip.

Output Capacitor Selection

V

ripple

OUT

I

L

V

CC

I

IN

I

L

Figure 34. Boost Input Voltage and Current

Ripple Waveforms

By examining the waveforms shown in Figure 36, we can

ripple

see that the output voltage ripple comes from two major
sources, namely capacitor ESR and the
charging/discharging of the output capacitor. In boost
circuits, when the power switch turns off, I
output capacitor causing an instant V = I
same time, current IL − I
increases the output voltage gradually. When the power
switch is turned on, IL is shunted to ground and I
discharges the output capacitor. When the IL ripple is small
enough, IL can be treated as a constant and is equal to input
current I

http://onsemi.com

13

Figure 36. Typical Output Voltage Ripple

flows into the

L

× ESR. At the

IN

charges the capacitor and

OUT

.

IN

OUT

CS5171, CS5172, CS5173, CS5174

Summing up, the output voltage peak−peak ripple can be

calculated by:

V

OUT(RIPPLE)



(IIN I

I

OUT



(C

(C

OUT

(1  D)

OUT)

(f)

OUT)

D

 IIN ESR

)(f)

The equation can be expressed more conveniently in

terms of V

CC

, V

OUT

and I

for design purposes as

OUT

follows:

V

OUT(RIPPLE)

I

OUT(VOUT



(I



OUT

(C

OUT
)(V

V

 VCC)

)(f)

OUT

CC

)(ESR)



(C

1

OUT

)(f)

The capacitor RMS ripple current is:

I

RIPPLE



 (IIN I

OUT



 I

)2(1  D)(I

OUT

V

OUT

V

 V

CC

CC

OUT

)2(D)

Although the above equations apply only for boost
circuits, similar equations can be derived for flyback
circuits.

Unfortunately, such a simple circuit is not generally
acceptable if VIN is loosely regulated.

V

IN

V

CC

R2

V

D1

R3

Figure 37. Current Limiting using a Diode Clamp

C

R1

C1

C2

Another solution to the current limiting problem is to
externally measure the current through the switch using a
sense resistor. Such a circuit is illustrated in Figure 38.

Reducing the Current Limit

In some applications, the designer may prefer a lower
limit on the switch current than 1.5 A. An external shunt can
be connected between the VC pin and ground to reduce its
clamp voltage. Consequently, the current limit of the
internal power transistor current is reduced from its nominal
value.

The voltage on the V

pin can be evaluated with the

C

equation

VC ISWREA

V

where:

RE = .063, the value of the internal emitter resistor;

A

= 5 V/V, the gain of the current sense amplifier.

V

Since RE and AV cannot be changed by the end user, the
only available method for limiting switch current below

1.5 A is to clamp the VC pin at a lower voltage. If the
maximum switch or inductor current is substituted into the
equation above, the desired clamp voltage will result.

A simple diode clamp, as shown in Figure 37, clamps the
V

voltage to a diode drop above the voltage on resistor R3.

C

V

CC

+

−

V

IN

Figure 38. Current Limiting using a Current Sense

PGND

Q1

C3

R

SENSE

AGND

R2

Resistor

V

C

R1

C1

C2

Output
Ground

The switch current is limited to

V

I

SWITCH(PEAK)



BE(Q1)

R

SENSE

where:

V

= the base−emitter voltage drop of Q1, typically

BE(Q1)

0.65 V.

http://onsemi.com

14

CS5171, CS5172, CS5173, CS5174

The improved circuit does not require a regulated voltage
to operate properly. Unfortunately, a price must be paid for
this convenience in the overall efficiency of the circuit. The
designer should note that the input and output grounds are
no longer common. Also, the addition of the current sense
resistor, R

, results in a considerable power loss which

SENSE

increases with the duty cycle. Resistor R2 and capacitor C3
form a low−pass filter to remove noise.

Subharmonic Oscillation

Subharmonic oscillation (SHM) is a problem found in
current−mode control systems, where instability results
when duty cycle exceeds 50%. SHM only occurs in
switching regulators with a continuous inductor current.
This instability is not harmful to the converter and usually
does not affect the output voltage regulation. SHM will
increase the radiated EM noise from the converter and can
cause, under certain circumstances, the inductor to emit
high−frequency audible noise.

SHM is an easily remedied problem. The rising slope of
the inductor current is supplemented with internal “slope
compensation” to prevent any duty cycle instability from
carrying through to the next switching cycle. In the CS517x
family, slope compensation is added during the entire switch
on−time, typically in the amount of 180 mA/s.

In some cases, SHM can rear its ugly head despite the
presence of the onboard slope compensation. The simple
cure to this problem is more slope compensation to avoid the
unwanted oscillation. In that case, an external circuit, shown
in Figure 39, can be added to increase the amount of slope
compensation used. This circuit requires only a few
components and is “tacked on” to the compensation
network.

V

SW

V

C

R1

C1

C2

C3

R2

R3

V

SW

The dashed box contains the normal compensation
circuitry to limit the bandwidth of the error amplifier.
Resistors R2 and R3 form a voltage divider off of the V

SW

pin. In normal operation, VSW looks similar to a square
wave, and is dependent on the converter topology. Formulas
for calculating V

in the boost and flyback topologies are

SW

given in the section “VSW Voltage Limit.” The voltage on
VSW charges capacitor C3 when the switch is off, causing
the voltage at the VC pin to shift upwards. When the switch
turns on, C3 discharges through R3, producing a negative
slope at the V

pin. This negative slope provides the slope

C

compensation.

The amount of slope compensation added by this circuit
is

I

T

 V

SW



R2R

R

3





3

1  e

(1D)

R3C3f

SW



(1  D)REA

f

SW



V

where:

I/T = the amount of slope compensation added (A/s);

VSW = the voltage at the switch node when the transistor

is turned off (V);

fSW = the switching frequency, typically 280 kHz

(CS5171/3) or 560 kHz (CS5172/4) (Hz);

D = the duty cycle;

R

= 0.063 , the value of the internal emitter resistor;

E

AV = 5 V/V, the gain of the current sense amplifier.

In selecting appropriate values for the slope compensation
network, the designer is advised to choose a convenient
capacitor, then select values for R2 and R3 such that the
amount of slope compensation added is 100 mA/s. Then
R2 may be increased or decreased as necessary. Of course,
the series combination of R2 and R3 should be large enough
to avoid drawing excessive current from V

. Additionally,

SW

to ensure that the control loop stability is improved, the time
constant formed by the additional components should be
chosen such that

R3C

1  D



3

f

SW

Finally, it is worth mentioning that the added slope
compensation is a tradeoff between duty cycle stability and
transient response. The more slope compensation a designer
adds, the slower the transient response will be, due to the
external circuitry interfering with the proper operation of the
error amplifier.

Soft−Start

Through the addition of an external circuit, a Soft−Start
function can be added to the CS5171/2/3/4 family of
components. Soft−Start circuitry prevents the VC pin from
slamming high during startup, thereby inhibiting the
inductor current from rising at a high slope.

Figure 39. Technique for Increasing Slope

Compensation

http://onsemi.com

15

CS5171, CS5172, CS5173, CS5174

This circuit, shown in Figure 40, requires a minimum
number of components and allows the Soft−Start circuitry to
activate any time the SS pin is used to restart the converter.

V

IN

V

CC

SS

D1

SS

V

C

D2

C1

C3

Figure 40. Soft Start

R1

C2

Resistor R1 and capacitors C1 and C2 form the
compensation network. At turn on, the voltage at the VC pin
starts to come up, charging capacitor C3 through Schottky
diode D2, clamping the voltage at the VC pin such that
switching begins when VC reaches the VC threshold,
typically 1.05 V (refer to graphs for detail over temperature).

VC V

F(D2)VC3

Therefore, C3 slows the startup of the circuit by limiting
the voltage on the VC pin. The Soft−Start time increases with
the size of C3.

Diode D1 discharges C3 when SS is low. If the shutdown
function is not used with this part, the cathode of D1 should
be connected to V

Calculating Junction Temperature

IN

.

To ensure safe operation of the CS5171/2/3/4, the
designer must calculate the on−chip power dissipation and
determine its expected junction temperature. Internal
thermal protection circuitry will turn the part off once the
junction temperature exceeds 180°C ± 30°. However,
repeated operation at such high temperatures will ensure a
reduced operating life.

Calculation of the junction temperature is an imprecise
but simple task. First, the power losses must be quantified.
There are three major sources of power loss on the CS517x:

• biasing of internal control circuitry, P

• switch driver, P

• switch saturation, P

DRIVER

SAT

BIAS

The internal control circuitry, including the oscillator and
linear regulator, requires a small amount of power even

when the switch is turned off. The specifications section of
this datasheet reveals that the typical operating current, I

Q

due to this circuitry is 5.5 mA. Additional guidance can be
found in the graph of operating current vs. temperature. This
graph shows that IQ is strongly dependent on input voltage,
V

, and temperature. Then

IN

P

 VINI

BIAS

Q

Since the onboard switch is an NPN transistor, the base
drive current must be factored in as well. This current is
drawn from the V

pin, in addition to the control circuitry

IN

current. The base drive current is listed in the specifications
as ICC/ISW, or switch transconductance. As before, the
designer will find additional guidance in the graphs. With
that information, the designer can calculate

I

P

DRIVER

 VINI

SW



I

CC

SW

 D

where:

ISW = the current through the switch;

D = the duty cycle or percentage of switch on−time.

I

and D are dependent on the type of converter. In a

SW

boost converter,

I

SW(AVG)

 I

LOAD

D 

 D 

V

OUT

1

Efficiency

 V

V

OUT

IN

In a flyback converter,

V

V



OUT



OUTILOAD

V

IN

N

S

V

IN

N

P

I

SW(AVG)

D 

V

OUT

The switch saturation voltage, V
source of on−chip power loss. V



Efficiency

1

, is the last major

(CE)SAT

(CE)SAT

is the
collector−emitter voltage of the internal NPN transistor
when it is driven into saturation by its base drive current. The
value for V

can be obtained from the specifications

(CE)SAT

or from the graphs, as “Switch Saturation Voltage.” Thus,

P

SAT

 V

(CE)SATISW

 D

Finally, the total on−chip power losses are

PD P

BIASPDRIVERPSAT

Power dissipation in a semiconductor device results in the
generation of heat in the junctions at the surface of the chip.
This heat is transferred to the surface of the IC package, but
a thermal gradient exists due to the resistive properties of the
package molding compound. The magnitude of the thermal
gradient is expressed in manufacturers’ data sheets as 

JA

or junction−to−ambient thermal resistance. The on−chip
junction temperature can be calculated if 

, the air

JA

temperature near the surface of the IC, and the on−chip
power dissipation are known.

,

,

http://onsemi.com

16

CS5171, CS5172, CS5173, CS5174

40°C

T

125°C

TJ TA(P

DJA

)

where:

T

= IC or FET junction temperature (°C);

J

TA = ambient temperature (°C);
PD = power dissipated by part in question (W);



= junction−to−ambient thermal resistance (°C/W).

JA

For the CS517x, JA=165°C/W.
Once the designer has calculated T

, the question of

J

whether the CS517x can be used in an application is settled.
If TJ exceeds 150°C, the absolute maximum allowable
junction temperature, the CS517x is not suitable for that
application.

If T

approaches 150°C, the designer should consider

J

possible means of reducing the junction temperature.
Perhaps another converter topology could be selected to
reduce the switch current. Increasing the airflow across the
surface of the chip might be considered to reduce TA.

Circuit Layout Guidelines

In any switching power supply, circuit layout is very
important for proper operation. Rapidly switching currents
combined with trace inductance generates voltage

transitions that can cause problems. Therefore the following
guidelines should be followed in the layout.

1. In boost circuits, high AC current circulates within the
loop composed of the diode, output capacitor, and
on−chip power transistor. The length of associated
traces and leads should be kept as short as possible. In
the flyback circuit, high AC current loops exist on both
sides of the transformer. On the primary side, the loop
consists of the input capacitor, transformer, and
on−chip power transistor, while the transformer,
rectifier diodes, and output capacitors form another
loop on the secondary side. Just as in the boost circuit,
all traces and leads containing large AC currents
should be kept short.

2. Separate the low current signal grounds from the
power grounds. Use single point grounding or ground
plane construction for the best results.

3. Locate the voltage feedback resistors as near the IC as
possible to keep the sensitive feedback wiring short.
Connect feedback resistors to the low current analog
ground.

ORDERING INFORMATION

Device Operating Temperature Range Package Shipping

CS5171ED8 95 Units/Rail
CS5171EDR8 2500 Tape & Reel
CS5172ED8
CS5172EDR8
CS5173ED8
CS5173EDR8
CS5173EDR8G

CS5174ED8 95 Units/Rail
CS5174EDR8
CS5171GD8
CS5171GDR8 2500 Tape & Reel
CS5171GDR8G

CS5172GD8
CS5172GDR8
CS5173GD8
CS5173GDR8
CS5174GD8 95 Units/Rail
CS5174GDR8 2500 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

−

°

−

<

<

J

0°C < TJ < 125°C

°

SOIC−8

SOIC−8

(Pb−Free)

SOIC−8

SOIC−8

(Pb−Free)

SOIC−8

95 Units/Rail

2500 Tape & Reel

95 Units/Rail
2500 Tape & Reel
2500 Tape & Reel

2500 Tape & Reel

95 Units/Rail

2500 Tape & Reel

95 Units/Rail
2500 Tape & Reel

95 Units/Rail
2500 Tape & Reel

†

http://onsemi.com

17

V

CC

5.0 V

C1

0.01 F

SS

R2

4.87 k

CS5171, CS5172, CS5173, CS5174

1

C

2

Test

3

NFB

CS5172/4

4

SS

V

SW

PGND

AGND

V

CC

8

7

22 F

6

L1

5

22 H

D2
MBRS120T3

C4

+

D1

MBRS120T3

+

22 F

V

C3

OUT

−12 VV

R1

5.0 k

R3

1.27 k

+

C2

22 F

Figure 41. Additional Application Diagram, 5.0 V to −12 V/ 75 mA Inverting Converter

3.3 V

GND

IN

0.1 F

10 F

V

PGND (7)
AGND (6)

CS5171/3

V

(1 )

C

CC

(5)

22 H

V

SW

FB (2)

(8)

MBRS120T3

3.6 k

1.3 k

22 F

5.0 V

GND

O

5.0 k

200 pF

Figure 42. Additional Application Diagram, 3.3 V Input, 5.0 V/ 400 mA Output Boost Converter

http://onsemi.com

18

CS5171, CS5172, CS5173, CS5174

MBRS140T3

V

CC

GND

+

22 F

47 nF

1.0 F

V

PGND (7)
AGND (6)

V

(1 )

C

(5)

CC

CS5171/3

V

SW

FB (2)

(8)

P6KE−15A

1N4148

1.28 k

T1

1:2

+

+

MBRS140T3

10.72 k

4.7 nF

2.0 k

Figure 43. Additional Application Diagram, 2.7 to 13 V Input, 12 V/ 200 mA Output Flyback Converter

GND

V

CC

V

SW

FB (2)

(5)

(8)

15 H

22 F

Low
ESR

1.1 k

300

2.2 F

V

(1 )

C

5.0 k

200 pF

CS5171/3

.01 F

V

IN

AGND (6)

PGND (7)

47 F

47 F

−12 V

GND

+12 V

GND

−5.0

V

OUT

Figure 44. Additional Application Diagram, −9.0 V to −28 V Input, −5.0 V/700 mA Output Inverted Buck Converter

V

CC

GND

200 pF

22 F

.01 F

5.0 k

PGND (7)

AGND (6)

CS5171/3

V

(1 )

C

22 H

V

(5)

CC

(8)

V

SW

FB (2)

22 F

+

22 H

+

22 F
Low

ESR

37.24 k

5.0 V

GND

12.76 k

Figure 45. Additional Application Diagram, 2.7 V to 28 V Input, 5.0 V Output SEPIC Converter

http://onsemi.com

19

CS5171, CS5172, CS5173, CS5174

GND

.01 

4.0 V

R1 R2

99.755 k/0.1 W, 1%1.245 k/0.1 W, 1%

C1 C2 C3

.1 

50 V

C11

C10

.1 

R3

2.0 k

.1 
50 V

1

V

C

2

FB

3

Test

4

SS

V

SW

PGND
AGND

CS5171/3

V

CC

8
7
6

C8
10 

5

D1 D1 D1 D1 D1 D1 D1

C9

.1 

C7

.1 

C4 C5 C6

.1  .1 
50 V 50 V 50 V

.1 
50 V

50 V

Figure 46. Additional Application Diagram, 4.0 V Input, 100 V/ 10 mA Output Boost Converter with

Output Voltage Multiplier

200 pF

D1

D3

SS

R1

5.0 k

C6

C1

0.01 F

1

V

C

2

FB

V

SW

PGND

8

7

L1

15 H

3

Test

45

SS

CS5171

AGND

V

CC

6

+

22 F

D2

.1 

1N41481N41481N41481N41481N41481N41481N4148

+

C3

22 F

−12 V

100 V

GND

O

+5.0 V

GND

C4

0.1 F

R2 R3

1.28 k

10.72 k

Figure 47. Additional Application Diagram, 5.0 V Input, ± 12 V

Output Dual Boost Converter

+

GND

C5

22 F

+12 V

http://onsemi.com

20

CS5171, CS5172, CS5173, CS5174

PACKAGE DIMENSIONS

SOIC−8

D SUFFIX

CASE 751−07

ISSUE AB

−Y−

−Z−

−X−
A

58

B

1

S

0.25 (0.010)

4

M

M

Y

K

G

C

SEATING
PLANE

0.10 (0.004)

H

D

0.25 (0.010) Z

M

SXS

Y

N

X 45



M

J

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020

G 1.27 BSC 0.050 BSC

H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050

M 0 8 0 8



N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

INCHES

SOLDERING FOOTPRINT*

1.52

0.060

7.0

0.275

0.6

0.024

4.0

0.155

1.270

0.050

SCALE 6:1



inches

mm



*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

http://onsemi.com

21

CS5171, CS5172, CS5173, CS5174

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA

Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: [e-mail]

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

http://onsemi.com

ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder

For additional information, please contact your
local Sales Representative.

CS5171/D

22