ON Semiconductor CS51227 Technical data

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CS51227
Enhanced Voltage Mode PWM Controller
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SO–8 D SUFFIX CASE 751
Features
1.0 MHz Frequency Capability
4.7 V Start–Up Voltage
Fixed Frequency Voltage Mode Operation with Feed Forward
Undervoltage Lockout
75 µA Start–Up Current
Thermal Shutdown
1.0 A Sink/Source Gate Drive
Pulse–By–Pulse Current Limit with Leading Edge Blanking
50 ns GATE Rise and Fall Time (1.0 nF Load)
Maximum Duty Cycle Over 85%
Programmable Volt–Second Clamp
PIN CONNECTIONS AND
MARKING DIAGRAM
1
GATE
SENSE
CT
A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week
ORDERING INFORMATION
Device Package Shipping
CS51227ED8 SO–8 95 Units/Rail CS51227EDR8 SO–8
ALYW
8
51227
V
CC
GNDI COMPFF V
FB
2500 Tape & Reel
Semiconductor Components Industries, LLC, 2001
April, 2001 – Rev. 7
1 Publication Order Number:
CS51227/D
5.0 V
6.8 µH
FS70VSJ–03
0.1
B320DICT
GATE
CS51227
V
CC
12 V/ 2.0 A
0.1 µF
1.0 k
GND
COMP
CS51227
V
FB
2700 pF
100 pF
9.1 k
5.6 nF
51 k
+
22 µF × 4
300
+
22 µF × 2
9.31 k
0.025
330 pF1.0 nF
I
SENSE
FF CT
110
GND
GND
Figure 1. Applications Diagram, 5.0 V to 12 V/2.0 A Boost Converter
MAXIMUM RATINGS*
Rating Value Unit
Operating Junction Temperature, T Storage Temperature Range, T
J
S
ESD Susceptibility (Human Body Model) 2.0 kV Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) 230 peak °C
1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed.
150 °C
–65 to +150 °C
MAXIMUM RATINGS
Pin Name Pin Symbol V
Gate Drive Output GATE 20 V –0.3 V 1.0 A Peak, 200 mA DC 1.0 A Peak, 200 mA DC
Current Sense Input I
Timing Capacitor CT 6.0 V –0.3 V 1.0 mA 10 mA
Feed Forward FF 6.0 V –0.3 V 1.0 mA 25 mA Error Amp Output COMP 6.0 V –0.3 V 10 mA 20 mA Feedback Voltage V
Power Supply V
Ground GND N/A N/A 1.0 A Peak, 200 mA DC N/A
SENSE
FB
CC
MAX
V
MIN
I
SOURCE
I
SINK
6.0 V –0.3 V 1.0 mA 1.0 mA
6.0 V –0.3 V 1.0 mA 1.0 mA 20 V –0.3 V 10 mA 1.0 A Peak, 200 mA DC
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CS51227
ELECTRICAL CHARACTERISTICS: (–40°C < T
C
= 390 pF; unless otherwise specified.)
T
Characteristic
< 85°C, –40°C < TJ < 125°C, 4.7 V < VCC < 18 V
A
Test Conditions Min Typ Max Unit
Start/Stop Voltages
Start Threshold 4.4 4.5 4.7 V Stop Threshold 3.2 3.8 4.2 V Hysteresis Start – Stop 300 700 1400 mV ICC @ Startup VCC < UVL Start Threshold 38 75 µA
Supply Current
ICC Operating No Load 10 16 mA
Overcurrent Protection
Overcurrent Threshold Ramp I I
to GATE Delay VFB = 0.5 V (no blanking) 60 125 ns
SENSE
SENSE
0.27 0.30 0.33 V
Error Amp
Reference Voltage VFB connected to COMP 1.234 1.263 1.285 V VFB Input Current VFB = 1.25 V 1.3 2.0 µA Open Loop Gain Note 2 60 90 dB Unity Gain Bandwidth Note 2 1.5 2.5 MHz COMP Sink Current COMP = 1.4 V, VFB = 1.45 V 3.0 12 32 mA COMP Source Current COMP = 1.4 V, VFB = 1.15 V 1.0 1.7 2.4 mA COMP High Voltage VFB = 1.15 V 2.8 3.1 3.4 V COMP Low Voltage VFB = 1.45 V 75 150 300 mV PSRR Freq = 120 Hz, Note 2 60 85 dB
Oscillator
Frequency Accuracy 200 235 270 kHz Max Duty Cycle 85 90 95 % Peak Voltage Note 2 1.99 2.05 2.11 V Valley Clamp Voltage 0.90 0.95 1.00 V Valley Voltage Note 2 0.90 0.95 1.00 V Discharge Current 0.85 1.00 1.15 mA Charge Current 95 115 135 µA
Gate Driver
High Saturation Voltage VCC – V Low Saturation Voltage V
GATE
, VCC = 10 V, I
GATE
, I
= 150 mA 1.2 1.5 V
SINK
= 150 mA 1.5 2.0 V
SOURCE
High Voltage Clamp 11 13.5 16 V Output UVL Leakage V
= 0 V 1.0 50 µA
GATE
Rise Time 1.0 nF Load, VCC = 18 V, 1.0 V < VO < 9.0 V 32 50 ns Fall Time 1.0 nF Load, VCC = 18 V, 9.0 V < VO < 1.0 V 25 50 ns Max GATE Voltage @ UVL I
= 100 µA 0.4 0.7 1.5 V
LOAD
2. Guaranteed by design, not 100% tested in production.
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