ON Semiconductor CS51033 Technical data
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CS51033
Fast PFET Buck Controller
The CS51033 is a switching controller for use in dc–dc converters.
It can be used in the buck topology with a minimum number of
external components. The CS51033 consists of a 1.0 A power driver
for controlling the gate of a discrete P–channel transistor, fixed
frequency oscillator, short circuit protection timer, programmable Soft
Start, precision reference, fast output voltage monitoring comparator,
and output stage driver logic with latch.
The high frequency oscillator allows the use of small inductors and
output capacitors, minimizing PC board area and systems cost. The
programmable Soft Start reduces current surges at start up. The short
circuit protection timer significantly reduces the PFET duty cycle to
approximately 1/30 of its normal cycle during short circuit conditions.
The CS51033 is available in an 8–Lead SO package.
Features
• 1.0 A Totem Pole Output Driver
• High Speed Oscillator (700 kHz max)
• No Stability Compensation Required
• Lossless Short Circuit Protection
• 2.0% Precision Reference
• Programmable Soft Start
• Wide Ambient Temperature Range:
♦ Industrial Grade: –40°C to 85°C
♦ Commercial Grade: 0°C to 70°C
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SO–8
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1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
D SUFFIX
CASE 751
PIN CONNECTIONS
1
V
GATE
C
OSC
GND
MARKING
DIAGRAM
8
51033
ALYW
1
V
C
CSPGND
V
CC
V
FB
ORDERING INFORMATION*
Device Package Shipping
CS51033YD8 SO–8 95 Units/Rail
CS51033YDR8 2500 Tape & Reel
CS51033GD8
CS51033GDR8 2500 Tape & ReelSO–8
*Additional ordering information can be found on page
9 of this data sheet.
SO–8
SO–8
95 Units/Rail
Semiconductor Components Industries, LLC, 2002
October, 2002 – Rev. 8
1 Publication Order Number:
CS51033/D
3.3V
IN
C
100 µF
CS51033
IN
R
10 Ω
C
D
4
1N5818
1N4148
1N4148
V
CC
C
OSC
D
2
D
3
V
C
V
U1
CS51033
GATE
V
FB
C
1
0.1 µF
0.1 µF
R
10 Ω
G
IRF7404
4.7 µH
100
1.5V
OUT
@ 3.0 Amp
C
1.0 µF
2
C
100 µF
C
3
OSC
150 pF
GND
PGND
CS
CS
0.1 µF
0.1 µF
D
1
1N5821
C
100 µF
C
0.1 µF
4
0
100 µF
GND
R
1.5 k
A
R
300
B
Note: Capacitors C2, C3, and C4, are low
ESR tantalum caps used for noise reduction.
Figure 1. Typical Application Diagram
MAXIMUM RATINGS*
Rating Value Unit
Power Supply Voltage, V
Driver Supply Voltage, V
Driver Output Voltage, V
C
, CS, VFB (Logic Pins) 5.0 V
OSC
CC
C
GATE
Peak Output Current 1.0 A
Steady State Output Current 200 mA
Operating Junction Temperature, T
Storage Temperature Range, T
J
S
ESD (Human Body Model) 2.0 kV
Package Thermal Resistance: Junction–to–Case, R
Junction–to–Ambient, R
θ
JC
θ
JA
Lead Temperature Soldering: Reflow (SMD styles only) (Note 1) 230 peak °C
1. 60 sec. max above 183°C.
*The maximum package power dissipation must be observed.
5.0 V
20 V
20 V
150 °C
–65 to 150 °C
45
165
GND
°C/W
°C/W
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CS51033
ELECTRICAL CHARACTERISTICS (Specifications apply for 3.135 ≤ V
Industrial Grade: –40°C < T
Characteristic
< 85°C; –40°C < TJ < 125°C: Commercial Grade: 0°C < TA < 70°C; 0°C < TJ < 125°C, unless otherwise specified.)
A
Test Conditions Min Typ Max Unit
≤ 3.465, 3.0 V ≤ VC ≤ 16 V;
CC
Oscillator VFB = 1.2 V
Frequency C
Charge Current 1.4 V < V
Discharge Current 2.7 V > V
Maximum Duty Cycle 1 – (t
Short Circuit Timer VFB = 1.0 V; CS = 0.1 F; V
= 470 pF 160 200 240 kHz
OSC
< 2.0 V – 110 – µA
COSC
> 2.0 V – 660 – µA
COSC
) 80.0 83.3 – %
OFF/tON
= 2.0 V
COSC
Charge Current 1.0 V < VCS < 2.0 V 175 264 325 µA
Fast Discharge Current 2.55 V > VCS > 2.4 V 40 66 80 µA
Slow Discharge Current 2.4 V > VCS > 1.5 V 4.0 6.0 10 µA
Start Fault Inhibit Time – 0.70 0.85 1.40 ms
Valid Fault Time 2.6 V > VCS > 2.4 V 0.2 0.3 0.45 ms
GATE Inhibit Time 2.4 V > VCS > 1.5 V 9.0 15 23 ms
Duty Cycle – 2.5 3.1 4.6 %
CS Comparator VFB = 1.0 V
Fault Enable CS Voltage – – 2.5 – V
Max. CS Voltage VFB = 1.5 V – 2.6 – V
Fault Detect Voltage VCS when GATE goes high – 2.4 – V
Fault Inhibit Voltage Minimum V
CS
– 1.5 – V
Hold Off Release Voltage VFB = 0 V 0.4 0.7 1.0 V
Regulator Threshold Voltage Clamp VCS = 1.5 V 0.725 0.866 1.035 V
VFB Comparators V
Regulator Threshold Voltage TJ = 25°C (Note 2)
Fault Threshold Voltage TJ = 25°C (Note 2)
= VCS = 2.0 V
COSC
= –40 to 125°C
T
J
T
= –40 to 125°C
J
1.225
1.210
1.12
1.10
1.250
1.250
1.15
1.15
1.275
1.290
1.17
1.19
Threshold Line Regulation 3.135 V ≤ VCC ≤ 3.465 – 6.0 15 mV
Input Bias Current VFB = 0 V – 1.0 4.0 µA
Voltage Tracking (Regulator Threshold – Fault Threshold Voltage) 70 100 120 mV
Input Hysteresis Voltage – – 4.0 20 mV
Power Stage VC = 10 V; VFB = 1.2 V
GATE DC Low Saturation Voltage V
GATE DC High Saturation Voltage V
Rise Time C
Fall Time C
= 1.0 V; 200 mA Sink – 1.2 1.5 V
COSC
= 2.7 V; 200 mA Source; VC = V
COSC
= 1.0 nF; 1.5 V < V
GATE
= 1.0 nF; 9.0 V > V
GATE
GATE
GATE
GATE
< 9.0 V – 25 60 ns
> 1.5 V – 25 60 ns
– 1.5 2.1 V
Current Drain
I
CC
I
C
3.135 V < VCC < 3.465 V, Gate switching – 3.5 6.0 mA
3.0 V < VC < 16 V, Gate non–switching – 2.7 4.0 mA
2. Guaranteed by design, not 100% tested in production.
V
V
V
V
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PACKAGE PIN DESCRIPTION
PIN NUMBER
1 V
2 PGND Output power stage ground connection.
3 C
4 GND Logic ground.
5 V
6 V
7 CS Soft Start and fault timing capacitor.
8 V
C
OSC
V
CC
CS
PIN SYMBOL FUNCTION
GATE
OSC
FB
CC
C
V
CC
I
C
7I
C
V
CC
Driver pin to gate of external PFET.
Oscillator frequency programming capacitor.
Feedback voltage input.
Logic supply voltage.
Driver supply voltage.
Oscillator
Comparator
+
A1
–
+
–
+
2.5 V1.5 V
–
G3
I
T
CS
Comparator
+
A2
–
55
I
T
I
T
5
+
–
+
2.5 V1.5 V
–
2.4 V
CS51033
G4
–
A3
+
Slow Discharge
+
Comparator
–
G1
G5
G2
Fault
Comp
V
GATE
Flip–Flop
Q
R
F2
Q
S
+
Hold Off
Comp
–
–
1.15 V
+
+
–
Q
R
F1
Q
S
Slow Discharge
Flip–Flop
A6
0.7 V
+
–
V
FB
Comparator
–
1.25 V
+
A4
+
+
–
RG
+
–
CS Charge
Sense
Comparator
–
2.3 V
V
C
V
GATE
PGND
V
FB
GND
Figure 2. Block Diagram
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