ON Semiconductor CAV24C128 User Manual

CAV24C128

EEPROM Serial 128-Kb I2C

- Automotive Grade 1

Description

The CAV24C128 is a EEPROM Serial 128−Kb I2C, internally

organized as 16,384 words of 8 bits each.

It features a 64−byte page write buffer and supports both the Standard (100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I protocol.

Write operations can be inhibited by taking the WP pin High (this protects the entire memory).

On−Chip ECC (Error Correction Code) makes the device suitable for high reliability applications.

Features

• Automotive AEC−Q100 Grade 1 (−40°C to +125°C) Qualified

• Supports Standard, Fast and Fast−Plus I

• 2.5 V to 5.5 V Supply Voltage Range

• 64−Byte Page Write Buffer

• Hardware Write Protection for Entire Memory

• Schmitt Triggers and Noise Suppression Filters on I

(SCL and SDA)

• Low Power CMOS Technology

• 1,000,000 Program/Erase Cycles

• 100 Year Data Retention

• 8−lead SOIC and TSSOP Packages

• This Device is Pb−Free, Halogen Free/BFR Free and RoHS

Compliant*

C Protocol

C Bus Inputs

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TSSOP−8 Y SUFFIX

CASE 948AL

SOIC−8

W SUFFIX

CASE 751BD

PIN CONFIGURATION

SOIC (W), TSSOP (Y)

For the location of Pin 1, please consult the corresponding package drawing.

SCL

SDA

SCL

A2, A1, A

CAV24C128

SDA

Figure 1. Functional Symbol

* For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

April, 2019 − Rev. 2

1 Publication Order Number:

PIN FUNCTION

FunctionPin Name

Device Address InputsA0, A1, A

Serial Data Input/OutputSDA

Serial Clock InputSCL

Write Protect InputWP

Power SupplyV

GroundV

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.

CAV24C128/D

CAV24C128

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter Rating Units

Storage Temperature −65 to +150 °C

Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V

undershoot to no less than −1.5 V or overshoot to no more than V

+ 1.5 V, for periods of less than 20 ns.

Table 2. RELIABILITY CHARACTERISTICS (Note 2)

Symbol Parameter Min Units

(Notes 3, 4) Endurance 1,000,000 Program / Erase Cycles

END

2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

3. Page Mode, V

4. This device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte

has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order to benefit from the maximum number of write cycles.

Data Retention 100 Years

= 5 V, 25°C

+ 0.5 V. During transitions, the voltage on any pin may

Table 3. D.C. OPERATING CHARACTERISTICS (V

Symbol

CCR

CCW

Parameter Test Conditions Min Max Units

Read Current Read, f

= 400 kHz/1 MHz 1 mA

SCL

Write Current 3 mA

Standby Current All I/O Pins at GND or V

I/O Pin Leakage Pin at GND or V

Input Low Voltage −0.5 0.3 V

Input High Voltage 0.7 V

Output Low Voltage IOL = 3.0 mA 0.4 V

Table 4. PIN IMPEDANCE CHARACTERISTICS (V

= 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise speciﬁed.)

TA = −40°C to +125°C 5

TA = −40°C to +125°C 2

VCC + 0.5 V

Symbol Parameter Conditions Max Units

CIN (Note 5) SDA I/O Pin Capacitance VIN = 0 V 8 pF

CIN (Note 5) Input Capacitance (other pins) VIN = 0 V 6 pF

IWP, IA (Note 6) WP Input Current, Address Input

Current (A

, A1, A2)

< VIH, VCC = 5.5 V 75 mA

< VIH, VCC = 3.3 V 50

> V

5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

6. When not driven, the WP, A

strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V

, A1, A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively

), the strong pull−down reverts to a weak current source.

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CAV24C128

Table 5. A.C. CHARACTERISTICS (V

= 2.5 V to 5.5 V, TA = −40°C to +125°C) (Note 7)

Standard Fast Fast−Plus

Symbol

SCL

HD:STA

LOW

HIGH

SU:STA

HD:DAT

SU:DAT

Parameter

Clock Frequency 100 400 1,000 kHz

START Condition Hold Time 4 0.6 0.25

Low Period of SCL Clock 4.7 1.3 0.45

High Period of SCL Clock 4 0.6 0.40

START Condition Setup Time 4.7 0.6 0.25

Data In Hold Time 0 0 0

Data In Setup Time 250 100 50 ns

Min Max Min Max Min Max

tR (Note 8) SDA and SCL Rise Time 1,000 300 100 ns

tF (Note 8) SDA and SCL Fall Time 300 300 100 ns

SU:STO

BUF

Ti (Note 8) Noise Pulse Filtered at SCL

STOP Condition Setup Time 4 0.6 0.25

Bus Free Time Between

4.7 1.3 0.5

STOP and START

SCL Low to Data Out Valid 3.5 0.9 0.40

Data Out Hold Time 100 100 50 ns

100 100 50 ns

and SDA Inputs

SU:WP

HD:WP

(Notes 8, 9)

WP Setup Time 0 0 0

WP Hold Time 2.5 2.5 1

Write Cycle Time 5 5 5 ms

Power-up to Ready Mode 1 1 0.1 1 ms

7. Test conditions according to “A.C. Test Conditions” table.

8. Tested initially and after a design or process change that affects this parameter.

is the delay between the time VCC is stable and the device is ready to accept commands.

9. t

Units

Table 6. A.C. TEST CONDITIONS

Input Levels 0.2 x VCC to 0.8 x V

Input Rise and Fall Times v 50 ns

Input Reference Levels 0.3 x VCC, 0.7 x V

Output Reference Levels 0.5 x V

Output Load Current Source: IOL = 3 mA; CL = 100 pF

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CAV24C128

Power−On Reset (POR)

The CAV24C128 incorporates Power−On Reset (POR) circuitry which protects the device against powering up in the wrong state.

The CAV24C128 will power up into Standby mode after V

exceeds the POR trigger level and will power down into

Reset mode when V

drops below the POR trigger level.

This bi−directional POR feature protects the device against ‘brown−out’ failure following a temporary loss of power.

Pin Description

SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master.

SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL.

, A1 and A2: The Address pins accept the device address.

When not driven, these pins are pulled LOW internally.

WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. When not driven, this pin is pulled LOW internally.

Functional Description

The CAV24C128 supports the Inter−Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAV24C128 acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Up to 8 devices may be connected to the bus as determined by the device address inputs A and A

C Bus Protocol

two wires are connected to the V

The I

C bus consists of two ‘wires’, SCL and SDA. The

supply via pull−up

, A1,

resistors. Master and Slave devices connect to the 2−wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.

Data transfer may be initiated only when the bus is not

busy (see A.C. Characteristics).

During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 2). The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake−up’ call to all receivers. Absent a START, a Slave will not respond to commands. The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH.

Device Addressing

The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8−bit serial Slave address. The first 4 bits of the Slave address are set to 1010, for normal Read/Write operations (Figure 3). The next 3 bits, A

, A1 and A0, select one of 8 possible Slave

devices and must match the state of the external address pins. The last bit, R/W

, specifies whether a Read (1) or Write (0)

operation is to be performed.

Acknowledge

After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line

during the 9

clock cycle (Figure 4). The Slave will also acknowledge all address bytes and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9

clock cycle. As long as the Master acknowledges the data, the Slave will continue transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by issuing a STOP condition. Bus timing is illustrated in Figure 5.

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