CAT5191
256‐position I2C Compatible
Digital Potentiometer (POT)
The CAT5191 is a 256-position digital linear taper potentiometer
ideally suited for replacing mechanical potentiometers and variable
resistors.
The wiper settings are controlled through an I
interface. Upon power-up, the wiper assumes a midscale position and
may be repositioned anytime after the power is stable. The device can
be programmed to reset the wiper position to midscale or to go to a
shutdown state during operation. An address input pin, AD0, allows
the connection of two devices onto the same I
The CAT5191 operates from 2.7 V to 5.5 V, while consuming less
than 2 mA. This low operating current, combined with a small package
footprint, makes the CAT5191 ideal for battery-powered portable
applications.
The CAT5191, designed as a pin for pin replacement for the
AD5245, is o f fered in the 8-lead SOT23 package and operates over the
−40°C to +125°C industrial temperature range.
Features
• 256-position
• End-to-End Resistance: 50 kW, 100 kW
2
• I
C Compatible Interface
• Power-on Preset to Midscale
• Single Supply 2.7 V to 5.5 V
• Low Temperature Coefficient 100 ppm/°C
• Low Power, I
2 mA max
DD
• Extended Operating Temperature −40°C to +125°C
• SOT−23 8-lead (2.9 mm × 3 mm) Package
• These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
2
C-compatible digital
2
C bus.
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SOT23−8
TP, TB SUFFIX
CASE 527AK
MARKING DIAGRAM
AKYM
1
AK = 50 kW
AL = 100 kW
Y = Production Year
Y = (Last Digit)
M = Production Month
M = (1 − 9, A, B, C)
PIN CONNECTIONS
ALYM
1
Typical Applications
• Potentiometer Replacement
• Transducer Adjustment of Pressure, Temperature, Position,
Chemical, and Optical Sensors
• RF Amplifier Biasing
• Gain Control and Offset Adjustment
© Semiconductor Components Industries, LLC, 2016
November, 2016 − Rev. 0
W
V
DD
GND
SCL
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
1 Publication Order Number:
1
(Top View)
A
B
AD0
SDA
CAT5191/D
CAT5191
V
DD
SCL
SDA
AD0
I2C Interface
and
Control
Power On
Midscale
GND
A
W
B
Figure 1. Functional Block Diagram
Table 1. ORDERING INFORMATION
Part Number Resistance Temperature Range Package Shipping
CAT5191TBE−50GT3
CAT5191TBE−00GT3
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
50 kW
100 kW
−40°C to +125°C
.
SOT−23−8
(Pb-Free)
3000 / Tape & Reel
3000 / Tape & Reel
†
Table 2. PIN FUNCTION DESCRIPTION
Pin No. Pin Name Description
1 W Resistor’s Wiper Terminal
2 V
3 GND Digital Ground
4 SCL Serial Clock Input
5 SDA Serial Data Input
6 AD0 I2C Address bit 0 input
7 B Bottom Terminal of resistive element
8 A Top Terminal of resistive element
DD
Positive Power Supply
Table 3. ABSOLUTE MAXIMUM RATINGS (Note 2)
Rating Value Unit
VDD to GND −0.3 to 6.5 V
VA, VB, VW to GND V
I
MAX
Digital Inputs and Output Voltage to GND 0 to 6.5 V
Operating Temperature Range −40 to +125 °C
Maximum Junction Temperature (T
Storage Temperature −65 to +150 °C
Lead Temperature (Soldering, 10 sec) 300 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and
maximum applied voltage across any two of the A, B, and W terminals at a given resistance.
) 150 °C
JMAX
DD
±20 mA
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2
CAT5191
Table 4. ELECTRICAL CHARACTERISTICS: 50 kW and 100 kW Versions
V
= 2.7 V to 5.5 V; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.
DD
Typ
Parameter
Test Conditions Symbol Min
DC CHARACTERISTICS — RHEOSTAT MODE
Resistor Differential Nonlinearity (Note 4)
RWB, VA = no connection R−DNL −1 ±0.1 +1 LSB
Resistor Integral Nonlinearity (Note 4) RWB, VA = no connection R−INL −2 ±0.4 +2 LSB
Nominal Resistor Tolerance (Note 5) T
= 25°C nR
A
AB
−20 +20 %
Resistance Temperature Coefficient VAB = VDD, Wiper = no connection nRAB/nT 100 ppm/°C
Wiper Resistance
VDD = 5 V, IW = ±3 mA
R
W
VDD = 3 V, IW = ±3 mA 100 250
DC CHARACTERISTICS — POTENTIOMETER DIVIDER MODE
Resolution
N 8 Bits
Differential Nonlinearity (Note 6) DNL −1 ±0.1 +1 LSB
Integral Nonlinearity (Note 6) INL −1 ±0.4 +1 LSB
Voltage Divider Temperature Coefficient Code = 0x80 nVW/nT 100 ppm/°C
Full-Scale Error Code = 0xFF V
Zero-Scale Error Code = 0x00 V
WFSE
WZSE
−3 −1 0 LSB
RESISTOR TERMINALS
Voltage Range (Note 7)
Capacitance (Note 8) A, B f = 1 MHz, measured to GND,
Code = 0 x 80
Capacitance (Note 8) W f = 1 MHz, measured to GND,
Code = 0 x 80
Common-Mode Leakage (Note 8) VA = VB = VDD/2 I
V
A,B,W
C
C
A,B
W
CM
GND V
DIGITAL INPUTS
Input Logic High
VDD = 5 V V
Input Logic Low VDD = 5 V V
Input Logic High VDD = 3 V V
Input Logic Low VDD = 3 V V
Input Current VIN = 0 V or 5 V I
0.7 x V
IH
IL
0.7 x V
IH
IL
IL
POWER SUPPLIES
Power Supply Range
V
DD RANGE
Supply Current VIH = 5 V or VIL = 0 V I
Power Dissipation (Note 8) VIH = 5 V or VIL = 0 V, VDD = 5 V P
DD
DISS
2.7 5.5 V
Power Supply Sensitivity nVDD = +5 V ±10%, Code = Midscale PSS ±0.05 %/%
DYNAMIC CHARACTERISTICS (Notes 8 and 10)
Bandwidth –3 dB
RAB = 50 kW / 100 kW, Code = 0x80
Total Harmonic Distortion VA =1 V rms, VB = 0 V,
= 10 kW
AB
VW Settling Time (50 kW/100 kW)
f = 1 kHz, R
VA = 5 V, VB = 0 V, ±1 LSB error band t
BW 100/40 kHz
THD
W
S
3. Typical specifications represent average readings at +25°C and VDD = 5 V.
4. Resistor position nonlinearity error R−INL is the deviation from an ideal value measured between the maximum resistance and the mini-
mum resistance wiper positions. R−DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
= VDD, Wiper (VW) = no connect.
5. V
AB
6. INL and DNL are measured at VW with the digital potentiometer configured as a potentiometer divider similar to a voltage output D/A con-
verter. V
7. Resistor terminals A, B, W have no limitations on polarity with respect to each other.
= VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
A
8. Guaranteed by design and not subject to production test.
9. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and
maximum applied voltage across any two of the A, B, and W terminals at a given resistance.
10.All dynamic characteristics use V
DD
= 5 V.
(Note 3)
50 120
Max Unit
W
0 1 3 LSB
DD
V
45 pF
60 pF
1 nA
DD
DD
V
V
V
V
mA
mA
DD
0.3V
DD
0.3V
±1
0.3 2
0.2 mW
0.05 %
2
ms
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3
CAT5191
Table 5. CAPACITANCE
TA = 25°C, f = 1.0 MHz, VDD = 5 V
Symbol
C
I/O
(Note 11)
Input/Output Capacitance (SDA, SCL) V
Table 6. POWER UP TIMING (Notes 11 and 12)
Symbol
t
PUR
t
PUW
Power-up to Read Operation 1 ms
Power-up to Write Operation 1 ms
11.This parameter is tested initially and after a design or process change that affects the parameter.
12.t
PUR
and t
are delays required from the time VCC is stable until the specified operation can be initiated.
PUW
Table 7. DIGITAL POTENTIOMETER TIMING
Symbol Parameter Min Max Units
t
WRPO
t
WR
Wiper Response Time After Power Supply Stable 50
Wiper Response Time: SCL falling edge after last bit of wiper position data byte to
wiper change
Table 8. A.C. CHARACTERISTICS
VDD = +2.7 V to +5.5 V, −40°C to +125°C unless otherwise specified.
Symbol
f
SCL
t
HIGH
t
LOW
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
t
R
t
F
t
DH
T
t
AA
I
Clock Frequency 400 kHz
Clock High Period 600 ns
Clock Low Period 1300 ns
Start Condition Setup Time (for a Repeated Start Condition) 600 ns
Start Condition Hold Time 600 ns
Data in Setup Time 100 ns
Data in Hold Time 0 ns
Stop Condition Setup Time 600 ns
Time the bus must be free before a new transmission can start 1300 ns
SDA and SCL Rise Time 300 ns
SDA and SCL Fall Time 300 ns
Data Out Hold Time 100 ns
Noise Suppression Time Constant at SCL, SDA Inputs 50 ns
SCL Low to SDA Data Out and ACK Out 1
Test Conditions Max Units
= 0V 8 pF
I/O
Parameter Max Units
20
Parameter Min Typ Max Units
ms
ms
ms
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4
CAT5191
TYPICAL CHARACTERISTICS
0.03
0.02
0.01
0
−0.01
−0.02
ERROR (LSB)
−0.03
−0.04
−0.05
120
100
80
60
Rw (W)
40
20
DNL
192
TAP TAP
Figure 2. Differential Non−Linearity,
V
= 5.6 V
DD
VDD = 2.6 V
3.3 V
4.0 V
5.6 V
2562241601289664320
0.1
0
−0.1
−0.2
ERROR (LSB)
−0.3
−0.4
−0.5
6
5
4
3
Vw (V)
2
1
INL
Figure 3. Integral Non−Linearity,
VDD = 5.6 V
VDD = 2.6 V
2241921601289664320
5.6 V
5.0 V
4.0 V
3.3 V
256
−6
−12
−18
A (dB)
−24
−30
−36
0
250200150100500
TAP TAP
Figure 4. Wiper Resistance at Room
0
Figure 5. Wiper Voltage
Temperature
0
VDD = 5 V
VDD = 3 V
1000100101
f (KHz) f (KHz)
30
25
20
15
PSRR (dB)
10
5
0
Figure 6. Gain vs. Bandwidth (Tap 0x80) Figure 7. PSRR
260208156104520
VDD = 5 V
VDD = 3 V
1000100101
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5
CAT5191
A
BASIC OPERATION
The CAT5191 is a 256-position digitally controlled
potentiometer. When power is first applied, the wiper
assumes a mid-scale position. Once the power supply is
PROGRAMMING: VARIABLE RESISTOR
stable, the wiper may be repositioned via the I
interface.
2
C compatible
Rheostat Mode
The resistance between terminals A and B, RAB, has a
nominal value of 50 kW or 100 kW and has 256 contact
points accessed by the wiper terminal, plus the B terminal
contact. Data in the 8-bit Wiper register is decoded to select
one of these 256 possible settings.
The wiper’s first connection is at the B terminal,
corresponding to control position 0x00. Ideally this would
present a 0 W between the Wiper and B, but just as with a
mechanical rheostat there is a small amount of contact
resistance to be considered, there is a wiper resistance
comprised of the R
of the FET switch connecting the
ON
wiper output with its respective contact point. In CAT5191
this ‘contact’ resistance is typically 50 W. Thus a connection
setting of 0x00 yields a minimum resistance of 50 W
between terminals W and B.
For a 100 kW device, the second connection, or the first tap
point, corresponds to 441 W (R
= RAB/256 + RW = 390.6
WB
+ 50 W) for data 0x01. The third connection is the next tap
point, is 831 W (2 x 390.6 + 50 W) for data 0x02, and so on.
Figure 8 shows a simplified equivalent circuit where the last
resistor string will not be accessed; therefore, there is 1 LSB
less of the nominal resistance at full scale in addition to the
wiper resistance.
R
S
R
S
Wiper
Register
and
Decoder
Figure 8. CAT5191 Equivalent Digital POT Circuit
R
S
W
R
S
B
The equation for determining the digitally programmed
output resistance between W and B is
WB
+
D
256
RAB) R
W
(eq. 1)
R
where D is the decimal equivalent of the binary code loaded
in the 8-bit Wiper register, R
is the end-to-end resistance,
AB
and R
is the wiper resistance contributed by the on
W
resistance of the internal switch.
In summary, if R
circuited, the following output resistance R
= 100 kW and the A terminal is open
AB
will be set for
WB
the indicated Wiper register codes:
Table 9. CODES AND CORRESPONDING R
RESISTANCE FOR RAB = 100 kW, VDD = 5 V
D (Dec.)
255 99,559 Full Scale (RAB – 1 LSB + RW)
128 50,050 Midscale
1 441 1 LSB
0 50 Zero Scale
RWB (W)
(Wiper Contact Resistance)
Output State
WB
Be aware that in the zero-scale position, the wiper
resistance of 50 W is still present. Current flow between W
and B in this condition should be limited to a maximum
pulsed current of no more than 20 mA. Failure to heed this
restriction can cause degradation or possible destruction of
the internal switch contact.
Similar to the mechanical potentiometer, the resistance of
the digital POT between the wiper W and terminal A also
produces a digitally controlled complementary resistance
R
. When these terminals are used, the B terminal can be
WA
opened. Setting the resistance value for R
starts at a
WA
maximum value of resistance and decreases as the data
loaded in the latch increases in value. The general equation
for this operation is
RWA(D) +
256 * D
256
RAB) R
W
(eq. 2)
For RAB = 100 kW and the B terminal open circuited, the
following output resistance R
will be set for the indicated
WA
Wiper register codes.
Table 10. CODES AND CORRESPONDING R
RESISTANCE FOR RAB = 100 kW, VDD = 5 V
D (Dec.)
255 441 Full Scale
128 50,050 Midscale
1 99,659 1 LSB
0 100,050 Zero Scale
RWA (W)
Output State
WA
Typical device to device resistance matching is lot
dependent and may vary by up to ±20%.
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6
CAT5191
ESD Protection
Digital
Input
GND
W, A, B
GND
LOGIC
Potentiometer
Figure 9. ESD Protection Networks
Terminal Voltage Operating Range
The CAT5191 VDD and GND power supply define the
limits for proper 3-terminal digital potentiometer operation.
Signals or potentials applied to terminals A, B or the wiper
must remain inside the span of V
and GND. Signals
DD
which attempt to go outside these boundaries will be
clamped by the internal forward biased diodes.
V
DD
Power-up Sequence
Because ESD protection diodes limit the voltage
compliance at terminals A, B, and W (see Figure 9), it is
recommended that V
/GND be powered before applying
DD
any voltage to terminals A, B, and W. The ideal power−up
sequence is: GND, V
order of powering V
important as long as they are powered after V
Power Supply Bypassing
, digital inputs, and then V
DD
, VB, VW, and the digital inputs is not
A
DD
A/B/W
/GND.
. The
Good design practice employs compact, minimum lead
length layout design. Leads should be as direct as possible.
It is also recommended to bypass the power supplies with
quality low ESR Ceramic chip capacitors of 0.01 mF to
0.1 mF. Low ESR 1 mF to 10 mF tantalum or electrolytic
capacitors can also be applied at the supplies to suppress
transient disturbances and low frequency ripple. As a further
precaution digital ground should be joined remotely to the
analog ground at one point to minimize the ground bounce.
V
DD
C
3
10 mF
+
C
0.1 mF
Figure 11. Power Supply Bypassing
V
DD
1
CAT5191
GND
W, A, B
LOGIC
GND
CAT5191
Figure 10.
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7
CAT5191
I2C BUS PROTOCOL
2
The following defines the features of the I
C bus protocol:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high
will be interpreted as a START or STOP condition.
The device controlling the transfer is a master, typically a
processor or controller , and the device being controlled is th e
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations.
Therefore, the CAT5191 will be considered a slave device
in all applications.
START Condition
The START condition precedes all commands to the
device, and is defined as a high to low transition of SDA
when SCL is high. The CAT5191 monitors the SDA and
SCL lines and will not respond until this condition is met.
STOP Condition
A low to high transition of SDA when SCL is high
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
The bus Master begins a transmission by sending a
START condition. The Master then sends the address of the
particular slave device it is requesting. The six most
significant bits of the 8-bit slave address are fixed as 010110
for the CAT5191. The next bit (AD0) is the device least
significant address bit and defines which device the Master
is accessing. Up to two devices may be individually
addressed by the system. Typically, +5 V (V
) or ground
DD
is hard-wired to the AD0 pin to establish the device’s
address.
After the Master sends a START condition and the slave
address byte, the CAT5191 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
The CAT5191 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8-bit
byte.
When the CAT5191 is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for an
acknowledge. Once it receives this acknowledge, the
CAT5191 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
Write Operation
In the Write mode, the Master device sends the START
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte. After receiving another
acknowledge from the Slave, the Master device transmits
the data to be written into the wiper register. The CAT5191
acknowledges once more and the Master generates the
STOP condition.
SCL
SDAIN
SDAOUT
t
SU:STA
t
F
t
LOW
t
HD:STA
t
HIGH
t
LOW
t
HD:DAT
t
AA
Figure 12. Bus Timing Diagram
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8
t
DH
t
R
t
SU:DAT
t
SU:STO
t
BUF
SDA
SCL
CAT5191
START CONDITION
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
Figure 13. Start/Stop Condition
1
Figure 14. Acknowledge Condition
STOP CONDITION
89
ACKNOWLEDGE
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9
CAT5191
INSTRUCTION AND REGISTER DESCRIPTION
Slave Address Byte
The first byte sent to the CAT5191 from the
power-up, the wiper is set to midscale and may be
repositioned anytime after the power has become stable.
master/processor is called the Slave Address Byte. The most
significant six bits of the slave address are a device type
identifier. For the CAT5191, these bits are fixed at 010110.
The next bit, AD0, is the first bit of the internal slave
address and must match the physical device address which
is defined by the state of the AD0 input pin for the CAT5191
to successfully continue the command sequence. Only the
device which slave address matches the incoming device
address sent by the master executes the instruction. The AD0
input can be actively driven by CMOS input signals or tied
to the supply voltage or ground.
The next bit, R/W
, indicates whether this command
corresponds to a Write or Read instruction. To write into the
Wiper control register, R/W
bit is set to a logic low; while a
read from the wiper register is done with the bit high.
Instructions
Write and Read instructions are respectively three and two
bytes in length. The basic sequence of the two instructions
is illustrated in Table 11 and 12.
In write mode, the second byte is the instruction byte. The
first bit (MSB) of the instruction byte is a don’t care. The
second MSB, RS, is the midscale reset. A logic high on this
bit moves the wiper to the center tap. The third MSB, SD, is
a shutdown bit. A logic high causes an open circuit at
terminal A, and short the wiper terminal W to terminal B.
The “shutdown” operation does not change the contents of
the wiper register. When the shutdown bit, SD, goes back to
a logic low, the previous wiper position is restored. Also
during shutdown, new settings can be programmed. As soon
as the device is returned from shutdown, the wiper position
Wiper Control
is set according to the wiper register value.
The CAT5191 contains one 8-bit Wiper Control Register
(WCR). The Wiper Control Register output is decoded to
select one of 256 switches along its resistor array. The
contents of the WCR may be written by the host via Write
instruction.
The Wiper Control Register is a volatile register that loses
its contents when the CAT5191 is powered-down. Upon
Two CAT5191 on a Single Bus
When needed, it is possible to connect two CAT5191
2
potentiometers on the same I
C bus and be able to address
each one independently. Each device can be set to a unique
address by using the AD0 input pin. One device AD0 pin is
connected to ground, and the other device AD0 pin is tied to
the supply voltage.
Table 11. Write
S 0 1 0 1 1 0 AD0 W A X RS SD X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Instruction Byte Data Byte
SDA
0 1 0 1 1 0 AD0
S
T
A
R
T
Slave Address Byte
R/W
RS SD X D6 D5 D4 D3 D2 D1 D0
XXXXX
A
C
K
Instruction Byte Data Byte
D7
A
C
K
S
A
T
C
O
K
P
Table 12. READ
S 0 1 0 1 1 0 AD0 R A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Data Byte
SDA
S
T
A
R
T
Legend
S = Start
P = Stop
A = Acknowledge
AD0 = Address bit 0, needed when using two
D = Data bit
R = Read (bit is 1 for Read instruction)
0 1 0 1 1 0 AD0
Slave Address Byte
R/W
potentiometers on the same I
A
C
K
2
C bus.
D7
D6 D5 D4 D3 D2 D1 D0
Data Byte
W
= Write (bit is 0 for Write instruction)
RS = When the bit is 1, the wiper position is moved
to mid-scale 0x80
SD = Shut Down:
0: normal operation
1: wiper is parked at B terminal and terminal A
is open circuit.
X = Don’t Care
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10
N
A
C
K
S
T
O
P
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23, 8 Lead
CASE 527AK−01
ISSUE A
DATE 18 MAR 2009
eb
PIN #1 IDENTIFICATION
TOP VIEW
D
A
A3
EE1
A2
SYMBOL
A
A1
A2
MIN NOM MAX
0.90
0.00
0.90
1.10
1.45
0.15
1.30
A3 0.60 0.80
b
c
D
E
E1
e
L
0.28
0.08
0.38
0.22
2.90 BSC
2.80 BSC
1.60 BSC
0.65 BSC
0.30 0.60
0.45
L1 0.60 REF
L2
0.25 REF
θ0° 8°
q
c
A1
L1 L2L
SIDE VIEW END VIEW
Notes:
(1) All dimensions in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-178.
DOCUMENT NUMBER:
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SOT−23, 8 LEAD
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