ON Semiconductor CAT25512 User Manual

EEPROM Serial 512-Kb SPI

CAT25512

Description

The CAT25512 is a EEPROM Serial 512−Kb SPI device internally organized as 64Kx8 bits. This features a 128−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD communication with the CAT25512 device. The device features software and hardware write protection, including partial as well as full array protection.

On−Chip ECC (Error Correction Code) makes the device suitable for high reliability applications.

Features

• 20 MHz SPI Compatible

• 1.8 V to 5.5 V Supply Voltage Range

• SPI Modes (0,0) & (1,1)

• 128−byte Page Write Buffer

• Additional Identification Page with Permanent Write Protection

• Self−timed Write Cycle

• Hardware and Software Protection

• Block Write Protection

− Protect

/4, 1/2 or Entire EEPROM Array

• Low Power CMOS Technology

• 1,000,000 Program/Erase Cycles

• 100 Year Data Retention

• Industrial and Extended Temperature Range

• SOIC, TSSOP 8−lead, UDFN 8−pad

• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS

Compliant

HOLD

SCK

Figure 1. Functional Symbol

input may be used to pause any serial

CAT25512

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SOIC−8

V SUFFIX

CASE 751BD

TSSOP−8 Y SUFFIX

CASE 948AL

PIN CONFIGURATIONS

SOIC (V, X), TSSOP (Y), UDFN (HU5)

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.

(Top View)

PIN FUNCTION

Chip SelectCS

Serial Data OutputSO

Write ProtectWP

GroundV

Serial Data InputSI

Serial ClockSCK

Hold Transmission InputHOLD

Power SupplyV

UDFN−8

HU5 SUFFIX

CASE 517BU

SOIC−8 WIDE

X SUFFIX

CASE 751BE

HOLD

SCK

FunctionPin Name

December, 2020 − Rev. 11

1 Publication Order Number:

CAT25512/D

CAT25512

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameters Ratings Units

Operating Temperature −45 to +130 °C

Storage Temperature −65 to +150 °C

Voltage on any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V

undershoot to no less than −1.5 V or overshoot to no more than V

+ 1.5 V, for periods of less than 20 ns.

Table 2. RELIABILITY CHARACTERISTICS (Note 2)

Symbol

(Note 3, 4) Endurance 1,000,000 Program / Erase Cycles

END

Data Retention 100 Years

2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

3. Write Mode: groups of 4 bytes, 25°C.

4. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte

has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order to benefit from the maximum number of write cycles.

Parameter Max Units

Table 3. D. C. OPERATING CHARACTERISTICS

(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified)

Symbol

CCR

CCW

SB1

SB2

IL1

IH1

IL2

IH2

OL1

OH1

OL2

OH2

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

Parameter Test Conditions Min Max Units

Supply Current

(Read Mode)

Read, SO open /

−40°C to +85°C

VCC = 1.8 V, f

= 2.5 V, f

VCC = 5.5 V, f

Supply Current

(Write Mode)

Read, SO open /

−40°C to +125°C

Write, CS = VCC/

−40°C to +85°C

Write, CS = VCC/

2.5 V < VCC < 5.5 V, f

SCK

1.8 V < VCC < 5.5 V 2 mA

2.5 V < VCC < 5.5 V 2 mA

−40°C to +125°C

Standby Current VIN = GND or VCC,

= VCC, WP = VCC, HOLD = VCC, VCC = 5.5 V

Standby Current VIN = GND or VCC,

TA = −40°C to +85°C 1

TA = −40°C to +125°C 3

TA = −40°C to +85°C 3 CS = VCC, WP = GND, HOLD = GND, VCC = 5.5 V

Input Leakage Current VIN = GND or V

Output Leakage

Current

CS = V V

OUT

= GND or V

TA = −40°C to +125°C 5

Input Low Voltage VCC ≥ 2.5 V −0.5 0.3V

Input High Voltage VCC ≥ 2.5 V 0.7V

Input Low Voltage VCC < 2.5 V −0.5 0.25V

Input High Voltage VCC < 2.5 V 0.75V

Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V

Output High Voltage VCC ≥ 2.5 V, IOH = −1.6 mA VCC − 0.8V V

Output Low Voltage

Output High Voltage

VCC < 2.5 V, IOL = 150 mA

VCC < 2.5 V, IOH = −100 mA

+ 0.5 V. During transitions, the voltage on any pin may

= 5 MHz 1.2 mA

SCK

= 10 MHz 1.8 mA

SCK

= 20 MHz 3 mA

SCK

3 mA

= 10 MHz

−2 2

VCC + 0.5 V

0.2 V

VCC − 0.2V V

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CAT25512

Table 4. PIN CAPACITANCE (T

Symbol

OUT

Output Capacitance (SO) V

Input Capacitance (CS, SCK, SI, WP, HOLD) VIN = 0 V 8 pF

Table 5. A.C. CHARACTERISTICS (T

Symbol

SCK

Clock Frequency DC 5 DC 10 DC 20 MHz

Data Setup Time 20 10 5 ns

Data Hold Time 20 10 5 ns

SCK High Time 75 40 20 ns

SCK Low Time 75 40 20 ns

HOLD to Output Low Z 50 25 25 ns

= 25°C, f = 1.0 MHz, VCC = +5.0 V) (Note 2)

Test Conditions Min Typ Max Units

= −40°C to +125°C, unless otherwise specified.) (Note 5)

VCC = 1.8 V − 5.5 V

−405C to +855C

Parameter

Min Max Min Max Min Max

= 0 V 8 pF

OUT

VCC = 2.5 V − 5.5 V

−405C to +1255C

VCC = 4.5 V − 5.5 V

−405C to +855C

tRI (Note 6) Input Rise Time 2 2 2

tFI (Note 6) Input Fall Time 2 2 2

CSS

CSH

CNS

CNH

WPS

WPH

DIS

HOLD Setup Time 0 0 0 ns

HOLD Hold Time 10 10 5 ns

Output Valid from Clock Low 75 40 20 ns

Output Hold Time 0 0 0 ns

Output Disable Time 50 20 20 ns

HOLD to Output High Z 100 25 25 ns

CS High Time 80 40 20 ns

CS Setup Time 60 30 15 ns

CS Hold Time 60 30 15 ns

CS Inactive Setup Time 60 30 15

CS Inactive Hold Time 60 30 15

WP Setup Time 10 10 10 ns

WP Hold Time 10 10 10 ns

tWC (Note 7) Write Cycle Time 5 5 5 ms

5. AC Test Conditions: Input Pulse Voltages: 0.3 V Input rise and fall times: ≤ 10 ns Input and output reference voltages: 0.5 V Output load: current source I

6. This parameter is tested initially and after a design or process change that affects the parameter.

is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.

7. t

to 0.7 V

OL max/IOH max

; CL = 30 pF

Units

Table 6. POWER−UP TIMING (Notes 6, 8)

Symbol Parameter Max Units

8. t

PUR

PUW

and t

PUW

Power−up to Read Operation 1 ms

Power−up to Write Operation 1 ms

are the delays required from the time VCC is stable until the specified operation can be initiated.

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CAT25512

Pin Description

SI: The serial data input pin accepts op−codes, addresses and data. In SPI modes (0,0) and (1,1) input data is latched on the rising edge of the SCK clock input.

SO: The serial data output pin is used to transfer data out of the device. In SPI modes (0,0) and (1,1) data is shifted out on the falling edge of the SCK clock.

SCK: The serial clock input pin accepts the clock provided by the host and used for synchronizing communication between host and CAT25512.

: The chip select input pin is used to enable/disable the

CAT25512. When CS

is high, the SO output is tri−stated (high impedance) and the device is in Standby Mode (unless an internal write operation is in progress). Every communication

session between host and CAT25512 must be preceded by a high to low transition and concluded with a low to high transition of the CS

input.

WP: The write protect input pin will allow all write operations to the device when held high. When WP

pin is tied low and the WPEN bit in the Status Register (refer to Status Register description, later in this Data Sheet) is set to “1”, writing to the Status Register is disabled.

: The HOLD input pin is used to pause transmission

HOLD

between host and CAT25512, without having to retransmit the entire sequence at a later time. To pause, HOLD

must be taken low and to resume it must be taken back high, with the SCK input low during both transitions. When not used for pausing, it is recommended the HOLD V

, either directly or through a resistor.

input to be tied to

Functional Description

The CAT25512 device supports the Serial Peripheral Interface (SPI) bus protocol, modes (0,0) and (1,1). The device contains an 8−bit instruction register. The instruction set and associated op−codes are listed in Table 7.

Reading data stored in the CAT25512 is accomplished by simply providing the READ command and an address. Writing to the CAT25512, in addition to a WRITE command, address and data, also requires enabling the device for writing by first setting certain bits in a Status Register, as will be explained later.

After a high to low transition on the CS

input pin, the CAT25512 will accept any one of the six instruction op−codes listed in Table 7 and will ignore all other possible 8−bit combinations. The communication protocol follows the timing from Figure 2.

The CAT25512 features an additional Identification Page (128 bytes) which can be accessed for Read and Write operations when the IPL bit from the Status Register is set to “1”. The user can also choose to make the Identification Page permanent write protected.

Table 7. INSTRUCTION SET

Instruction Opcode Operation

WREN 0000 0110 Enable Write Operations

WRDI 0000 0100 Disable Write Operations

RDSR 0000 0101 Read Status Register

WRSR 0000 0001 Write Status Register

READ 0000 0011 Read Data from Memory

WRITE 0000 0010 Write Data to Memory

SCK

CNH

HI−Z

CSS

VALID

CSH

VALID

OUT

DIS

CNS

HI−Z

Figure 2. Synchronous Data Timing

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CAT25512

Status Register

The Status Register, as shown in Table 8, contains a

number of status and control bits.

The RDY

(Ready) bit indicates whether the device is busy with a write operation. This bit is automatically set to 1 during an internal write cycle, and reset to 0 when the device is ready to accept commands. For the host, this bit is read only.

The WEL (Write Enable Latch) bit is set/reset by the WREN/WRDI commands. When set to 1, the device is in a Write Enable state and when set to 0, the device is in a Write Disable state.

The BP0 and BP1 (Block Protect) bits determine which blocks are currently write protected. They are set by the user with the WRSR command and are non−volatile. The user is allowed to protect a quarter, one half or the entire memory, by setting these bits according to Table 9. The protected blocks then become read−only.

The WPEN (Write Protect Enable) bit acts as an enable for the WP

pin. Hardware write protection is enabled when the

pin is low and the WPEN bit is 1. This condition

prevents writing to the status register and to the block

Table 8. STATUS REGISTER

7 6 5 4 3 2 1 0

WPEN IPL 0 LIP BP1 BP0 WEL RDY

protected sections of memory. While hardware write protection is active, only the non−block protected memory can be written. Hardware write protection is disabled when

pin is high or the WPEN bit is 0. The WPEN bit, WP

the WP pin and WEL bit combine to either permit or inhibit Write operations, as detailed in Table 10.

The IPL (Identification Page Latch) bit determines whether the additional Identification Page (IPL = 1) or main memory array (IPL = 0) can be accessed both for Read and Write operations. The IPL bit is set by the user with the WRSR command and is volatile. The IPL bit is automatically reset after read/write operations.

The LIP (Lock Identification Page) bit is set by the user with the WRSR command and is non−volatile. When set to 1, the Identification Page is permanently write protected (locked in Read−only mode).

Note: The IPL and LIP bits cannot be set to 1 using the same WRSR instruction. If the user attempts to set (“1”) both the IPL and LIP bit in the same time, these bits cannot be written and therefore they will remain unchanged.

Table 9. BLOCK PROTECTION BITS

Status Register Bits

BP1 BP0

0 0 None No Protection

0 1 C000−FFFF Quarter Array Protection

1 0 8000−FFFF Half Array Protection

1 1 0000−FFFF Full Array Protection

Table 10. WRITE PROTECT CONDITIONS

WPEN WP WEL Protected Blocks Unprotected Blocks Status Register

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected

X High 0 Protected Protected Protected

X High 1 Protected Writable Writable

Array Address Protected Protection

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