ON Semiconductor CAT24C01, CAT24C04, CAT24C02, CAT24C16, CAT24C08 User Manual

CAT24C01, CAT24C02,
CAT24C04, CAT24C08,
CAT24C16

1-Kb, 2-Kb, 4-Kb, 8-Kb and

2

16-Kb I

C CMOS Serial

EEPROM

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Description

The CAT24C01/02/04/08/16 are 1−Kb, 2−Kb, 4−Kb, 8−Kb and
16−Kb respectively CMOS Serial EEPROM devices organized
internally as 8/16/32/64 and 128 pages respectively of 16 bytes each.
All devices support both the Standard (100 kHz) as well as Fast
(400 kHz) I

2

C protocol.

Data is written by providing a starting address, then loading 1 to 16
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.

External address pins make it possible to address up to eight
CAT24C01 or CAT24C02, four CAT24C04, two CAT24C08 and one
CAT24C16 device on the same bus.

Features

• Supports Standard and Fast I

2

C Protocol

• 1.7 V to 5.5 V Supply Voltage Range

• 16−Byte Page Write Buffer

• Hardware Write Protection for Entire Memory

• Schmitt Triggers and Noise Suppression Filters on I

(SCL and SDA)

2

C Bus Inputs

• Low power CMOS Technology

• More than 1,000,000 Program/Erase Cycles

• 100 Year Data Retention

• Industrial and Extended Temperature Range

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

PIN CONFIGURATION

CAT24C__

16 / 08 / 04 / 02 / 01

////

NC

NC NC

////

NC NC

NC

A1A1A

////

A2A2A

A

2

A

A

0

0

1

2

V

SS

8

1

7

2

6

3

5

4

V

CC

WP

SCL

SDA

PDIP−8

L SUFFIX

CASE 646AA

MSOP−8

Z SUFFIX

CASE 846AD

TSSOP−8
Y SUFFIX

CASE 948AL

SOIC−8

W SUFFIX

CASE 751BD

TDFN−8*

VP2 SUFFIX

CASE 511AK

UDFN8−EP

HU4 SUFFIX

CASE 517AZ

TSOT−23

TD SUFFIX

CASE 419AE

TSOP−5**

TS SUFFIX

CASE 483

WLCSP−4***
C4A SUFFIX

CASE 567DC

WLCSP−5***
C5A SUFFIX

CASE 567DD

PIN CONFIGURATIONS

SCL

V

SS

SDA

TSOT−23 (TD), TSOP−5** (TS) (Top View)

** TSOP are available for the CAT24C02 only.

Pin 1

A

V

B

SCL SDA

WLCSP−4*** WLCSP−5***

*** WLCSP are available for the CAT24C04,
CAT24C08 and CAT24C16 only.

Pin 1

V

CC

SS

(Top Views)

TOP MARKING FOR WLCSP

(Ball Down)

5

1

2

3

4

Pin 1

WP

V

CC

12312

V

CC

SDA

WP SCL

A

V

SS

B

C

Pin 1

PDIP (L), SOIC (W), TSSOP (Y), MSOP (Z),
TDFN, (VP2)*, UDFN−EP (HU4) (Top View)

* The TDFN (VP2) package is not recommended for new designs.

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.

© Semiconductor Components Industries, LLC, 2013

February, 2013 − Rev. 26

X X

Y M Y M

WLCSP−4 WLCSP−5

Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)

1 Publication Order Number:

X = Specific Device

X = Code

4 = 24C04
8 = 24C08
6 = 24C16

CAT24C01/D

CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16

V

CC

SCL

A2, A1, A

0

CAT24Cxx

SDA

WP

V

SS

Figure 1. Functional Symbol

Table 2. ABSOLUTE MAXIMUM RATINGS

Parameters Ratings Units

Storage Temperature −65 to +150 °C

Voltage on any pin with respect to Ground (Note 1) −0.5 to +6.5 V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

1. During input transitions, voltage undershoot on any pin should not exceed −1 V for more than 20 ns. Voltage overshoot on pins A

and WP should not exceed VCC + 1 V for more than 20 ns, while voltage on the I2C bus pins, SCL and SDA, should not exceed the absolute
maximum ratings, irrespective of V

CC

.

Table 1. PIN FUNCTION

Pin Name

A0, A1, A2 Device Address Input

†The exposed pad for the TDFN/UDFN packages can be left floating

or connected to Ground.

†

Function

SDA Serial Data Input/Output

SCL Serial Clock Input

WP Write Protect Input

V

CC

V

SS

Power Supply

Ground

NC No Connect

, A1, A

0

2

Table 3. RELIABILITY CHARACTERISTICS (Note 2)

Symbol

N

(Note 3) Endurance 1,000,000 Program / Erase Cycles

END

T

DR

Data Retention 100 Years

2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

3. Page Mode, V

= 5 V, 25°C.

CC

Parameter Min Units

Table 4. D.C. OPERATING CHARACTERISTICS

(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)

Symbol

I

CCR

I

CCW

I

SB

I

L

V

IL

V

IH

V

OL

Parameter Test Conditions Min Max Units

Read Current Read, f

Write Current Write, f

Standby Current All I/O Pins at GND or V

= 400 kHz 1 mA

SCL

= 400 kHz 2 mA

SCL

TA = −40°C to +85°C

CC

V

CC

TA = −40°C to +85°C
V

CC

≤ 3.3 V

> 3.3 V

1 mA

3

TA = −40°C to +125°C 5

I/O Pin Leakage Pin at GND or V

CC

Input Low Voltage −0.5 0.3 x V

Input High Voltage

Output Low
Voltage

A0, A1, A2 and WP 0.7 x V

SCL and SDA 0.7 x V

CC

CC

VCC > 2.5 V, IOL = 3 mA 0.4

VCC < 2.5 V, IOL = 1 mA 0.2

2

CC

VCC + 0.5

5.5

mA

V

V

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CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16

Table 5. PIN IMPEDANCE CHARACTERISTICS

(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)

Symbol

C

(Note 4)

IN

SDA Pin Capacitance

Other Pins 6 pF

IWP (Note 5) WP Input Current

IA (Note 5) Address Input Current

(A0, A1, A2)
Product Rev H: CAT24C02
Product Rev K: CAT24C04,
CAT24C08, CAT24C16

4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is

relatively strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To
conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak
current source.

Table 6. A.C. CHARACTERISTICS

(Note 6) (VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)

Symbol

F

SCL

t

HD:STA

t

LOW

t

HIGH

t

SU:STA

t

HD:DAT

t

SU:DAT

t

R

tF (Note 6) SDA and SCL Fall Time 300 300 ns

t

SU:STO

t

BUF

t

AA

t

DH

Ti (Note 6) Noise Pulse Filtered at SCL and SDA Inputs 100 100 ns

t

SU:WP

t

HD:WP

t

WR

tPU (Notes 7, 8) Power−up to Ready Mode 1 1 ms

6. Test conditions according to “AC Test Conditions” table.

7. Tested initially and after a design or process change that affects this parameter.

is the delay between the time VCC is stable and the device is ready to accept commands.

8. t

PU

Clock Frequency 100 400 kHz

START Condition Hold Time 4 0.6

Low Period of SCL Clock 4.7 1.3

High Period of SCL Clock 4 0.6

START Condition Setup Time 4.7 0.6

Data In Hold Time 0 0

Data In Setup Time 250 100 ns

SDA and SCL Rise Time 1000 300 ns

STOP Condition Setup Time 4 0.6

Bus Free Time Between STOP and START 4.7 1.3

SCL Low to Data Out Valid 3.5 0.9

Data Out Hold Time 100 100 ns

WP Setup Time 0 0

WP Hold Time 2.5 2.5

Write Cycle Time 5 5 ms

Parameter Conditions Max Units

VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V

8 pF

VIN < VIH, VCC = 5.5 V 130 mA

VIN < VIH, VCC = 3.3 V 120

VIN < VIH, VCC = 1.7 V 80

VIN > V

IH

2

VIN < VIH, VCC = 5.5 V 50 mA

VIN < VIH, VCC = 3.3 V 35

VIN < VIH, VCC = 1.7 V 25

VIN > V

IH

2

Standard Fast

Parameter

Min Max Min Max

Units

ms

ms

ms

ms

ms

ms

ms

ms

ms

ms

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CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16

Table 7. A.C. TEST CONDITIONS

Input Drive Levels 0.2 x VCC to 0.8 x V

Input Rise and Fall Time v 50 ns

Input Reference Levels 0.3 x VCC, 0.7 x V

Output Reference Level 0.5 x V

Output Test Load Current Source IOL = 3 mA (VCC w 2.5 V); IOL = 1 mA (V

CC

CC

CC

< 2.5 V); CL = 100 pF

CC

Power−On Reset (POR)

Each CAT24Cxx* incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.

A CAT24Cxx device will power up into Standby mode
after V
down into Reset mode when V

exceeds the POR trigger level and will power

CC

drops below the POR

CC

trigger level. This bi−directional POR feature protects the
device against ‘brown−out’ failure following a temporary
loss of power.

*For common features, the CAT24C01/02/04/08/16 will be
referred to as CAT24Cxx.

Pin Description

SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.

SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.

A0, A1 and A2: The Address inputs set the device address
when cascading multiple devices. When not driven, these
pins are pulled LOW internally.

WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this pin is
pulled LOW internally.

Functional Description

The CAT24Cxx supports the Inter−Integrated Circuit

2

(I

C) Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT24Cxx acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver.

I2C Bus Protocol

The I2C bus consists of two ‘wires’, SCL and SDA. The

two wires are connected to the V

supply via pull−up

CC

resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.

Data transfer may be initiated only when the bus is not

busy (see AC Characteristics).

During data transfer, the SDA line must remain stable
while the SCL line is high. An SDA transition while SCL is
high will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake−up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.

NOTE: The I/O pins of CAT24Cxx do not obstruct the SCL
and SDA lines if the VCC supply is switched off. During
power−up, the SCL and SDA pins (connected with pull−up
resistors to VCC) will follow the VCC monotonically from
VSS (0 V) to nominal VCC value, regardless of pull−up
resistor value. The delta between the VCC and the
instantaneous voltage levels during power ramping will be
determined by the relation between bus time constant
(determined by pull−up resistance and bus capacitance) and
actual VCC ramp rate.

Device Addressing

The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. For normal Read/Write operations, the
first 4 bits of the Slave address are fixed at 1010 (Ah). The
next 3 bits are used as programmable address bits when
cascading multiple devices and/or as internal address bits.
The last bit of the slave address, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed. The 3
address space extension bits are assigned as illustrated in
Figure 3. A
address pins, and a

Acknowledge

, A1 and A0 must match the state of the external

2

, a9 and a8 are internal address bits.

10

After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge the address byte and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9

th

clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.

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4

CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16

SCL

SDA

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

START

CONDITION

STOP

CONDITION

Figure 2. Start/Stop Timing

1010A2A1A0R/W CAT24C01 and CAT24C02

1010A2A1a8R/W CAT24C04

1010A2a9a8R/W CAT24C08

1010a

10a9

a8R/W CAT24C16

Figure 3. Slave Address Bits

BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY

189

(RECEIVER)

DATA OUTPUT

FROM RECEIVER

SCL

SDA IN

SDA OUT

t

SU:STA

START

ACK DELAY (v t

AA

ACK SETUP (w t

)

SU:DAT

)

Figure 4. Acknowledge Timing

t

F

t

LOW

t

HD:SDA

t

HIGH

t

LOW

t

HD:DAT

t

AA

t

R

t

SU:DAT

t

DH

t

SU:STO

t

BUF

Figure 5. Bus Timing

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CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16

WRITE OPERATIONS

Byte Write

In Byte Write mode, the Master sends the START
condition and the Slave address with the R/W bit set to zero
to the Slave. After the Slave generates an acknowledge, the
Master sends the byte address that is to be written into the
address pointer of the CAT24Cxx. After receiving another
acknowledge from the Slave, the Master transmits the data
byte to be written into the addressed memory location. The
CAT24Cxx device will acknowledge the data byte and the
Master generates the STOP condition, at which time the
device begins its internal Write cycle to nonvolatile memory
(Figure 6). While this internal cycle is in progress (t

WR

), the
SDA output will be tri−stated and the CAT24Cxx will not
respond to any request from the Master device (Figure 7).

Page Write

The CAT24Cxx writes up to 16 bytes of data in a single
write cycle, using the Page Write operation (Figure 8). The
Page Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating after
the data byte is transmitted, the Master is allowed to send up
to fifteen additional bytes. After each byte has been
transmitted the CAT24Cxx will respond with an
acknowledge and internally increments the four low order
address bits. The high order bits that define the page address
remain unchanged. If the Master transmits more than sixteen
bytes prior to sending the STOP condition, the address
counter ‘wraps around’ to the beginning of page and
previously transmitted data will be overwritten. Once all

sixteen bytes are received and the STOP condition has been
sent by the Master, the internal Write cycle begins. At this
point all received data is written to the CAT24Cxx in a single
write cycle.

Acknowledge Polling

The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24Cxx initiates the internal write cycle.
The ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24Cxx is still busy
with the write operation, NoACK will be returned. If the
CAT24Cxx has completed the internal write operation, an
ACK will be returned and the host can then proceed with the
next read or write operation.

Hardware Write Protection

With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAT24Cxx. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAT24Cxx will not acknowledge the data byte
and the Write request will be rejected.

Delivery State

The CAT24Cxx is shipped erased, i.e., all bytes are FFh.

BUS ACTIVITY:

MASTER

SLAVE

* For the CAT24C01 a

S
T
A

SLAVE

R

ADDRESS

T

S

= 0

7

Figure 6. Byte Write Sequence

A
C
K

ADDRESS

BYTE

a

DATA

BYTE

− a

7

0

d7− d

0

A
C
K

S
T
O
P

P

A
C
K

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6

SCL

CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16

SDA

BUS ACTIVITY:

MASTER

SLAVE

S

T
A
R

T

S

n = 1
P v 15

SCL

th

Bit

Byte n

ACK8

t

WR

STOP
CONDITION

START
CONDITION

Figure 7. Write Cycle Timing

SLAVE

ADDRESS

A
C
K

ADDRESS

BYTE

DATA
BYTE

n n+1 n+P

A
C
K

DATA
BYTE

A
C
K

A
C
K

DATA
BYTE

Figure 8. Page Write Sequence

ADDRESS

BYTE

1891 8

DATA

BYTE

ADDRESS

S

T
O
P

A
C
K

P

SDA

WP

a

7

a

0

t

SU:WP

d

t

HD:WP

7

d

0

Figure 9. WP Timing

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