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AP0100CSSL00SPGAH-GEVB
AP0100CS Evaluation Board
User's Manual
Evaluation Board Overview
The evaluation boards are designed to demonstrate the features of
ON Semiconductor’s image sensors products. This headboard is
intended to plug directly into the Demo 2X system. Test points and
jumpers on the board provide access to the clock, I/Os, and other
miscellaneous signals.
Features
• Clock Input
♦ Default – 27 MHz Crystal Oscillator
♦ Optional Demo 2X Controlled MClk
• Two Wire Serial Interface
• Parallel Interface
• HiSPi (High Speed Serial Pixel) Interface
• ROHS Compliant
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EVAL BOARD USER’S MANUAL
Figure 1. AP0100CS Evaluation Board
Block Diagram
Figure 2. Block Diagram of AP0100CSSL00SPGAH−GEVB
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 0
1 Publication Order Number:
EVBUM2316/D
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Top View
AP0100CSSL00SPGAH−GEVB
Headboard Connector J8
Headboard Connector J7
EEPROM Sel P47, P48, P59
SPI_SCLK/CS_N P44
GPIO_DATA16 P37, P40, P41, P42
Bottom View
+2V8_VDDPHY P20
SEN_CLK P30
SEN_DATA P31
SPI_SDI_BAR P5
SPI Mem. Sel P7
TRST_BAR P3
ON_LED P11
Figure 3. Top View of the Board with Default Jumpers
1OE/2OE P54
SEN_RST_OUT P51
MCLK_IN P16
OSC/XTAL Sel P22, P23
VDD P26
Video Filter Sel P56, P57, P58
GPIO1_LED P17
RESET Switch SW7
STANDBY P6
+VCC P14
+SVDDIO P10
+HVDDIO P12
+3V3_VDDADAC P21
+AVDD P9
HiSPi Connector J2HiSPi Connector J1
Baseboard Connector J6
Baseboard Connector J5
Figure 4. Bottom View of the Board
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AP0100CSSL00SPGAH−GEVB
Jumper Pin Locations
The jumpers on headboards start with Pin 1 on the
leftmost side of the pin. Grouped jumpers increase in pin
size with each jumper added.
Figure 5. Pin Locations for a Single Jumper. Pin 1 is Located at the Leftmost Side
and Increases as it Moves to the Right
Pins 1−4Pin 1
Pins 1 and 2Pin 1
Pins 3 and 4
Pins 5 and 6
Pins 7 and 8
Pins 9 and 10
Figure 6. Pin Locations and Assignments of Grouped Jumpers.
Pin 1 is Located at the Top-Left Corner and Increases in a Zigzag Fashion Shown in the Picture
Jumper/Header Functions & Default Positions
Table 1. JUMPERS AND HEADERS
Jumper/Header No. Jumper/Header Name Pins Description
P3 TRST_BAR
P4 SADDR
P5 SPI_SDI_BAR
P6 STANDBY
P7 SPI Memory Selection
P8 GPIO_5
P9 +AVDD
P10 +SVDDIO
Open OTPM Programming Voltage Not Supplied
2−3 (Default) Set to Normal Mode
Open Set to Test Mode
Open Analog Test 1 Header
1−2 (Default) GND; AP0100 in Host Mode
Open SPI_SDI_SEL; AP0100 in Flash Mode
2−3 (Default) Active Mode
1−2 Standby Mode
Open I2C IO Expander Control
2−3 (Default) EEPROM Disable/Flash Enable
1−2 Flash Disable/EEPROM Enable
Open (Default) Serial IO expander Control
1−2 Set to Normal
2−3 Set to Vertical Flip
Closed (Default) Connects to On-Board Regulator +1V8, Internal
Regulator Use
Open Disconnects from On-Board Regulator +1V8, External
Regulator Use
3−5 Select Demo 3 Baseboard Clock
2−4 Select Slave Clock (for Slave Sensor in Multi-Camera
Mode)
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AP0100CSSL00SPGAH−GEVB
Table 1. JUMPERS AND HEADERS (continued)
Jumper/Header No. DescriptionPinsJumper/Header Name
P11 ON_LED 1−2 (Default) Connects to On-Board to Indicate Power On
P12 +HVDDIO
P14 +VCC
P15 +5V0
P16 MCLK_IN
P17 GPIO1_LED
P19 +AVDD
P20 +2V8_VDDPHY
P21 +3V3_VDDADAC
P22, P23 Oscillator/Xtal
Selection
P24 EXT_REG
P26 VDD
P28 UART Transceiver
P30 SEN_CLK
P31 SEN_DATA
P32 ENLDO
P33 GPIO1_LED
P34 GPIO_4
P35 GPIO_3
P36 GPIO_2
P37 GPIO_DATA16
1−2 (Default) Connects to On-Board +HVDDIO Power Supply
2−3 External Power Supply Connection
1−2 (Default) Connects to On-Board +VCC Power Supply
2−3 External Power Supply Connection
1−2 (Default) USB +5V0_BUS Power Supply Connection
2−3 Connects to On-Board +5V0_EXT Power Supply
1−2 (Default) Connects to On-Board Oscillator
2−3 Connects to XMCLK (i.e. Clock Signal from Demo 2
Open (Default) Off Frame LED
Closed On Frame LED
Closed (Default) Connects to On-Board Regulator +1V8, Internal
Open Disconnects from On-Board Regulator +1V8, External
1−2 (Default) Connects to On-Board +2V8_VDDPHY Power Supply
2−3 External Power Supply Connection
1−2 (Default) Connects to On-Board +3V3_VDDADAC Power Supply
2−3 External Power Supply Connection
P22 1−2,
P23 Open (Default)
P22 2−3,
P23 Closed
1−2 (Default) Internal Regulator
2−3 External Regulator
1−2 (Default) Internal Regulator +1V2_VDD
2−3 External On-Board Regulator U2 Set +1V2
Open (Default) Turn off UART Transceiver
Closed Turn on UART Transceiver
Open (Default) Beagle Serial No Access to Demo 2X & Sensor
1−2 Beagle Serial Access to Demo 2X & Sensor
Open (Default) Beagle Serial No Access to Demo 2X & Sensor
1−2 Beagle Serial Access to Demo 2X & Sensor
1−2 (Default) Enable Internal Regulator
2−3 Disable Internal Regulator
1−2 Set to GPI
2−3 Set to GPO
Open (Default) Serial IO Expander Control
1−2 Set to Normal
2−3 Set to Horizontal Mirror
Open (Default) Serial IO Expander Control
1−2 Set to NTSC
2−3 Set to PAL
Open (Default) Serial IO Expander Control
1−2 Set to No Pedestal
2−3 Set to Pedestal
1−2 (Default) Auto-Configuration Access
Open JTAG/UART Access
Baseboard)
Regulator Use
Regulator Use
Selects Oscillator as AP0100 Input Clock
Selects Crystal as AP0100 Input Clock
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AP0100CSSL00SPGAH−GEVB
Table 1. JUMPERS AND HEADERS (continued)
Jumper/Header No. DescriptionPinsJumper/Header Name
P38, P39 IO Expander U38
P40 GPIO_DATA17
P41 GPIO_DATA18
P42 GPIO_DATA19
P43 SP1_SDO/SDI
P44
P44
P45 SPI_SDI
P47, P48, P59 Serial I2C EEPROM
P49 SEN_SCLK
P50 SEN_SDATA
P51 SEN_RST_OUT
P52 BEAGLE_SCL
P53 BEAGLE_SDA
P54 1OE/2OE
P56, P57, P58 Video Filter Selection
SW7 RESET N/A When Pushed, 240 ms Reset Signal will be Sent to
Setting
SP1_SCLK/CS_N
Address
P39 Open,
P38 Closed (Default)
P39 Open,
P38 Open
P39 Closed,
P38 Open
P39 Closed,
P38 Closed
1−2 (Default) Auto-Configuration Access
Open JTAG/UART Access
1−2 (Default) Auto-Configuration Access
Open JTAG/UART Access
1−2 (Default) Auto-Configuration Access
Open JTAG/UART Access
1−2 (Default) Beagle SPI No Access to Sensor SPI
Open Beagle SPI Access to Sensor SPI
1−2 (Default) Beagle SPI No Access to Sensor SPI
Open Beagle SPI Access to Sensor SPI
Open (Default) Data or GND; AP0100 in Flash/Host Mode
1−2 High Z; AP0100 in Auto-Config Mode
P47 Closed,
P48 Open,
P59 Open
P47 Closed,
P48 Open,
P59 Open
P47 Open,
P48 Closed,
P59 Open
P47 Open,
P48 Open,
P59 Open
2−3 (Default) AP0100 Serial Control
1−2 Demo 2X Serial Control
2−3 (Default) AP0100 Serial Control
1−2 Demo 2X Serial Control
2−3 (Default) AP0100 Reset
1−2 Demo 2X Reset
1−2 (Default) Demo 2X Accessed
2−3 Sensor Accessed
1−2 (Default) Demo 2X Accessed
2−3 Sensor Accessed
1−2 (Default) Enable Level Transistor U9
2−3 Disable Level Transistor U9
1−2 (Default) Active Low Pass Filter
2−3 Discrete Low Pass Filter
EEPROM Address Set to 0x48
EEPROM Address Set to 0x4C
EEPROM Address Set to 0x44
EEPROM Address Set to 0x40
EEPROM Address Set to 0xAA (Default)
EEPROM Address Set to 0xA2
EEPROM Address Set to 0xA6
EEPROM Address Set to 0xAE
AP0100 Chip
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AP0100CSSL00SPGAH−GEVB
P
al
Interfacing to ON Semiconductor Demo 2X Baseboard
The ON Semiconductor 2X baseboard has a similar
26-pin connector and 13-pin connector which mate with J5
and J6 of the headboard. The four mounting holes secure the
baseboard and the headboard with spacers and screws.
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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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EVBUM2316/D
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