ON Semiconductor AP0100CSSL00SPGAH-GEVB, AP0100AT2L00XUGAH-GEVB User Manual

AP0100CSSL00SPGAH-GEVB
AP0100CS Evaluation Board User's Manual
Evaluation Board Overview
Features
Clock Input
Default – 27 MHz Crystal OscillatorOptional Demo 2X Controlled MClk
Two Wire Serial Interface
Parallel Interface
HiSPi (High Speed Serial Pixel) Interface
ROHS Compliant
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EVAL BOARD USER’S MANUAL
Figure 1. AP0100CS Evaluation Board
Block Diagram
Figure 2. Block Diagram of AP0100CSSL00SPGAH−GEVB
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 0
1 Publication Order Number:
EVBUM2316/D
Top View
AP0100CSSL00SPGAH−GEVB
Headboard Connector J8 Headboard Connector J7
EEPROM Sel P47, P48, P59
SPI_SCLK/CS_N P44
GPIO_DATA16 P37, P40, P41, P42
Bottom View
+2V8_VDDPHY P20
SEN_CLK P30
SEN_DATA P31
SPI_SDI_BAR P5
SPI Mem. Sel P7
TRST_BAR P3
ON_LED P11
Figure 3. Top View of the Board with Default Jumpers
1OE/2OE P54
SEN_RST_OUT P51
MCLK_IN P16 OSC/XTAL Sel P22, P23 VDD P26 Video Filter Sel P56, P57, P58
GPIO1_LED P17
RESET Switch SW7 STANDBY P6
+VCC P14 +SVDDIO P10
+HVDDIO P12
+3V3_VDDADAC P21
+AVDD P9
HiSPi Connector J2HiSPi Connector J1
Baseboard Connector J6 Baseboard Connector J5
Figure 4. Bottom View of the Board
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