ON Semiconductor AND9954/D User Manual

AND9954/D

Multi-Core Configuration of LC823455 Series for Audio Applications

Introduction

This application note describes multi−core configuration for the implementation of multi−core RTOS (Real Time Operating System).

First, the H/W requirements for the implementation of multi−core RTOS are described, and then the S/W requirements are described.

The intended audience is customers who are developing audio applications using LC823455 Series (called LC823455 hereafter).

BACKGROUND

Implemented Cores

LC823455 has two Arm® Cortex−M3 processors (Core0 and Core1) and one proprietary−DSP called LPDSP. LPDSP is used for audio processing, and its instruction set is different that of Cortex−M3 processor. Therefore, in LC823455 the two Cortex−M3 processors and the LPDSP are configured to heterogeneous multi−core architecture as outlined with the blue frame in Figure 1. On the other hand, as focus on the two Cortex−M3 processors they are configured to homogeneous dual−core architecture as outlined with the red frame in Figure 1.

Heterogeneous Multi-core Configuration

Homogeneous Dual-core Configuration

Arm Cortex -M3

(Core0)

Arm Cortex -M3

(Core1)

LPDSP

Figure 1. Core Configuration of LC823455

HARDWARE REQUIREMENTS

Memory Access from Cores

LC823455 has multiple bus masters including the two Cortex−M3 processors, and multiple bus slaves as described in Figure 2. The bus masters access the bus slaves via a bus matrix depicted by • in Figure 2.

Cortex−M3 processors (core0 and core1) can access all bus slaves except the LPDSP32−ROM. Access latency to a target bus slave from both cores of Cortex−M3 processors is the same if they both don’t access to same bus−slave at the same time. If they both try to access the same slave at the same time, one core will have to stall while the other one completes its access first.

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APPLICATION NOTE

Multiple bus masters can access different bus slaves at the same time via the bus matrix. When multiple bus masters access to same bus slave at the same time, bus matrix performs bus arbitration.

Master

Arm Cortex -M3

(Core0)

System-BUS

Bus-Matrix

Arm Cortex -M3

(Core1)

System-BUS

D-BUS

I-BUS

LPDSP

D-BUS

DMIO

DMA

DMB

DMAC0USB

DMAC0

DMA

2.0

DMAC1

DMAC

Slave

System

ROM

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

BASIC

EXT1

EXT3

EXT4

APB

Figure 2. Bus−matrix of LC823455

Note about bus arbitration:

• PM, DMA and DMB access from LPDSP are top priority

and always preferred.

• Access from master except LPDSP is usually scheduled

in round−robin arbitration.

May, 2020 − Rev. 2

1 Publication Order Number:

AND9954/D

Mutex

Mutual exclusion (Mutex) is used to enable exclusive access control to critical bus slaves. Using Mutex, it is possible to maintain the consistency of data. LC823455 has 16 mutex registers.

Atomic Instruction

Cortex−M3 supports bit−band instruction. This instruction performs an atomic read−modify−write operation with exclusive access to memory. Using this instruction, it is possible to maintain the consistency of data.

LPDSP doesn’t support atomic instruction.

Unique id

Cortex−M3 processors (both core0 and core1) have unique CPUID in address 0xE00F_E000 respectively. Since this address is accessed through the Private Peripheral Bus (PPB), each core can access a unique register.

CPUID for Cortex−M3 core0 indicates 0 (“0” is allocated in 0xE00F_E000 for Cortex−M3 core0).

CPUID for Cortex−M3 core1 indicates 1 (“1” is allocated in 0xE00F_E000 for Cortex−M3 core1).

When unique program codes for each core are included in one as a common program code, each core recognize its CPUID on boot, and then executes its respective unique program code.

Interrupts between Cores

LC823455 has 12 interrupts be generated between the cores as shown in Figure 3. Interrupts to Cortex−M3 (core0 and core1) are connected via the NVIC. Interrupts to LPDSP are connected via the SELECTOR.

INTISR0_0, INTISR0_1, INTISR0_2 and INTISR0_3 are used to generate interrupts from Cortex−M3 core0. When Cortex−M3 core0 sets a value of “1” on INTISR0_0, an interrupt is generated from Cortex−M3 core0 to Cortex−M3 core0, core1 and LPDSP. NTISR0_1, INTISR0_2, and INTISR0_3 operate in the same way as INTISR0_0.

INTISR1_0, INTISR1_1, INTISR1_2 and INTISR1_3 are used to generate interrupts from Cortex−M3 core1. When Cortex−M3 core1 sets a value of “1” on INTISR1_0, an interrupt is generated from Cortex−M3 core1 to Cortex−M3 core0, core1 and LPDSP. NTISR1_1, INTISR1_2 and INTISR1_3 operate in the same way as INTISR1_0.

INTISR2_0, INTISR2_1, INTISR2_2 and INTISR2_3 are used to generate interrupts from LPDSP. When LPDSP sets a value of “1” on INTISR2_0, an interrupt is generated from LPDSP to Cortex−M3 core0, core1 and LPDSP. NTISR2_1, INTISR2_2 and INTISR2_3 operate in the same way as INTISR2_0.

External interrupts refer to interrupts from the GPIOs. And Functional interrupts refer to interrupts from function blocks. External interrupts are provided via the FILTER to remove a noise.

External

Functional

Interrupt

Invalid(Bit31−24)

Invalid(Bit23−20)

Invalid(Bit15−12)

Invalid(Bit7−4)

These12bits registers are cleared by registers below. Register name: IPICLR( Address:0x4000_30004)

BUS−MATRIX

INTISR2

(Bit19)

(Bit18)

INTISR1

(Bit11)

(Bit10)

INTISR0

(Bit3)

Arm

Cortex−M3

(Core0)

Arm

Cortex−M3

(Core1)

LPDSP

INTISR2

(Bit17)

INTISR1

(Bit9)

INTISR0

(Bit2)

(Bit1)

INTCNT

FILTER

etc

INTISR2

(Bit16)

INTISR1

(Bit8)

INTISR0

(Bit0)

NVIC0

NVIC1

SELECTOR

Figure 3. Interrupt of LC823455

Event Communication between Cortex−M3 Core0 and Cortex−M3 Core1

Figure 4 shows how events are communicated between Cortex−M3 core0 and Cortex−M3 core1. The TXEV output of Cortex−M3 Core0 is connected to the RXEV input of Cortex−M3 Core1. The TXEV output of Core1 is connected to the RXEV input of Core0.

Both cores can synchronize their tasks by entering into sleep state via the WFE instruction, and by issuing an event to exit sleep state via the SEV command.

The behavior of the WFE instruction is affected by an event latch in the core. If the event latch is not set, the core will enter into sleep state by the WFE instruction. If the event latch is set, the latch is cleared and execution of the WFE instruction does not cause the core to enter sleep state, rather, it continues normal operation. Please refer to Arm documentation on the Cortex−M3 WFE command for more information about the event latch.

RXEV

Arm Cortex−M3

(Core 0)

TXEV

RXEV

Arm Cortex−M3

(Core 1)

TXEV

Interrupt from Peripherals

External interrupts and Functional interrupts are provided to Cortex−M3 (core0 and core1) and LPDSP as shown in Figure 3.

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Figure 4. Cortex−M3 Multi−Core of Event

Communication

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