ON Semiconductor ADT7466 Technical data

Cool® Remote Thermal

FEATURES

Monitors two analog voltages or thermistor temperature

inputs

One on-chip and up to two remote temperature sensors with

series resistance cancellation

Controls and monitors the speed of up to two fans Automatic fan speed control mode controls system

cooling based on measured temperature

Enhanced acoustic mode dramatically reduces user

perception of changing fan speeds

Thermal protection feature via

performance impact of Intel® Pentium® 4 processor thermal control circuit via

PROCHOT 3-wire fan speed measurement Limit comparison of all monitored values SMBus 1.1 serial interface

APPLICATIONS

Low acoustic noise notebook PCs

output monitors

THERM

input

FUNCTIONAL BLOCK DIAGRAM

Controller and Voltage Monitor

ADT7466

GENERAL DESCRIPTION

The ADT7466 dBCool controller is a complete thermal monitor and dual fan controller for noise-sensitive applications requiring active system cooling. It can monitor two analog voltages or the temperature of two thermistors, plus its own supply voltage. It can monitor the temperature of up to two remote sensor diodes, plus its own internal temperature. It can measure and control the speed of up to two fans so that they operate at the lowest possible speed for minimum acoustic noise. The automatic fan speed control loop optimizes fan speed for a given temperature. The effectiveness of the system’s thermal solution can be monitored using the

to time and monitor the

PROCHOT

output of the processor.

SCL SDA ALERT

PROCHOT

input

DRIVE1

DRIVE2

TACH1 TACH2

FANLOCK

FAN1_ON/

PROCHOT/

THERM

D1+ D1–

AIN1/TH1/D2– AIN2/TH2/D2+

CANCELLATION

TEMPERATURE

8-BIT

DAC

8-BIT

DAC

FAN1

ENABLE

SERIES

RESISTANCE

SERIES

RESISTANCE

BAND GAP

SENSOR

V_FAN_MIN

V_FAN_ON

CONTROL

FAN

SPEED

MONITOR

PROCHOT

INPUT

SIGNAL

CONDITIONING

AND

ANALOG

MULTIPLEXER

Figure 1.

Protected by U.S. Patent Numbers 6,188,189; 6,169,442; 6,097,239; 5,982,221; 5,867,012.

ACOUSTIC

ENHANCEMENT

CONTROL

AUTOMATIC

FAN SPEED

CONTROL

10-BIT

ADC

BAND GAP

REFERENCE

GND REFOUT

SERIAL BUS

INTERFACE

ADDRESS

POINTER

CONFIGURATION

REGISTERS

THERM

INTERRUPT

MASKING

INTERRUPT

STATUS

REGISTERS

LIMIT

COMPARATORS

VALUE AND

LIMIT

REGISTERS

ADT7466

04711-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

ADT7466

TABLE OF CONTENTS

Specifications..................................................................................... 3

Series Resistance Cancellation.................................................. 17

Serial Bus Timing .........................................................................5

Absolute Maximum Ratings............................................................ 6

Thermal Characteristics .............................................................. 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Functional Description .................................................................. 11

Measurement Inputs ..................................................................11

Sequential Measurement ........................................................... 11

Fan Speed Measurement and Control..................................... 11

Internal Registers of the ADT7466 .......................................... 11

Theory of Operation ...................................................................... 12

Serial Bus Interface..................................................................... 12

Write and Read Operations....................................................... 14

Alert Response Address (ARA)................................................ 15

Temperature Measurement Method........................................ 17

Using Discrete Transistors ........................................................ 17

Temperature Measurement Using Thermistors..................... 19

Reading Temperature from the ADT7466.............................. 20

Additional ADC Functions....................................................... 21

Limit Values ................................................................................ 21

Alert Interrupt Behavior............................................................ 23

Configuring the ADT7466

Fan Drive ..................................................................................... 26

PWM or Switch Mode Fan Drive............................................. 26

Fan Speed Measurement ........................................................... 26

Fan Start-Up Timeout................................................................ 28

Automatic Fan Speed Control .................................................. 29

Starting the Fan .......................................................................... 30

XOR Test Mode............................................................................... 31

THERM

Pin as an Output......... 25

SMBus Timeout .......................................................................... 15

Voltage Measurement ................................................................ 15

Reference Voltage Output.......................................................... 16

Configuration of Pin 11 and Pin 12 ......................................... 16

Temperature Measurement....................................................... 17

REVISION HISTORY

6/05—Revision 0: Initial Version

Application Circuit......................................................................... 32

ADT7466 Register Map................................................................. 33

Outline Dimensions ....................................................................... 47

Ordering Guide .......................................................................... 47

Rev. 0 | Page 2 of 48

ADT7466

SPECIFICATIONS

TA = T

MIN

to T

, VCC = V

MAX

MIN

to V

, unless otherwise noted.

MAX

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY

Supply Voltage 3.0 3.3 5.5 V Supply Current, ICC 1.4 3 mA Interface inactive, ADC active 30 70 µA Standby mode, digital inputs low

TEMPERATURE-TO-DIGITAL CONVERTER

Local Sensor Accuracy ±1 °C 20°C ≤ TA ≤ 60°C; VCC = 3.3 V ±3 °C −40°C ≤ TA ≤ +125°C; VCC = 3.3 V Resolution 0.25 °C Remote Diode Sensor Accuracy ±1 °C 20°C ≤ TA ≤ 60°C; −40°C ≤ TD ≤ +125°C; VCC = 3.3 V ±3 °C −40°C ≤TA ≤ +105°C; −40°C ≤ TD ≤ +125°C; VCC = 3.3 V ±5 °C −40°C ≤ TA ≤ +125°C; −40°C ≤ TD ≤ +125°C Resolution 0.25 °C Remote Sensor Source Current 192 µA High level 72 µA Mid level 12 µA Low level Series Resistance Cancellation 0 2 kΩ

THERMISTOR-TO-DIGITAL CONVERTER

Temperature Range 30 100 °C

Resolution 0.25 °C Accuracy ±2 °C

ANALOG-TO-DIGITAL CONVERTER

Input Voltage Range 0 V Total Unadjusted Error (TUE) ±1 ±2.5 % Differential Nonlinearity (DNL) ±1 LSB Power Supply Sensitivity ±1 %/V Conversion Time (AIN Input) 8.30 8.65 ms Averaging enabled Conversion Time (Local

8.63 8.99 ms Averaging enabled

Temperature) Conversion Time (Remote

35.22 36.69 ms Averaging enabled

Temperature) Conversion Time (VCC) 7.93 8.26 ms Averaging enabled Total Monitoring Cycle Time 68.38 71.24 ms

Total Monitoring Cycle Time 87 90.63 ms

FAN RPM-TO-DIGITAL CONVERTER

Accuracy ±4 % Full-Scale Count 65,535 Nominal Input RPM 109 RPM Fan count = 0xBFFF 329 RPM Fan count = 0x3FFF 5000 RPM Fan count = 0x0438 10000 RPM Fan count = 0x021C Internal Clock Frequency 78.64 81.92 85.12 kHz

V V

REF

Maximum resistance in series with thermal diode that can be cancelled out

Range over which specified accuracy is achieved. Wider range can be used with less accuracy.

Using specified thermistor and application circuit over specified temperature range

= 2.25V

REF

Averaging enabled, Pin 11 and Pin 12 configured for AIN/TH monitoring (see Table 15)

Averaging enabled, Pin 11 and Pin 12 configured for REM2 monitoring (see Table 15)

Rev. 0 | Page 3 of 48

ADT7466

Parameter Min Typ Max Unit Test Conditions/Comments

DRIVE OUTPUTS (DRIVE1, DRIVE2)

Output Voltage Range 0–2.2 V Digital input = 0x00 to 0xFF

Output Source Current 2 mA

Output Sink Current 0.5 mA

DAC Resolution 8 Bits

Monotonicity 8 Bits

Differential Nonlinearity ±1 LSB

Integral Nonlinearity ±1 LSB

Total Unadjusted Error ±5 % IL = 2 mA REFERENCE VOLTAGE OUTPUT

(REFOUT)

Output Voltage 2.226 2.25 2.288 V

Output Source Current 10 mA

Output Sink Current 0.6 mA OPEN-DRAIN SERIAL DATA BUS

OUTPUT (SDA)

Output Low Voltage (VOL) 0.4 V I

High Level Output Current (IOH) 0.1 1 µA V DIGITAL INPUTS (SCL, SDA, TACH

INPUTS,

PROCHOT) Input High Voltage (VIH) 2.0 V Input Low Voltage (VIL) 0.8 V Hysteresis 0.5 V

DIGITAL INPUT CURRENT (TACH INPUTS,

PROCHOT) Input High Current (IIH) −1 µA VIN = VCC

Input Low Current (IIL) 1 µA VIN = 0 Input Capacitance (IN) 20 pF

OPEN-DRAIN DIGITAL OUTPUTS

ALERT, FANLOCK, FAN1_ON/THERM)

(

Output Low Voltage (VOL) 0.4 V I High Level Output Current (IOH)

SERIAL BUS TIMING

Clock Frequency (f

) 400 kHz See Figure 2

SCLK

Glitch Immunity (tSW) 50 ns See Figure 2 Bus Free Time (t Start Setup Time (t Start Hold Time (t SCL Low Time (t SCL High Time (t

) 1.3 µs See Figure 2

BUF

) 0.6 µs See Figure 2

SU;STA

) 0.6 µs See Figure 2

HD;STA

) 1.3 µs See Figure 2

LOW

) 0.6 µs See Figure 2

HIGH

SCL, SDA Rise Time (tr) 1000 ns See Figure 2 SCL, SDA Fall Time (tf ) 300 ns See Figure 2 Data Setup Time (t Detect Clock Low Timeout (t

All voltages are measured with respect to GND, unless otherwise specified. Typical values are at T = 25°C and represent the most likely parametric norm. Logic inputs

accept input high voltages up to 5 V even when the device is operating at supply voltages below 5 V. Timing specifications are tested at logic levels of V falling edge and at V

Guaranteed by design, not production tested.

) 100 ns See Figure 2

SU;DAT

TIMEOUT

= 2.0 V for a rising edge.

= −4.0 mA, VCC = 3.3 V

OUT

= VCC

OUT

= −4.0 mA, VCC = 3.3 V

OUT

0.1 1 µA V

OUT

) 25 64 Ms Can be optionally disabled

= 0.8 V for a

Rev. 0 | Page 4 of 48

ADT7466

SERIAL BUS TIMING

HIGH

SU;STA

HD;STA

SU;STO

04711-003

SCL

SDA

BUF

PS S P

LOW

HD;STA

HD;DAT

SU;DAT

Figure 2. Diagram for Serial Bus Timing

Rev. 0 | Page 5 of 48

ADT7466

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Positive Supply Voltage (VCC) 6.5 V Voltage on Any Other Pin −0.3 V to 6.5 V Input Current at Any Pin ±5 mA Package Input Current ±20 mA Maximum Junction Temperature (TJ max) 150°C Storage Temperature Range −65°C to +150°C Lead Temperature, Soldering:

IR Peak Reflow Temperature 220°C Lead Temperature (10 sec) 300°C

ESD Rating 2000 V

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

16-Lead QSOP Package:

= 105°C/W

= 39°C/W

Rev. 0 | Page 6 of 48

ADT7466

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DRIVE1

TACH1

2 3

DRIVE2

TACH2

GND

FAN1_ON/PROCHOT/THERM

FANLOCK

ADT7466

TOP VIEW

(Not to Scale)

6 7 8

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Type Description

1 DRIVE1

Analog

Output of 8-Bit DAC Controlling Fan 1 Speed.

Output

2 TACH1

Digital

Fan Tachometer Input to Measure Speed of Fan 1.

Input

3 DRIVE2

Analog

Output of 8-Bit DAC Controlling Fan 2 Speed.

Output

4 TACH2

Digital

Fan Tachometer Input to Measure Speed of Fan 2.

Input 5 GND Ground Ground Pin for Analog and Digital Circuitry. 6 VCC

Power

3.3 V Power Supply. VCC is also monitored through this pin.

supply 7

FAN1_ON/ THERM

PROCHOT/

Digital I/O

If configured as FAN1_ON, this pin is the open-drain control signal output for the dc-dc converter. Active (high) when DRIVE1 > V_FAN_MIN.

If configured as

PROCHOT, the input can be connected to the PROCHOT

SCL

SDA

15 14

ALERT REFOUT

AIN2/TH2/D2+

12 11

AIN1/TH1/D2– D1+

D1–

04711-002

Rev. 0 | Page 7 of 48

ADT7466

TYPICAL PERFORMANCE CHARACTERISTICS

D+ TO GND

–10

–20

D+ TO V

–30

–40

TEMPERATURE ERROR (°C)

–50

–60

0 10080604020

LEAKAGE RESISTANCE (MΩ)

Figure 4. Temperature Error vs. PCB Track Resistance

TEMPERATURE ERROR (°C)

–5

–10

0645321

100mV

250mV

NOISE FREQUENCY (MHz)

Figure 5. Remote Temperature Error vs. Power Supply Noise Frequency

35 30 25 20 15 10

250mV

5 0

–5

100mV

TEMPERATURE ERROR (°C)

–10 –15 –20

0645321

NOISE FREQUENCY (MHz)

Figure 6. Local Temperature Error vs. Power Supply Noise Frequency

04711-004

04711-005

04711-006

–10

–20

–30

–40

–50

TEMPERATURE ERROR (°C)

–60

–70

DEVICE 1 DEVICE 2

DEVICE 3

022015105

CAPACITANCE (nF)

04711-007

Figure 7. Temperature Error vs. Capacitance Between D+ and D−

TEMPERATURE ERROR (°C)

–5

0645321

NOISE FREQUENCY (MHz)

100mV

60mV

40mV

04711-008

Figure 8. Remote Temperature Error vs. Common-Mode Noise Frequency

TEMPERATURE ERROR (°C)

–10

0645321

100mV

NOISE FREQUENCY (MHz)

60mV

40mV

04711-009

Figure 9. Remote Temperature Error vs. Differential Mode Noise Frequency

Rev. 0 | Page 8 of 48

ADT7466

(µA)

DEVICE 1

DEVICE 2

DEVICE 3

140

EXTERNAL

120

100

INTERNAL

3.0 5.45.25.04.84.64.44.24.03.83.63.43.2 VDD (V)

Figure 10. Standby Supply Current vs. Supply Voltage

(µA)

SHUTDOWN I

0 50 100 150 200 250 300 350 400

DEVICE 2

SCL FREQUENCY (kHz)

DEVICE 1

DEVICE 3

Figure 11. Standby Current vs. Clock Frequency

120

04711-010

04711-011

MEASURED TEMPERATURE (°C)

1.00

0.99

0.98

0.97

0.96

0.95

(mA)

0.94

0.93

0.92

0.91

0.90

0.89

065040302010

TIME (s)

Figure 13. Response to Thermal Shock

DEVICE 3

DEVICE 1

DEVICE 2

3.23.0 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 VDD (V)

Figure 14. Supply Current vs. Supply Voltage

04711-012

04711-013

100

PENTIUM 4 READING (°C)

–20

–40

–40 –20 0 20 40 60 80 100 120

ACTUAL TEMPERATURE (°C)

04711-014

Figure 12. Pentium 4 Temperature Measurement vs. ADT7466 Reading

Rev. 0 | Page 9 of 48

–1

–2

–3

TEMPERATURE ERROR

–4

–5

–6

–40 0 20 40 60 85 105 125

TEMPERATURE (°C)

Figure 15. Local Temperature Error

HIGH SPEC

MEAN

LOW SPEC

04711-015

ADT7466

–1

–2

–3

TEMPERATURE ERROR

–4

–5

–40 0 20 40 60 85 105 125

TEMPERATURE (°C)

HIGH SPEC

MEAN

LOW SPEC

04711-016

Figure 16. Remote Temperature Error

Rev. 0 | Page 10 of 48

ADT7466

FUNCTIONAL DESCRIPTION

The ADT7466 is a complete thermal monitor and dual fan controller for any system requiring monitoring and cooling. The device communicates with the system via a serial system management bus (SMBus). The serial data line (SDA, Pin 15) is used for reading and writing addresses and data. The input line, (SCL, Pin 16) is the serial clock. All control and programming functions of the ADT7466 are performed over the serial bus. In addition, an

output is provided to indicate out-of-limit

ALERT

conditions.

MEASUREMENT INPUTS

The device has three measurement inputs, two for voltage and one for temperature. It can also measure its own supply voltage and can measure ambient temperature with its on-chip temperature sensor.

Pin 11 and Pin 12 are analog inputs with an input range of 0 V to 2.25 V. They can easily be scaled for other input ranges by using external attenuators. These pins can also be configured for temperature monitoring by using thermistors or a second remote diode temperature measurement.

The ADT7466 can simultaneously monitor the local temperature, the remote temperature by using a discrete transistor, and two thermistor temperatures.

Remote temperature sensing is provided by the D+ and D− inputs, to which diode connected, remote temperature sensing transistors such as a 2N3904 or CPU thermal diode can be connected.

Temperature sensing using thermistors is carried out by placing the thermistor in series with a resistor. The excitation voltage is provided by the REFOUT pin.

Table 4. Internal Register Summary

Configuration These registers provide control and configuration of the ADT7466 including alternate pinout functionality. Address Pointer

Status

Interrupt Mask Value and Limit

Offset

PROCHOT Status This register allows the ADT7466 to monitor and time any PROCHOT events gauging system performance. T

These registers program the starting temperature for each fan under automatic fan speed control.

MIN

RANGE

Enhance Acoustics This register sets the step size for fan drive changes in AFC mode to minimize acoustic noise.

This register contains the address that selects one of the other internal registers. When writing to the ADT7466, the first byte of data is always a register address, which is written to the address pointer register.

These registers provide status of each limit comparison and are used to signal out-of-limit conditions on the temperature, voltage, or fan speed channels. Whenever a status bit is set, the

These registers allow interrupt sources to be masked so that they do not affect the The results of analog voltage inputs, temperature, and fan speed measurements are stored in these registers, along

with their limit values. These registers allow each temperature channel reading to be offset by a twos complement value written to these

registers.

These registers program the temperature-to-fan speed control slope in automatic fan speed control mode for each fan drive output.

The device also accepts input from an on-chip band gap temperature sensor that monitors system ambient temperature.

Power is supplied to the chip via Pin 6. The system also monitors V

through this pin. It is normally connected to a

3.3 V supply. It can, however, be connected to a 5 V supply and monitored without going over range.

SEQUENTIAL MEASUREMENT

When the ADT7466 monitoring sequence is started, it sequentially cycles through the measurement of analog inputs and the temperature sensors. Measured values from these inputs are stored in value registers, which can be read out over the serial bus, or can be compared with programmed limits stored in the limit registers. The results of out of limit comparisons are stored in the status registers, which can be read over the serial bus to flag out-of-limit conditions.

FAN SPEED MEASUREMENT AND CONTROL

The ADT7466 has two tachometer inputs for measuring the speed of 3-wire fans, and it has two 8-bit DACs to control the speed of two fans. The temperature measurement and fan speed control can be linked in an automatic control loop, which can operate without CPU intervention to maintain system operating temperature within acceptable limits. The enhanced acoustics feature ensures that fans operate at the minimum possible speed consistent with temperature control, and change speed gradually. This reduces the user’s perception of changing fan speed.

INTERNAL REGISTERS OF THE ADT7466

Table 4 provides brief descriptions of the ADT7466’s principal internal registers. More detailed information on the function of each register is given in Table 30 to Table 72.

ALERT output (Pin 14) goes low.

ALERT output.

Rev. 0 | Page 11 of 48

ADT7466

THEORY OF OPERATION

SERIAL BUS INTERFACE

The serial system management bus (SMBus) is used to control the ADT7466. The ADT7466 is connected to this bus as a slave device under the control of a master controller.

The ADT7466 has an SMBus timeout feature. When this is enabled, the SMBus times out after typically 25 ms of no activity. However, this feature is enabled by default. Bit 5 of Configuration Register 1 (0x00) should be set to 1 to disable this feature.

The ADT7466 supports optional packet error checking (PEC). It is triggered by supplying the extra clock pulses for the PEC byte. The PEC byte is calculated using CRC-8. The frame check sequence (FCS) conforms to CRC-8 by the polynomial

()

Consult the SMBus Specifications Rev. 1.1 for more information (www.smbus.org).

The ADT7466 has a 7-bit serial bus address, which is fixed at

1001100.

The serial bus protocol operates as follows:

The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates that an address/data stream follows. All slave peripherals connected to the serial bus respond to the start condition, and shift in the next 8 bits, consisting of a 7-bit address (MSB first) and a R/

bit, which determines the direction of the data transfer, that is, whether data is written to or read from the slave device.

The address of the ADT7466 is set at 1001100. Since the address must always be followed by a write bit (0) or a read bit (1), and data is generally handled in 8-bit bytes, it may be more convenient to think that the ADT7466 has an 8-bit write address of 10011000 (0x98) and an 8-bit read address of 10011001 (0x99). The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the 9th clock pulse, known as the acknowledge bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/

Data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or

bit is 0, the master writes to the slave device. If the

bit is 1, the master reads from the slave device.

1128 +++= xxxxC

write operation is limited only by what the master and slave devices can handle.

When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition.

Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and subsequently cannot be changed without starting a new operation.

ADT7466 write operations contain either one or two bytes, and read operations contain one byte, and perform the following functions.

To write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed, and data can be written to that register or read from it. The first byte of a write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. This is shown in Figure 17. The device address is sent over the bus followed by

set to 0. This is followed by two data bytes. The first data

byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register.

When reading data from a register, there are two possibilities.

If the ADT7466 address pointer register value is unknown or not the desired value, it is necessary to first set it to the correct value before data can be read from the desired data register. This is done by performing a write to the ADT7466 as before, but only the data byte containing the register address is sent since data is not to be written to the register. This is shown in Figure 18.

A read operation is then performed consisting of the serial bus address, R/

the data register. This is shown in Figure 19.

If the address pointer register is known to already be at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, so the procedure in Figure 18 can be omitted.

bit set to 1, followed by the data byte read from

Rev. 0 | Page 12 of 48

ADT7466

SCL

SDA

START BY

MASTER

0 0 1 1 0 0 R/W D7 D6 D5 D4 D3 D2 D1 D0

ACK. BY

FRAME 1

SERIAL BUS ADDRESS BYTE

SCL (CONTINUED)

ADT7466

ADDRESS POINTER REGISTER BYTE

FRAME 2

ACK. BY ADT7466

SDA (CONTINUED)

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 3 DATA BYTE

ACK. BY ADT7466

STOP BY MASTER

04711-017

Figure 17. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

191 9

SCL

START BY

MASTER

1 0 0 1 1 0 0 R/W D7 D6 D5 D4 D3 D2 D1 D0

ACK. BY

FRAME 1

SERIAL BUS ADDRESS BYTE

ADT7466

ADDRESS POINTER REGISTER BYTE

FRAME 2

ACK. BY ADT7466

STOP BY MASTER

04711-018

Figure 18. Writing to the Address Pointer Register Only

191 9

SCL

START BY

MASTER

1 0 0 1 1 0 0 R/W D7 D6 D5 D4 D3 D2 D1 D0

ACK. BY

FRAME 1

SERIAL BUS ADDRESS BYTE

ADT7466

ADDRESS POINTER REGISTER BYTE

FRAME 2

Figure 19. Reading Data from a Previously Selectea2ect

NO ACK. BY

MASTER

STOP BY MASTER

04711-019

Rev. 0 | Page 13 of 48

ADT7466

WRITE AND READ OPERATIONS

The SMBus specification defines several protocols for different types of write and read operations. The protocols used in the ADT7466 are discussed in the following sections. The following abbreviations are used in the diagrams:

S—Start P—Stop R—Read W—Wri te A—Acknowl edge

—No Acknowledge

Write Operations

The ADT7466 uses the send byte and write byte protocols.

Send Byte

In this operation, the master device sends a single command byte to a slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends a register address.

5. The slave asserts ACK on SDA.

6. The master asserts a stop condition on SDA and the

transaction ends.

For the ADT7466, the send byte protocol is used to write a register address to RAM for a subsequent single-byte read from the same address. This is shown in Figure 20.

SLAVE

ADDRESSue

04711-020

Rev. 0 | Page 14 of 48

ADT7466

ALERT RESPONSE ADDRESS (ARA)

ARA is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. The

output, or it can be used as an

be connected to a common master. If a device’s

ALERT

is pulled low.

output can be used as an interrupt

ALERT

. One or more outputs can

ALERT

line connected to the

ALERT

line goes low, the following occurs:

2. The master initiates a read operation and sends the alert

response address (ARA = 0001 100). This is a general call address, which must not be used as a specific device address.

3. The device whose

output is low responds to the

ALERT

alert response address, and the master reads its device address. The address of the device is now known, and it can be interrogated in the usual way.

4. If more than one device’s

output is low, the one

ALERT

with the lowest device address has priority, in accordance with normal SMBus arbitration.

5. Once the ADT7466 responds to the alert response address,

the master must read the status registers, the

ALERT

cleared only if the error condition no longer exists.

SMBus TIMEOUT

The ADT7466 includes an SMBus timeout feature. If there is no SMBus activity for 25 ms, the ADT7466 assumes that the bus is locked, and it releases the bus. This prevents the device from locking or holding the SMBus expecting data. Some SMBus controllers cannot handle the SMBus timeout feature, so they are disabled.

Table 5. Configuration Register 1—Register 0x00

Bit Address and Value Description

<5> TODIS = 0 SMBus timeout enabled (default) <5> TODIS = 1 SMBus timeout disabled

VOLTAGE MEASUREMENT

The ADT7466 has two external voltage measurement channels. Pin 11 and Pin 12 are analog inputs with a range of 0 V to

2.25 V. It can also measure its own supply voltage, V supply voltage measurement is carried out through the V (Pin 6). Setting Bit 6 of Configuration Register 1 (0x00) allows a 5 V supply to power the ADT7466 and be measured without overranging the V

measurement channel.

A/D Converter

All analog inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter. This has a resolution of 10 bits. The basic input range is 0 V to 2.25 V, but the V input has built in attenuators to allow measurement of 3.3 V or 5 V. To allow for the tolerance of the supply voltage, the ADC

. The VCC

produces an output of 3/4 full scale (decimal 768 or 0x300) for the nominal supply voltage, and so has adequate headroom to cope with overvoltages.

Table 9 shows the input ranges of the analog inputs and the output codes of the ADC.

Table 6. Voltage Measurement Registers

0x0A AIN1 reading 0x00 0x0B AIN2 reading 0x00 0x0C VCC reading 0x00

Associated with each voltage measurement channel are high and low limit registers. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate

ALERT

interrupts.

Table 7. Voltage Measurement Limit Registers

0x14 AIN1 low limit 0x00 0x15 AIN1 high limit 0xFF 0x16 AIN2 low limit 0x00 0x17 AIN2 high limit 0xFF 0x18 VCC low limit 0x00 0x19 VCC high limit 0xFF

When the ADC is running, it samples and converts a voltage input in 1 ms, and averages 16 conversions to reduce noise. Therefore a measurement on each input takes nominally 16 ms.

Turn Off Averaging

For each voltage measurement read from a value register, 16 readings have actually been made internally and the results averaged, before being placed into the value register. There can be an instance where faster conversions are required. Setting Bit 4 of Configuration Register 2 (0x01) turns averaging off. This effectively gives a reading 16 times faster (1 ms), but as a result the reading can be noisier.

Single-Channel ADC Conversions

Setting Bit 3 of Configuration Register 4 (0x03) places the ADT7466 into single-channel ADC conversion mode. In this mode, the ADT7466 can be made to read a single voltage channel only. If the internal ADT7466 clock is used, the selected input is read every 1 ms. The appropriate ADC channel is selected by writing to Bits 2:0 of Configuration Register 4 (0x03).

Table 8. Single-Channel ADC Conversions

Bits 2:0, Reg. 0x03 Channel Selected

000 AIN1 001 AIN2 010 V

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