ON Semiconductor ADM1024 User Manual

ADM1024

System Hardware Monitor with Remote Diode Thermal Sensing

The ADM1024 is a complete system hardware monitor for microprocessor-based systems, providing measurement and limit comparison of various system parameters. Eight measurement inputs are provided; three are dedicated to monitoring 5.0 V and 12 V power supplies and the processor core voltage. The ADM1024 can monitor a fourth power supply voltage by measuring its own V (two pins) is dedicated to a remote temperature-sensing diode. Two more pins can be configured as inputs to monitor a 2.5 V supply and a second processor core voltage, or as a second temperature-sensing input. The remaining two inputs can be programmed as general purpose analog inputs or as digital fan speed measuring inputs. Measured values can be read out via a serial System Management Bus and values for limit comparisons can be programmed in over the same serial bus. The high speed successive approximation ADC allows frequent sampling of all analog channels to ensure a fast interrupt response to any out-of-limit measurement.

The ADM1024’s 2.8 V to 5.5 V supply voltage range, low supply current, and SMBus interface make it ideal for a wide range of applications. These include hardware monitoring and protection applications in personal computers, electronic test equipment, and office electronics.

Features

• Up to Nine Measurement Channels

• Inputs Programmable-to-Measure Analog Voltage,

Fan Speed or External Temperature

• External Temperature Measurement with Remote Diode

(Two Channels)

• On-chip Temperature Sensor

• Five Digital Inputs for VID Bits

• LDCM Support

• System Management Bus (SMBus)

• Chassis Intrusion Detect

• Interrupt and Overtemperature Outputs

• Programmable RESET Input Pin

• Shutdown Mode to Minimize Power Consumption

• Limit Comparison of All Monitored Values

• This is a Pb-Free Device*

Applications

• Network Servers and Personal Computers

• Microprocessor-Based Office Equipment

• Test Equipment and Measuring Instruments

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

. One input

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TSSOP−24

CASE 948H

PIN ASSIGNMENT

AD1024

241 232 223 214 205 196 187 178 169 1510 1411 1312

VID0/IRQ0 VID1/IRQ1 VID2/IRQ2 VID3/IRQ3 VID4/IRQ4 +V

CCP1

+2.5VIN/D2+

/D2−

CCP2

+5.0V

+12V

D1+ D1−

NTEST_OUT/ADD

THERM

SDA

SCL FAN1/AIN1 FAN2/AIN2

GND

INT

NTEST_IN/AOUT

RESET

(Top View)

MARKING DIAGRAM

ADM 1024

ARUZ

Top Marking

#YYWW

ZZZZZZZZZ

CCCCCCCCCCC

Bottom Marking

YY = Year WW = Work Week ZZZZ = Assembly Lot Number CCCC = Country of Origin

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 29 of this data sheet.

January , 2016 − Rev. 5

1 Publication Order Number:

ADM1024/D

VID0/IRQ0

VID1/IRQ1

VID2/IRQ2

VID3/IRQ3

VID4/IRQ4

100k W

PULLUPS

VID0–3 AND

FAN DIVISOR

VID4 AND DEVICE ID REGISTER

ADM1024

SERIAL BUS

INTERFACE

CHANNEL

MODE

NTEST_OUT/ADD SDA

SCL

FAN1/AIN1 FAN2/AIN2

CCP1

+2.5VIN/D2+

+5.0V

+12V

/D2–

CCP2

D1+ D1–

POWER TO CHIP

BAND GAP

TEMPERATURE

SENSOR

FAN SPEED

COUNTER

INPUT

ATTENUATORS

AND

ANALOG

MULTIPLEXER

ADDRESS

POINTER

TEMPERATURE

CONFIGURATION

10−BIT ADC

2.5V

BAND GAP

REFERENCE

GND

VALUE AND

LIMIT

REGISTERS

LIMIT

COMPARATORS

INTERRUPT

STATUS

REGISTERS

INT MASK

REGISTERS

INTERRUPT

MASKING

CONFIGURATION

REGISTERS

ANALOG OUTPUT

8−BIT DAC

CHASSIS

INTRUSION

CLEAR

100k

100k W

THERM

INT

NTEST_IN/AOUT

RESET

Figure 1. Functional Block Diagram

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter Rating Unit

Positive Supply Voltage (VCC) 6.5 V Voltage on 12 VIN Pin 20 V Voltage on AOUT, NTEST_OUT ADD, 2.5 VIN/D2+ −0.3 to (VCC + 0.3) V Voltage on Any Other Input or Output Pin −0.3 to +6.5 V Input Current at Any Pin ±5 mA Package Input Current ±20 mA Maximum Junction Temperature (T Storage Temperature Range −65 to +150 °C Lead Temperature, Soldering

Reflow Temperature

ESD Rating All Pins 2000 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.

) 150 °C

JMAX

260

°C

Table 2. THERMAL CHARACTERISTICS

Package Type

24-Lead Small Outline Package 50 10 °C/W

Unit

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ADM1024

Table 3. PIN ASSIGNMENT

Pin No. Mnemonic Description

1 NTEST_OUT/ADD Digital I/O. Dual function pin. This is a three-state input that controls the two LSBs of the Serial Bus

2 THERM Digital I/O. Dual function pin. This pin functions as an interrupt output for temperature interrupts only, or

3 SDA Digital I/O. Serial bus bidirectional data. Open-drain output. 4 SCL Digital Input. Serial bus clock. 5 FAN1/AIN1 Programmable Analog/Digital Input. 0 V to 2.5 V analog input or digital (0 to VCC) amplitude fan

6 FAN2/AIN2 Programmable Analog/Digital Input. 0 V to 2.5 V analog input or digital (0 to VCC) amplitude fan

7 CI Digital I/O. An active high input from an external latch that captures a Chassis Intrusion event. This line

8 GND System Ground. 9 V

10 INT Digital Output. Interrupt request (open-drain). The output is enabled when Bit 1 of Register 40h is set to 1.

11 NTEST_IN/AOUT Digital Input/Analog Output. An active-high input that enables NAND Test mode board-level connectivity

12 RESET Digital I/O. Master Reset, 5 mA driver (open drain), active low output with a 45 ms minimum pulse width.

13 D1− Analog Input. Connected to cathode of first external temperature-sensing diode. 14 D1+ Analog Input. Connected to anode of first external temperature-sensing diode. 15 +12 V 16 +5.0 V 17 V

/D2– Programmable Analog Input. Monitors second processor core voltage or cathode of second external

CCP2

18 +2.5 VIN/D2+ Programmable Analog Input. Monitors 2.5 V supply or anode of second external temperature-sensing

19 +V

CCP1

20 VID4/IRQ4 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID4 Status

21 VID3/IRQ3 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status

22 VID2/IRQ2 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status

23 VID1/IRQ1 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status

24 VID0/IRQ0 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status

Address. This pin functions as an output when doing a NAND test.

as an interrupt input for fan control. It has an on-chip 100 kW pullup resistor.

tachometer input.

can go high without any clamping action, regardless of the powered state of the ADM1024. The ADM1024 provides an internal open drain on this line, controlled by Bit 6 of Register 40h or Bit 7 of Register 46h, to provide a minimum 20 ms pulse on this line to reset the external Chassis Intrusion Latch.

Power (2.8 V to 5.5 V). Typically powered from 3.3 V power rail. Bypass with the parallel combination of 10 mF (electrolytic or tantalum) and 0.1 mF (ceramic) bypass capacitors.

The default state is disabled. It has an on-chip 100 kW pullup resistor.

testing. Refer to the section on NAND testing. Also functions as a programmable analog output when NAND Test is not selected.

Set using Bit 4 in Register 40h. Also acts as reset input when pulled low (e.g., power-on reset). It has an on-chip 100 kW pullup resistor.

Programmable Analog Input. Monitors 12 V supply. Analog Input. Monitors 5.0 V supply.

temperature-sensing diode.

diode. Analog Input. Monitors first processor core voltage (0 V to 3.6 V).

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ADM1024

Table 4. ELECTRICAL CHARACTERISTICS (T

Parameter

= T

MIN

to T

MAX

, VCC = V

MIN

to V

, unless otherwise noted. (Note 1 and 2))

MAX

Test Conditions/Comments Min Typ Max Unit

POWER SUPPLY

Supply Voltage, V Supply Current, I

Interface Inactive, ADC Active ADC Inactive, DAC Active Shutdown Mode

2.8 3.3 5.5 V

−

1.4

1.0 45

3.5

−

145

TEMPERATURE-TO-DIGITAL CONVERTER

Internal Sensor Accuracy

0°C ≤ TA ≤ 100°C T

= 25°C

−

±3.0 ±2.0

Resolution − ±1.0 − °C External Diode Sensor Accuracy 0°C ≤ TA ≤ 100°C

25°C

−

±3.0

±5.0

− Resolution − ±1.0 − °C Remote Sensor Source Current High level

Low level

4.0

110

6.5

150

9.0

ANALOG-TO-DIGITAL CONVERTER (Including MUX and ATTENUATORS)

Total Unadjusted Error (TUE) (12 V TUE (AIN, V

, 2.5 VIN, 5.0 VIN) − − ±3.0 %

CCP

) (Note 3) − − ±4.0 %

Differential Non-linearity (DNL) − − ±1.0 LSB Power Supply Sensitivity − ±1.0 − %/V Conversion Time

(Note 4) − 754.8 856.8

(Analog Input or Internal Temperature) Conversion Time (External Temperature) (Note 4) − 9.6 − ms Input Resistance (2.5 V, 5.0 V, 12 V, V Input Resistance (A

, A

) − 5.0 −

IN1

IN2

CCP1

, V

) 80 140 200

CCP2

ANALOG OUTPUT

Output Voltage Range

0 − 2.5 V Total Unadjusted Error (TUE) IL = 2 mA − − ±3.0 % Full-Scale Error − ±1.0 ±5.0 % Zero-Scale Error No Load − 2.0 − LSB Differential Non-linearity (DNL) Monotonic by Design − − ±1.0 LSB Integral Non-linearity − ±1.0 − LSB Output Source Current − 2.0 − mA Output Sink Current − 1.0 − mA

FAN RPM-TO-DIGITAL CONVERTER

Accuracy

0°C ≤ TA ≤ 100°C − − ±12 % Full-Scale Count − − 255 FAN1 to FAN2 Nominal Input RPM (Note 5) Divisor = 1, Fan Count = 153

Divisor = 2, Fan Count = 153

Divisor = 3, Fan Count = 153

Divisor = 4, Fan Count = 153

−

8800 4400 2200 1100

−

RPM

−

Internal Clock Frequency 0°C ≤ TA ≤ 100°C 19.8 22.5 25.2 kHz

DIGITAL OUTPUTS (NTEST_OUT)

Output High Voltage, V Output Low Voltage, V

= +3.0 mA, VCC = 2.85 V −3.60 V 2.4 − − V

OUT

= −3.0 mA, VCC = 2.85 V −3.60 V − − 0.4 V

OUT

OPEN-DRAIN DIGITAL OUTPUTS (INT, THERM, RESET) (Note 6)

Output Low Voltage, V

High Level Output Leakage Current, I

= 3.0 mA, VCC = 3.60 V − − 0.4 V

OUT

= V

− 0.1 100

RESET and CI Pulsewidth 20 45 − ms

°C

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ADM1024

Table 4. ELECTRICAL CHARACTERISTICS (T

= T

MIN

to T

MAX

, VCC = V

MIN

to V

, unless otherwise noted. (Note 1 and 2))

MAX

Parameter UnitMaxTypMinTest Conditions/Comments

OPEN-DRAIN SERIAL DATABUS OUTPUT (SDA)

Output Low Voltage, V

High Level Output Leakage Current, I

= −3.0 mA, VCC = 2.85 V −3.60 V − − 0.4 V

OUT

= V

− 0.1 100

SERIAL BUS DIGITAL INPUTS (SCL, SDA)

Input High Voltage, V Input Low Voltage, V

2.2 − − V

− − 0.8 V Hysteresis − 500 − mV Glitch Immunity − 100 − ns

DIGITAL INPUT LOGIC LEVELS (ADD, CI, RESET, VID0−VID4, FAN1, FAN2) (Note 7)

Input High Voltage, V Input Low Voltage, V

VCC = 2.85 V − 5.5 V 2.2 − − V VCC = 2.85 V − 5.5 V − − 0.8 V

NTEST_IN

Input High Current, I

VCC = 2.85 V − 5.5 V 2.2 − −

DIGITAL INPUT CURRENT

Input High Current, I Input Low Current, I Input Capacitance, C

VIN = V

–1.0 − −

VIN = 0 − − 1.0

− 20 − pF

mA mA

SERIAL BUS TIMING (Note 8)

Clock Frequency, f Glitch Immunity, t Bus Free Time, t Start Setup Time, t Start Hold Time, t SCL Low Time, t SCL High Time, t

SCLK

BUF

SU; STA

HD; STA

LOW

HIGH

SCL, SDA Rise Time, t SCL, SDA Fall Time, t Data Setup Time, t Data Hold Time, t

SU; DAT

HD; DAT

See Figure 2 − − 400 kHz See Figure 2 − − 50 ns See Figure 2 1.3 − − See Figure 2 600 − − See Figure 2 600 − − See Figure 2 1.3 − − See Figure 2 0.6 − −

ms ns ns

See Figure 2 − − 300 ns See Figure 2 − − 300

See Figure 2 100 − − ns See Figure 2 − − 900 ns

1. All voltages are measured with respect to GND, unless otherwise specified.

2. Typicals are at T

3. TUE (Total Unadjusted Error) includes Offset, Gain, and Linearity errors of the ADC, multiplexer, and on-chip input attenuators, including

= 25°C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3V.

an external series input protection resistor value between 0 kW and 1 kW.

4. Total monitoring cycle time is nominally m × 755 ms + n × 33244 ms, where m is the number of channels configured as analog inputs, plus 2 for the internal V channels (D1 and D2).

measurement and internal temperature sensor, and n is the number of channels configured as external temperature

5. The total fan count is based on two pulses per revolution of the fan tachometer output.

6. Open−drain digital o utputs m ay ha ve a n external p ullup r esistor connected t o a v oltage lower o r higher t han V

7. All logic inputs except ADD are tolerant of 5.0 V logic levels, even if V

, GND, or left open−circuit.

to V

8. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge.

is less than 5.0 V. ADD is a three-state input that may be connected

(up to 6.5 V absolute maximum).

SCL

SDA

LOW

HD:STA

BUF

HD:DAT

HIGH

SU:DAT

SU:STA

HD:STA

SU:STO

PSPS

Figure 2. Serial Bus Timing Diagram

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ADM1024

TYPICAL PERFORMANCE CHARACTERISTICS

–10

–20

–30

TEMPERATURE ERROR (°C)

–40

–50

–60

1 3.3 10 30

DXP TO VCC (5.0 V)

LEAK RESISTANCE (MΩ)

DXP TO GND

Figure 3. Temperature Error vs. PC Board

Track Resistance

TEMPERATURE ERROR (5C)

–5

50 500 5k 50k

FREQUENCY (Hz)

100mV p−p

25mV p−p

500k 5M

50mV p−p

100

50M

TEMPERATURE ERROR (5C)

–1

50 500 5k 50k

250mV p−p REMOTE

100mV p−p REMOTE

500k 5M

FREQUENCY (Hz)

Figure 4. Temperature Error vs. Power Supply

Noise Frequency

110 100

90 80 70 60 50

READING

40 30 20 10

0 10 20 30 40 50 60 70 80 90 100 110

MEASURED TEMPERATURE

50M

Figure 5. Temperature Error vs. Common-mode

Noise Frequency

TEMPERATURE ERROR (5C)

–5

1 2.2 3.2 4.7

DXP−DXN CAPACITANCE (nF)

Figure 7. Temperature Error vs. Capacitance

Between D+ and D–

Figure 6. Pentium) III Temperature vs. ADM1024

Figure 8. Temperature Error vs. Differential-mode

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TEMPERATURE ERROR (5C)

50 500 5k 50k

Reading

10mV SQ. WAVE

500k 5M 25M100k

FREQUENCY (Hz)

Noise Frequency

50M

ADM1024

TYPICAL PERFORMANCE CHARACTERISTICS

26.5

26.0

25.5

25.0

24.5

24.0

STANDBY CURRENT (mA)

23.5

23.0

22.5 –40 –20 0 20 40 60 80 100 120

VDD = 3.3 V

TEMPERATURE (5C)

Figure 9. Standby Current vs. Temperature

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ADM1024

General Description

The ADM1024 is a c omplete s ystem h ardware monitor for microprocessor-based systems. The device communicates with the system via a serial SMBus. The serial bus controller has a hardwired address line for device selection (Pin 1), a serial data line for reading and writing addresses and data (SDA, Pin 14), and an input line for the serial clock (Pin 3), and an input line for the serial clock (Pin 4). All control and programming functions of the A DM1024 are performed o ver the serial bus.

Measurement Inputs

Programmability of the measurement inputs makes the ADM1024 extremely flexible and versatile. The device has a 10−bit ADC and nine measurement input pins that can be configured in different ways.

Pins 5 and 6 can be programmed as general-purpose analog inputs with a range of 0 V to 2.5 V, or as digital inputs to monitor the speed of fans with digital tachometer outputs. The fan inputs can be programmed to accommodate fans with different speeds and different numbers of pulses per revolution from their tachometer outputs.

Pins 13 and 14 are dedicated temperature inputs and may be connected to the cathode and anode of an external temperature sensing diode.

Pins 15, 16, and 19 are dedicated analog inputs with on-chip attenuators, configured to monitor 12 V, 5.0 V, and the processor core voltage, respectively.

Pins 17 and 18 may be configured as analog inputs with on-chip attenuators to monitor a s econd p rocessor core v oltage and a 2.5 V supply, or they may be configured as a t emperature input and connected to a second temperature-sensing diode.

The ADC also accepts input from an on-chip band gap temperature sensor that monitors system-ambient temperature.

Finally, the ADM1024 monitors the supply from which it is powered, so there is no need for a separate 3.3 V analog input if the chip V

is 3.3 V. The range of this V

measurement can be configured for either a 3.3 V or 5.0 V V

by Bit 3 of the Channel Mode Register.

Sequential Measurement

When the ADM1024 monitoring sequence is started, it cycles sequentially through the measurement of analog inputs and the temperature sensor, while at the same time the fan speed inputs are independently monitored. Measured values from these inputs are stored in Value Registers. These can be read out over the serial bus, or can be compared with programmed limits stored in the Limit Registers. The results of out-of-limit comparisons are stored in the Interrupt Status Registers, and will generate an interrupt on the INT

line

(Pin 10).

Any or all of the Interrupt Status Bits can be masked by appropriate programming of the Interrupt Mask Register.

Processor Voltage ID

Five digital inputs (VID4 to VID0−Pins 20 to 24) read the processor voltage ID code. These inputs can also be reconfigured as interrupt inputs.

The VID pins have internal 100 kW pullup resistors.

Chassis Intrusion

A chassis intrusion input (Pin 7) is provided to detect unauthorized tampering with the equipment.

RESET

A RESET input/output (Pin 12) is provided. Pulling this pin low will reset all ADM1024 internal registers to default values. The ADM1024 can also be programmed to give a low going 45 ms reset pulse at this pin.

Analog Output

The ADM1024 contains an on-chip, 8-bit DAC with an output range of 0 V to 2.5 V (Pin 11). This is typically used to implement a temperature-controlled fan by controlling the speed of a fan dependent upon the temperature measured by the on-chip temperature sensor.

Testing of board level connectivity is simplified by providing a NAND tree test function. The AOUT (Pin 11) also doubles as a NAND test input, while Pin 1 doubles as a NAND tree output.

Internal Registers of the ADM1024

A brief description of the ADM1024’s principal internal registers follows. More detailed information on the function of each register is given in Table 10 to Table 23:

• Configuration Registers: Provide control and

configuration.

• Channel Mode Register: Stores the data for the

operating modes of the input channels.

• Address Pointer Register: This register contains the

address that selects one of the other internal registers. When writing to the ADM1024, the first byte of data is always a register address, which is written to the Address Pointer Register.

• Interrupt (INT) Status Registers: Two registers to

provide status of each interrupt event. These registers are also mirrored at addresses 4Ch and 4Dh.

• Interrupt (INT) Mask Registers: Allow masking of

individual interrupt sources.

• Temperature Configuration Register: The configuration

of the temperature interrupt is controlled by the lower three bits of this register.

• VID/Fan Divisor Register: The status of the VID0 to

VID4 pins of the processor can be written to and read from these registers. Divisor values for fan speed measurement are also stored in this register.

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ADM1024

• Value and Limit Registers: The results of analog

voltage inputs, temperature, and fan speed measurements are stored in these registers, along with their limit values.

• Analog Output Register: The code controlling the

analog output DAC is stored in this register.

• Chassis Intrusion Clear Register: A signal latched on

the chassis intrusion pin can be cleared by writing to this register.

Serial Bus Interface

Control of the ADM1024 is carried out via the serial bus. The ADM1024 is connected to this bus as a slave device, under the control of a master device, e.g., ICH.

The ADM1024 has a 7-bit serial bus address. When the device is powered up, it will do so with a default serial bus address. The 5 MSBs of the address are set to 01011, and the 2 LSBs are determined by the logical states of Pin 1 (NTEST OUT/ADD). This is a three-state input that can be grounded, connected to V addresses.

Table 5. ADD PIN TRUTH TABLE

ADD Pin A1 A0

GND 1 0 No Connect 0 0 V

If ADD is left open-circuit, the default address will be

0101100. ADD is sampled only at powerup, so any changes made while power is on will have no immediate effect.

The facility to make hardwired changes to A1 and A0 allows the user to avoid conflicts with other devices sharing the same serial bus, for example, if more than one ADM1024 is used in a system.

The serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line, SCL, remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W data transfer, i.e., whether data will be written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge Bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W write to the slave device. If the R/W master will read from the slave device.

, or left open-circuit to give three different

0 1

bit, which determines the direction of the

bit is a 0, the master will

bit is a 1, the

2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an Acknowledge Bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition when the clock is high may be interpreted as a STOP signal. The number of data bytes that can be transmitted over the serial bus in a single Read or Write operation is limited only by what the master and slave devices can handle.

3. When all data bytes have been read or written, stop conditions are established. In Write mode, the master will pull the data line high during the tenth clock pulse to assert a STOP condition. In Read mode, the master device will override the Acknowledge Bit by pulling the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the tenth clock pulse, then high during the tenth clock pulse to assert a STOP condition.

Any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation.

In the case of the ADM1024, write operations contain either one or two bytes, and read operations contain one byte and perform the following functions.

To write data to one of the device data registers or read data from it, the Address Pointer Register must be set so that the correct data register is addressed, then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the Address Pointer Register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the Address Pointer Register. This is illustrated in Figure 10 The device address is sent over the bus followed by R/W

set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the Address Pointer Register. The second data byte is the data to be written to the internal data register.

When reading data from a register, there are two

possibilities:

1. If the ADM1024’s Address Pointer Register value is unknown or not the desired value, it is first necessary to set it to the correct value before data can be read from the desired data register. This is done by performing a write to the ADM1024 as before, but only the data byte containing the register address is sent, as data is not to be written to the register. This is shown in Figure 11. A read operation is then performed consisting of

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ADM1024

the serial bus address, R/W bit set to 1, followed by the data byte read from the data register. This is shown in Figure 12.

2. If the Address Pointer Register is known to be already at the desired address, data can be read

1 991

SCL

SDA

START BY

MASTER

1011

FRAME 1

SERIAL BUS ADDRESS BYTE

SCL (CONTINUED)

SDA (CONTINUED)

Figure 10. Writing a Register Address to the Address Pointer Register,

then Writing Data to the Selected Register

R/W

ACK. BY

ADM1024

from the corresponding data register without first writing to the Address Pointer Register, so Figure 11 can be omitted.

D5D6

D4 D3 D2 D1

ADDRESS POINTER REGISTER BYTE

FRAME 2

FRAME 3

DATA BYTE

D1D2D3

ACK. BY

ADM1024

ACK. BY

ADM1024

STOP BY MASTER

SCL

SDA

START BY

MASTER

1 0 1 1 A1 A0

FRAME 1

SERIAL BUS ADDRESS BYTE

Figure 11. Writing to the Address Pointer Register Only

SCL

START BY

MASTER

1SDA

SERIAL BUS ADDRESS BYTE

FRAME 1

Figure 12. Reading Data from a Previously Selected Register

NOTES

1. Although it is possible to read a data byte from a data register without first writing to the Address Pointer Register, if the Address Pointer Register is already at the correct value, it is not possible to write data to a register without writing to the Address Pointer Register because the first data byte of a write is always written to the Address Pointer Register.

R/W

ACK. BY

ADM1024

R/W

ACK. BY

ADM1024

D5D6

ADDRESS POINTER REGISTER BYTE

FRAME 2

D4 D3 D2 D1

FRAME 2

DATA BYTE FROM ADM1024

D1D2D3

ACK. BY

ADM1024

NO ACK.

BY MASTER

STOP BY

MASTER

STOP BY MASTER

2. In Figure 10 to Figure 12, the serial bus address is shown as the default value 01011(A1)(A0), where A1 and A0 are set by the three−state ADD pin.

Measurement Inputs

The ADM1024 has nine external measurement pins t hat can be configured to perform various functions by programming the Channel Mode Register.

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