The ON Semiconductor 74FST3257 is a quad 2:1, high performance
multiplexer/demultiplexer bus switch. The device is CMOS TTL
compatible when operating between 4 and 5.5 Volts. The device
exhibits extremely low R
The device adds no noise or ground bounce to the system.
Features
• R
t 4 W Typical
ON
• Less Than 0.25 ns−Max Delay Through Switch
• Nearly Zero Standby Current
• No Circuit Bounce
• Control Inputs are TTL/CMOS Compatible
• Pin−For−Pin Compatible With QS3257, FST3257, CBT3257
• All Popular Packages: SOIC−16, TSSOP−16, QFN16
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
and adds nearly zero propagation delay.
ON
16
SOIC−16
D SUFFIX
CASE 751B
16
TSSOP−16
DT SUFFIX
CASE 948F
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16
1
1
MARKING
DIAGRAMS
FST3257G
AWLYWW
1
16
FST
3257
ALYW G
G
1
SV
1
1B
2
1
1B
3
2
1A
4
2B
5
1
2B
6
2
2A
7
GND3A
89
16
15
14
13
12
11
10
OE
4B
4B
4A
3B
3B
CC
1B
1
2
1
2
1B
1A
2B
2B
2A
Figure 1. 16−Lead Pinout Diagrams
S
X
L
H
OE
H
L
L
Function
Disconnect
Figure 2. Truth Table
2
1
3
2
4
5
1
6
2
7
A = B
A = B
V
S
CC
1
16
GND
89
GND 3A
1
2
15
14
13
12
11
10
OE
4B
4B
4A
3B
3B
1
QFN16
MN SUFFIX
1
2
1
2
CASE 485AW
A= Assembly Location
WL, L= Wafer Lot
Y= Year
WW, W = Work Week
G or G= Pb−Free Package
(Note: Microdot may be in either location)
3257
ALYWG
G
PIN NAMES
Pin
OE1, OE
B1, B2, B3, B
2
S0, S
1
ABus A
4
Description
Bus Switch Enables
Select Inputs
Bus B
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
†
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2
74FST3257
MAXIMUM RATINGS
SymbolParameterValueUnits
V
CC
V
V
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
T
q
JA
MSLMoisture SensitivityLevel 1
F
V
ESD
I
Latchup
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
DC Supply Voltage−0.5 to +7.0V
DC Input Voltage−0.5 to +7.0V
I
DC Output Voltage−0.5 to +7.0V
O
DC Input Diode Current
V
t GND−50
I
DC Output Diode Current
V
t GND−50
O
DC Output Sink Current128mA
DC Supply Current per Supply Pin±100mA
DC Ground Current per Ground Pin±100mA
Storage Temperature Range−65 to +150
Lead Temperature, 1 mm from Case for 10 Seconds260
L
Junction Temperature Under Bias+150
J
Thermal Resistance
Flammability Rating
R
SOIC
TSSOP
QFN
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
125
170
N/A
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
u2000
u200
N/A
Latchup Performance
Above V
and Below GND at 85_C (Note 4)
CC
±500
mA
mA
_C
_C
_C
_C/W
V
mA
RECOMMENDED OPERATING CONDITIONS
SymbolParameterMinMaxUnits
V
CC
V
V
T
Dt/DV
Supply Voltage
Operating, Data Retention Only
Input Voltage (Note 5)05.5V
I
Output Voltage (HIGH or LOW State)05.5V
O
Operating Free−Air Temperature−40+85
A
4.05.5
Input Transition Rise or Fall RateSwitch Control Input
Switch I/OV
= 5.0 V ± 0.5 V
CC
0
DC
5
5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.
6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower
of the voltages on the two (A or B) pins.
TA = −40_C to +85_C
mA
mA
W
mA
AC ELECTRICAL CHARACTERISTICS
TA = −40_C to +85_C
C
= 50 pF, RU = RD = 500 W
L
VCC = 4.5−5.5 VVCC = 4.0 V
SymbolParameterConditionsMinMaxMinMaxUnits
t
PHL
t
t
PZH
t
t
PHZ
t
PLH
PZL
PLZ
,
Prop Delay Bus to Bus (Note 7)
Prop Delay, Select to Bus A1.04.75.2
,
Output Enable Time, Select to Bus BVI = 7 V for t
Output Enable Time, IOE to Bus A, BVI = OPEN for t
,
Output Disable Time, Select to Bus BVI = 7 V for t
Output Disable Time, IOE to Bus A, BVI = OPEN for t
VI = OPEN
PZL
PLZ
PZH
PHZ
0.250.25
1.05.25.7
1.05.15.6
1.05.25.5
1.05.55.5
ns
ns
ns
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE (Note 8)
Symbol
C
C
C
Control Pin Input CapacitanceVCC = 5.0 V3pF
IN
A Port Input/Output CapacitanceVCC, OE = 5.0 V7pF
I/O
B Port Input/Output CapacitanceVCC, OE = 5.0 V5pF
I/O
8. TA = )25_C, f = 1 MHz, Capacitance is characterized but not tested.
ParameterConditionsTypMaxUnits
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4
74FST3257
AC Loading and Waveforms
V
I
FROM
OUTPUT
UNDER
TEST
CL*
NOTES:
1. Input driven by 50 W source terminated in 50 W.
2. CL includes load and stray capacitance.
*C
= 50 pF
L
Figure 4. AC Test Circuit
t
= 2.5 nS
f
90 %
SWITCH
INPUT
OUTPUT
90 %
10 %10 %
t
PLH
1.5 V1.5 V
500 W
500 W
t
= 2.5 nS
f
3.0 V
1.5 V1.5 V
GND
t
PLH
V
OH
V
OL
ENABLE
INPUT
t
= 2.5 nS
f
OUTPUT
OUTPUT
Figure 5. Propagation Delays
90 %
t
PZL
t
PZH
1.5 V
10 %10 %
1.5 V
1.5 V
90 %
1.5 V
Figure 6. Enable/Disable Delays
t
= 2.5 nS
f
t
PLZ
t
PHZ
3.0 V
GND
V
OL
V
OL
V
OH
V
OH
+ 0.3 V
− 0.3 V
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
1
SCALE 2:1
16X
2X
2X
NOTE 4
PIN ONE
REFERENCE
C0.10
C0.08
L
16X
DETAIL A
C0.15
C0.15
TOP VIEW
DETAIL B
SIDE VIEW
2
1
e
e/2
BOTTOM VIEW
D
D2
8
0.15
10
15
A
B
E
A
(A3)
A1
C A B
K
0.15
E2
QFN16, 2.5x3.5, 0.5P
CASE 485AW−01
ISSUE O
L1
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
DETAIL B
ALTERNATE
CONSTRUCTIONS
SEATING
C
PLANE
C A B
16X
b
0.10 C
A B
0.05
C
NOTE 3
DATE 11 DEC 2008
NOTES:
1. DIMENSIONING AND TOLERANCING PER
L
MOLD CMPDEXPOSED Cu
L
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MINMAX
A
0.801.00
A10.000.05
A3
0.20 REF
b0.200.30
D2.50 BSC
D20.851.15
E3.50 BSC
E2
1.852.15
e0.50 BSC
K0.20---
L0.350.45
L1---0.15
GENERIC MARKING
DIAGRAM*
XXXX
ALYWG
G
XXXX= Specific Device Code
A= Assembly Location
L= Wafer Lot
Y= Year
W= Work Week
G= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
SOLDERING FOOTPRINT*
3.80
2.10
0.50
PITCH
2.80
1.10
1
PACKAGE
16X
0.60
16X
0.30
DIMENSIONS: MILLIMETERS
OUTLINE
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SCALE 1:1
−A−
169
−B−
18
G
K
C
−T−
SEATING
PLANE
D
16 PL
0.25 (0.010)A
M
S
B
T
S
CASE 751B−05
8 PLP
0.25 (0.010)B
M
SOIC−16
ISSUE K
M
R
X 45
DATE 29 DEC 2006
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
S
_
F
J
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
16
1
SCALE 2:1
16X REFK
M
G
0.10 (0.004)
−T−
SEATING
PLANE
L
U0.15 (0.006) T
PIN 1
IDENT.
U0.15 (0.006) T
D
S
2X L/2
S
0.10 (0.004)V
16
1
A
−V−
C
CASE 948F−01
U
T
9
B
−U−
8
TSSOP−16
ISSUE B
S
S
J
N
N
DETAIL E
H
J1
F
DETAIL E
K
K1
SECTION N−N
0.25 (0.010)
M
DATE 19 OCT 2006
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
XXXX = Specific Device Code
A= Assembly Location
L= Wafer Lot
Y= Year
0.65
PITCH
W= Work Week
G or G = Pb−Free Package
*This information is generic. Please refer to
16X
0.36
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
16X
1.26
98ASH70247A
TSSOP−16
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf
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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
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