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UC3845
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ON UC2844DG, UC2844N, UC2845DG, UC2845N, UC3844 Schematic [ru]

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UC3844, UC3845, UC2844, UC2845
High Performance Current Mode Controllers
Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle−by−cycle current limiting, a latch for single pulse metering, and a flip−flop which blanks the output off every other oscillator cycle, allowing output dead times to be programmed for 50% to 70%.
These devices are available in an 8−pin dual−in−line plastic package as well as the 14−pin plastic surface mount (SOIC−14). The SOIC−14 package has separate power and ground pins for the totem pole output stage.
The UCX844 has UVLO thresholds of 16 V (on) and 10 V (off), ideally suited for off−line converters. The UCX845 is tailored for lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off).
Features
• Current Mode Operation to 500 kHz Output Switching Frequency
• Output Deadtime Adjustable from 50% to 70%
• Automatic Feed Forward Compensation
• Latching PWM for Cycle−By−Cycle Current Limiting
• Internally Trimmed Reference with Undervoltage Lockout
• High Current Totem Pole Output
• Input Undervoltage Lockout with Hysteresis
• Low Startup and Operating Current
• Direct Interface with ON Semiconductor SENSEFETt Products
• Pb−Free Packages are Available
V
7(12)
CC
8(14)
R
TCT
4(7)
Voltage
Feedback
2(3)
1(1) Output Comp.
V
ref
R
R
Oscillator
+
−
Error
Amplifier
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
V
Undervoltage
Lockout
GND 5(9)
5.0V
Reference
ref
Flip
Flop
&
Latching
PWM
Figure 1. Simplified Block Diagram
V
CC
Undervoltage
Lockout
V
C
7(11)
Output
6(10)
PWR GND
5(8)
Current Sense
3(5)
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PDIP−8
N SUFFIX
8
1
14
1
8
1
CASE 626
SOIC−14
D SUFFIX
CASE 751A
SOIC−8
D1 SUFFIX
CASE 751A
PIN CONNECTIONS
Compensation
Voltage Feedback
Current Sense
R
T/CT
Compensation
NC
Voltage Feedback
NC
Current Sense
NC
R
T/CT
1
2
3
45
(Top View)
1
2
3
4
5
6
7
(Top View)
8
V
ref
7
V
CC
6
Output
GND
14
V
ref
13
NC
12
V
CC
11
V
C
10
Output
9
GND
Power Ground
8
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 7
1 Publication Order Number:
UC3844/D
UC3844, UC3845, UC2844, UC2845
MAXIMUM RATINGS
Rating Symbol Value Unit
Total Power Supply and Zener Current (ICC + IZ) 30 mA
Output Current, Source or Sink (Note 1) I
O
Output Energy (Capacitive Load per Cycle) W 5.0
Current Sense and Voltage Feedback Inputs V
Error Amp Output Sink Current I
in
O
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package, Case 751A
Maximum Power Dissipation @ T Thermal Resistance Junction−to−Air
N Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA = 25°C Thermal Resistance Junction−to−Air
Operating Junction Temperature T
Operating Ambient Temperature
UC3844, UC3845
= 25°C
A
P
D
R
q
JA
P
D
R
q
JA
J
T
A
UC2844, UC2845
Storage Temperature Range T
stg
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
1. Maximum Package power dissipation limits must be observed.
1.0 A
mJ
− 0.3 to + 5.5 V
10 mA
862 145
1.25 100
mW
°C/W
W
°C/W
+ 150 °C
°C
0 to + 70
− 25 to + 85
− 65 to + 150 °C
ELECTRICAL CHARACTERISTICS (V
= 15 V, (Note 2), RT = 10 k, CT = 3.3 nF, TA = T
CC
low
to T
(Note 3), unless otherwise noted.)
high
UC284X UC384X
Characteristics Symbol Min Typ Max Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) V
Line Regulation (VCC = 12 V to 25 V) Reg
Load Regulation (IO = 1.0 mA to 20 mA) Reg
Temperature Stability T
Total Output Variation over Line, Load, Temperature V
Output Noise Voltage (f = 10 Hz to kHz, TJ = 25°C) V
ref
line
load
S
ref
n
4.95 5.0 5.05 4.9 5.0 5.1 V
− 2.0 20 − 2.0 20 mV
− 3.0 25 − 3.0 25 mV
− 0.2 − − 0.2 − mV/°C
4.9 − 5.1 4.82 − 5.18 V
− 50 − − 50 −
Long Term Stability (TA = 125°C for 1000 Hours) S − 5.0 − − 5.0 − mV
Output Short Circuit Current I
SC
− 30 − 85 − 180 − 30 − 85 − 180 mA
OSCILLATOR SECTION
Frequency
= 25°C
T
J
= T
T
to T
A
low
high
Frequency Change with Voltage (VCC = 12 V to 25 V)
Frequency Change with Temperature
= T
T
to T
A
low
high
Oscillator Voltage Swing (Peak−to−Peak) V
Discharge Current (V
= 2.0 V, TJ = 25°C) I
osc
Df
Df
f
osc
osc/DV
osc/DT
osc
dischg
47 46
52
−
60
57
47 46
52
−
60
57
− 0.2 1.0 − 0.2 1.0 %
− 5.0 − − 5.0 − %
− 1.6 − − 1.6 − V
− 10.8 − − 10.8 − mA
ERROR AMPLIFIER SECTION
Voltage Feedback Input (VO = 2.5 V) V
Input Bias Current (VFB = 2.7 V) I
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) A
FB
IB
VOL
2.45 2.5 2.55 2.42 2.5 2.58 V
− −0.1 −1.0 − −0.1 −2.0
65 90 − 65 90 − dB
2. Adjust VCC above the Startup threshold before setting to 15 V.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. =0°C for UC3844, UC3845 T
T
low
−25°C for UC2844, UC2845 +85°C for UC2844, UC2845
= +70°C for UC3844, UC3845
high
mV
kHz
mA
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UC3844, UC3845, UC2844, UC2845
ELECTRICAL CHARACTERISTICS (V
= 15 V, (Note 4), RT = 10 k, CT = 3.3 nF, TA = T
CC
low
to T
(Note 5), unless otherwise noted.)
high
UC284X UC384X
Characteristics Symbol Min Typ Max Min Ty p Max Unit
ERROR AMPLIFIER SECTION (continued)
Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 − 0.7 1.0 − MHz
Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 − 60 70 − dB
Output Current
Sink (V
O
Source (V
= 1.1 V, VFB = 2.7 V)
= 5.0 V, VFB = 2.3 V)
O
I
Sink
I
Source
2.0
−0.512−1.0
−
−
2.0
−0.512−1.0
−
−
Output Voltage Swing
High State (R Low State (R
= 15 k to ground, VFB = 2.3 V)
L
= 15 k to V
L
, VFB = 2.7 V)
ref
V
OH
V
OL
5.0−6.2
0.8
1.1
−
5.0
6.2
−
0.8
−
1.1
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 6 & 7)
Maximum Current Sense Input Threshold (Note 6) V
Power Supply Rejection Ratio
= 12 V to 25 V (Note 6)
V
CC
PSRR
Input Bias Current I
Propagation Delay (Current Sense Input to Output) t
PLH(IN/OUT)
A
V
th
IB
2.85 3.0 3.15 2.85 3.0 3.15 V/V
0.9 1.0 1.1 0.9 1.0 1.1 V
− 70 − − 70 −
− −2.0 −10 − −2.0 −10
− 150 300 − 150 300 ns
OUTPUT SECTION
Output Voltage
Low State (I
High State (I
Output Voltage with UVLO Activated
= 6.0 V, I
V
CC
Sink
(I
Sink
Sink
(I
Sink
Sink
= 20 mA) = 200 mA) = 20 mA) = 200 mA)
= 1.0 mA
V
OL(UVLO)
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) t
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) t
V
OL
V
OH
r
f
−
12 12
0.1
−
1.6
13.5
13.4
0.4
2.2
−
0.1
−
−
13
−
12
1.6
13.5
13.4
0.4
2.2
−
−
− 0.1 1.1 − 0.1 1.1
− 50 150 − 50 150 ns
− 50 150 − 50 150 ns
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold
UCX844 UCX845
Minimum Operating Voltage After Turn−On
UCX844 UCX845
V
V
CC(min)
th
15
7.8168.4
9.0
7.0107.6
17
9.0
11
8.2
14.5
7.8
8.5
7.0
16
8.4
10
7.6
17.5
9.0
11.5
8.2
PWM SECTION
Duty Cycle
Maximum Minimum
DC DC
max
min
46
48
−
50
−
47
0
48
−
50
−
0
TOTAL DEVICE
Power Supply Current (Note 4)
I
CC
Startup:
= 6.5 V for UCX845A,
(V
CC
14 V for UCX844) Operating
(V
CC
Power Supply Zener Voltage (ICC = 25 mA) V
Z
−
0.5
−
12
1.0 17
−
0.5
−
12
1.0 17
30 36 − 30 36 − V
4. Adjust VCC above the Startup threshold before setting to 15 V.
5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. =0°C for UC3844, UC3845 T
T
low
−25°C for UC2844, UC2845 +85°C for UC2844, UC2845
6. This parameter is measured at the latch trip point with V
7. Comparator gain is defined as: A
DV Output Compensation
V
DV Current Sense Input
= +70°C for UC3844, UC3845
high
= 0 V.
FB
mA
V
dB
mA
V
V
V
V
%
mA
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UC3844, UC3845, UC2844, UC2845
10
0
50
VCC = 15 V T
A
Ω, TIMING RESISTOR (k )
20
10
5.0
T
2.0
R
NOTE: Output switches at one−half the oscillator frequency.
1.0 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M
f
, OSCILLATOR FREQUENCY (Hz)
osc
Figure 2. Timing Resistor versus
Oscillator Frequency
VCC = 15 V A
= −1.0
2.55 V
V
T
A
= 25°C
= 25°C
75
70
65
CT = 10 nF
5.0 nF
2.0 nF
60
55
% DT, PERCENT OUTPUT DEADTIME
50
10 k 20 k 50 k 100 k 200 k 500 k 1.0 M
f
, OSCILLATOR FREQUENCY (Hz)
osc
500 pF
Figure 3. Output Deadtime versus
Oscillator Frequency
VCC = 15 V A
= −1.0
3.0 V
V
T
A
= 25°C
200 pF
1.0 nF
100 pF
2.5 V
2.45 V
100
80
60
40
20
, OPEN LOOP VOLTAGE GAIN (dB)
0
VOL
A
−20
0.5 ms/DIV
Figure 4. Error Amp Small Signal
Transient Response
VCC = 15 V V
= 2.0 V to 4.0 V
O
R
= 100 K
Gain
100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz)
L
T
= 25°C
A
Phase
2.5 V
20 mV/DIV
2.0 V
0
30
60
90
120
150
180
10 M10
1.2
1.0
0.8
0.6
0.4
, EXCESS PHASE (DEGREES)
0.2
φ
, CURRENT SENSE INPUT THRESHOLD (V)
th
V
1.0 ms/DIV
Figure 5. Error Amp Large Signal
Transient Response
VCC = 15 V
TA = 25°C
TA = 125°C
TA = −55°C
0
0
2.0 4.0 6.0 8.0 , ERROR AMP OUTPUT VOLTAGE (V)
V
O
200 mV/DIV
Figure 6. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 7. Current Sense Input Threshold
versus Error Amp Output Voltage
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UC3844, UC3845, UC2844, UC2845
0
VCC = 15 V
−4.0
−8.0
−12
−16
−20
ref
V Δ , REFERENCE VOLTAGE CHANGE (mV)
−24 0 20 40 60 80 100 120
TA = 125°C
TA = −55°C
TA = 25°C
, REFERENCE SOURCE CURRENT (mA)
I
ref
Figure 8. Reference Voltage Change
versus Source Current
VCC = 15 V I
= 1.0 mA to 20 mA
O
TA = 25°C
110
VCC = 15 V
≤ 0.1 W
R
L
90
70
50
SC
−55 −25 0 25 50 75 100 125
, REFERENCE SHORT CIRCUIT CURRENT (mA)
, AMBIENT TEMPERATURE (°C)
I
T
A
Figure 9. Reference Short Circuit Current
versus Temperature
VCC = 12 V to 25 V T
= 25°C
A
O
V Δ , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
Figure 10. Reference Load Regulation Figure 11. Reference Line Regulation
0
−1.0
−2.0
3.0
2.0
, OUTPUT SATURATION VOLTAGE (V)
1.0
sat
V
0
V
CC
TA = 25°C
TA = −55°C
Figure 12. Output Saturation Voltage
2.0 ms/DIV
Source Saturation
(Load to Ground)
TA = −55°C
Sink Saturation
(Load to V
I
, OUTPUT LOAD CURRENT (mA)
O
)
CC
versus Load Current
VCC = 15 V
80 ms Pulsed Load
120 Hz Rate
TA = 25°C
GN
D
O
V Δ , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
2.0 ms/DIV
VCC = 15 V C
= 1.0 nF
90%
L
T
A
= 25°C
10%
8006004002000
50 ns/DIV
Figure 13. Output Waveform
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UC3844, UC3845, UC2844, UC2845
VCC = 30 V
25
C
= 15 pF
, OUTPUT VOLTAGE
CC
V
, SUPPLY CURRENT
CC
I
100 ns/DIV
L
= 255C
T
A
, SUPPLY CURRENT (mA)
CC
I
100 mA/DIV 20 V/DIV
20
15
10
5
UCX845
0
010203040
UCX844
, SUPPLY VOLTAGE (V)
V
CC
RT = 10 k C
= 3.3 nF
T
= 0 V
V
FB
I
= 0 V
Sense
T
= 255C
A
Figure 14. Output Cross Conduction Figure 15. Supply Current versus
Supply Voltage
PIN FUNCTION DESCRIPTION
Pin
8−Pin 14−Pin
1 1 Compensation This pin is Error Amplifier output and is made available for loop compensation.
2 3 Voltage
3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this
4 7 RT/C
5 − GND This pin is combined control circuitry and power ground (8−pin package only).
6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are
7 12 V
8 14 V
− 8 Power Ground This pin is a separate power ground return (14−pin package only) that is connected back to
− 11 V
− 9 GND This pin is the control circuitry ground return (14−pin package only) and is connected to back
− 2,4,6,13 NC No connection (14−pin package only). These pins are not internally connected.
Function Description
This is the inverting input of the Error Amplifier. It is normally connected to the switching
Feedback
power supply output through a resistor divider.
information to terminate the output switch conduction.
T
The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to V
and capacitor CT to ground. Operation to 1.0 MHz is possible.
ref
sourced and sunk by this pin. The output switches at one−half the oscillator frequency.
CC
ref
This pin is the positive supply of the control IC.
This is the reference output. It provides charging current for capacitor CT through resistor RT.
the power source. It is used to reduce the effects of switching transient noise on the control circuitry.
C
The Output high state (VOH) is set by the voltage applied to this pin (14−pin package only). With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry.
to the power source ground.
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UC3844, UC3845, UC2844, UC2845
OPERATING DESCRIPTION
The UC3844, UC3845 series are high performance, fixed frequency, current mode controllers. They are specifically designed for Off−Line and DC−to−DC converter applications offering the designer a cost effective solution with minimal external components. A representative block diagram is shown in Figure 16.
Oscillator
The oscillator frequency is programmed by the values selected for the timing components R
and CT. Capacitor C
T
is charged from the 5.0 V reference through resistor RT to approximately 2.8 V and discharged to 1.2 V by an internal current sink. During the discharge of C
, the oscillator
T
generates an internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. An internal flip−flop has been incorporated in the UCX844/5 which blanks the output off every other clock cycle by holding one of the inputs of the NOR gate high. This in combination with the C
discharge period yields output
T
deadtimes programmable from 50% to 70%. Figure 2 shows R
versus Oscillator Frequency and Figure 3, Output
T
Deadtime versus Frequency, both for given values of C Note that many values of R
and CT will give the same
T
oscillator frequency but only one combination will yield a specific output deadtime at a given frequency.
In many noise sensitive applications it may be desirable to frequency−lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 18. For reliable locking, the free−running oscillator frequency should be set about 10% less than the clock frequency. A method for multi unit synchronization is shown in Figure 19. By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved to realize output deadtimes of greater than 70%.
Error Amplifier
A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical dc voltage gain of 90 dB, and a unity gain bandwidth of
1.0 MHz with 57 degrees of phase margin (Figure 6). The noninverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is −2.0 mA which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provide for external loop compensation (Figure 29). The output voltage is offset by two diode drops (≈ 1.4 V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when Pin 1 is at its lowest state (V
OL
This occurs when the power supply is operating and the load is removed, or at the beginning of a soft−start interval (Figures 21, 22). The Error Amp minimum feedback resistance is limited by the amplifier’s source current (0.5 mA) and the required output voltage (V
) to reach the
OH
comparator’s 1.0 V clamp level:
R
f(min)
Current Sense Comparator and PWM Latch
T
3.0 (1.0 V) + 1.4 V
≈
0.5 mA
= 8800 W
The UC3844, UC3845 operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus the error signal controls the inductor current on a cycle−by−cycle basis. The current Sense Comparator PWM Latch configuration used ensures that only a single pulse appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground referenced sense resistor R
in series with the source of
S
output switch Q1. This voltage is monitored by the Current
.
T
Sense Input (Pin 3) and compared a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where:
− 1.4 V
V
Ipk =
(Pin 1)
3 R
S
Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the maximum peak switch current is:
I
pk(max)
1.0 V
=
R
S
When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of R
to a reasonable
S
level. A simple method to adjust this voltage is shown in Figure 20. The two external diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the I
pk(max)
clamp
voltage.
A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability; refer to Figure 24.
).
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UC3844, UC3845, UC2844, UC2845
V
CC
7(12)
V
V
CC
in
V
R
T
C
T
Voltage Feedback Input
Output Compensation
ref
8(14)
2.5V
R
Internal
Bias
R
3.6V
4(7)
Oscillator
+
1.0mA
+
2(3)
−
Error
2R
R
Amplifier
1(1)
5(9)GND
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
Figure 16. Representative Block Diagram
Reference
Regulator
+
−
+
−
− +
1.0V
Current Sense Comparator
V
ref
UVLO
S
R
V
CC
UVLO
QT
Q
PWM Latch
+
−
+
− +
−
=
36V
V
C
7(11)
Output
6(10)
Power Ground
5(8)
Current Sense Input
3(5)
Sink Only Positive True Logic
Q1
R
S
Capacitor C
Latch
‘‘Set’’ Input
Output/
Compensation
Current Sense
Input
Latch
‘‘Reset’’ Input
Output
T
Large RT/Small C
T
Small RT/Large C
T
Figure 17. Timing Diagram
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UC3844, UC3845, UC2844, UC2845
Undervoltage Lockout
Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (V
and the reference output (V
CC
ref
) are each monitored by separate comparators. Each has built−in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The V
comparator
CC
upper and lower thresholds are 16 V/10 V for the UCX844, and 8.4 V/7.6 V for the UCX845. The V
comparator upper
ref
and lower thresholds are 3.6 V/3/4 V. The large hysteresis and low startup current of the UCX844 makes it ideally suited in off−line converter applications where efficient bootstrap startup techniques later required (Figure 30). The UCX845 is intended for lower voltage DC−to−DC converter applications. A 36 V zener is connected as a shunt regulator from V
to ground. Its purpose is to protect the IC from
CC
excessive voltage that can occur during system startup. The minimum operating voltage for the UCX844 is 11 V and
8.2 V for the UCX845.
Output
These devices contain a single totem pole output stage that
was specifically designed for direct drive of power MOSFETs. It is capable of up to± 1.0 A peak drive current and has a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the Output in a sinking mode whenever and undervoltage lockout is active. This characteristic eliminates the need for an external pull−down resistor.
The SOIC−14 surface mount package provides separate
pins for V
(output supply) and Power Ground. Proper
C
implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the I
pk(max)
clamp level. The separate VC supply input allows the
designer added flexibility in tailoring the drive voltage independent of V
A zener clamp is typically connected
CC.
to this input when driving power MOSFETs in systems where V
is greater the 20 V. Figure 23 shows proper
CC
power and control ground connections in a current sensing power MOSFET application.
Reference
The 5.0 V bandgap reference is trimmed to± 1.0%
tolerance at T
= 25°C on the UC284X, and± 2.0% on the
J
UC384X. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short circuit protection and is capable of providing in excess of 20 mA for powering additional control system circuitry.
Design Considerations
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. High frequency
circuit layout techniques are imperative to prevent pulsewidth jitter. This is usually caused by excessive noise pick−up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low−current signal and high−current switch and output grounds returning on separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1 mF) connected directly to V and V
may be required depending upon circuit layout.
ref
CC
, VC,
This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise generating components.
V
ref
8(14)
R
T
External Sync Input
0.01
The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300 mV below ground.
4(7)
C
T
47
2(3)
1(1)
R
Bias
R
OSC
+
+
− EA
2R
R
5(9)
R
A
8
R
B
5.0k
6
5
5.0k
2
5.0k
C
1
1.44
f =
+ 2RB)C
(R
A
4
+
R
− Q
+
S
−
MC1455
R
B
=
D
max
RA + 2R
8(14)
3
7
4(7)
2(3)
1(1)
To Additional
B
UCX84XA’s
Figure 18. External Clock Synchronization Figure 19. External Duty Cycle Clamp and
Multi−Unit Synchronization
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9
R
Bias
R
OSC
+
+
− EA
2R
R
5(9)
UC3844, UC3845, UC2844, UC2845
V
CC
7(12)
V
in
T
S
Q
R
Comp/Latch
I
pk(max)
+
− +
−
≈
Where: 0 ≤ V
V
Clamp
R
7(11)
6(10)
5(8)
3(5)
S
Clamp
≤ 1.0 V
Q1
8(14)
R
Bias
R
OSC
4(7)
R
S
2(3)
1.0M
1(1)
C
t
Soft−Start
+
1.0mA
+
− EA
3600C in mF
V
R2
R1
Clamp
8(14)
4(7)
2(3)
1(1)
5.0V
V
+
−
Clamp
ref
+
−
− +
R
Bias
R
OSC
+
1.0mA
+
− EA
2R
R
1.0V
5(9)
1.67
R
2
+ 1
R
1
+ 0.33 x 10
−3
R
1
R1 + R
R
2
2
Figure 20. Adjustable Reduction of Clamp Level Figure 21. Soft−Start Circuit
V
CC
V
in
V
CC
(12)
T
S
Q
R
Comp/Latch
Control CIrcuitry
+
− +
−
Ground:
To Pin (9)
(11)
(10)
(8)
(5)
G
R
1/4 W
5.0V
Q1
ref
+
−
+
−
R
S
− +
Virtually lossless current sensing can be achieved with the implement of a SENSEFET power switch. For proper operation during over current conditions, a reduction of the
clamp level must be implemented. Refer to Figures 20 and 22.
I
pk(max)
Figure 23. Current Sensing Power MOSFET
5.0V
V
Clamp
5(9)
−3
≤ 1.0 V
R
C
R
+
−
1
1.0V
1
+ R
R
ref
+
−
− +
Comp/Latch
R
R
1
R1 + R
2
2
T
S
Q
R
2
2
C
I
pk(max)
t
8(14)
R2
R1
≈
Softstart
4(7)
+
−
2(3)
1(1)
MPSA63
V
Clamp
V
Clamp
R
S
= − In 1 −
R
Bias
R
OSC
+
1.0mA
EA
1.67
R
2
+ 1
R
1
Where: 0 ≤ V
V
C
3V
Clamp
2R
R
+ 0.33 x 10
Clamp
Figure 22. Adjustable Buffered Reduction of
7(12)
+
− +
−
7(11)
6(10)
5(8)
3(5)
Clamp Level with Soft−Start
V
CC
7(12)
V
in
5.0V
+
−
2R
R
1.0V
5(9)
V
in
5 ≈
V
Pin
If: SENSEFET = MTP10N10M
Then: V
D
SENSEFET
S
K
M
Power Ground
To Input Source
Return
S
ref
+
−
T
S
Q
− R
+
R
Ipk r
S
DS(on)
+ R
r
DM(on)
S
R
= 200
S
5 = 0.075 I
pin
pk
T
S
Q
R
Comp/Latch
+
− +
−
7(11)
Q1
6(10)
5(8)
R
3(5)
C
The addition of the RC filter will eliminate
R
S
instability caused by the leading edge spike on the current waveform.
5.0V
ref
+
−
+
−
− +
Figure 24. Current Waveform Spike Suppression
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10
UC3844, UC3845, UC2844, UC2845
V
CC
7(12)
5.0V
ref
+
−
+
−
− +
+
− +
−
7(11)
T
S
Q
R
6(10)
5(8)
V
R
Q1
g
Comp/Latch
3(5)
Series gate resistor R caused by the MOSFET input capacitance and any series wiring inductance
will damp any high frequency parasitic oscillations
g
R
in the gate−source circuit.
Figure 25. MOSFET Parasitic Oscillations
V
CC
7(12)
−
5.0V
+
ref
+
−
− +
Comp/Latch
+
− +
−
T
S
Q
R
7(11)
6(10)
5(8)
3(5)
C
Isolation
Boundary
R
R
S
Q1
N
S
in
S
V
in
Waveforms
V
GS
+ 0
− 50% DC 25% DC
V
− 1.4
(pin 1)
Ipk =
3 R
S
N
p
I
B
+
0
−
Base
Charge
Removal
C
6(1)
V
in
1
Q1
5(8)
3(5)
The totem−pole output can furnish negative base current for enhanced transistor turn−off, with the addition of capacitor C
R
S
.
1
Figure 26. Bipolar Transistor Drive
8(14)
4(7)
2(3)
2N
3903
1(1)
+ 0
−
N
P
N
S
MCR
101
The MCR101 SCR must be selected for a holding of less than 0.5 mA at T The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10 k.
2N
3905
R
Bias
R
OSC
+
1.0mA
+
− EA
2R
R
5(9)
.
A(min)
Figure 27. Isolated MOSFET Drive Figure 28. Latched Shutdown
From V
O
R
i
C
R
I
d
2.5V
+
2(3)
R
f
1.0mA
+
− EA
2R
R
1(1)
Rf ≥8.8 k
Error Amp compensation circuit for stabilizing any current−mode topology except for boost and flyback converters operating with continuous inductor current.
5(9)
From V
O
R
p
R
i
C
R
I
C
d
p
2.5V
+
2(3)
R
f
+
− EA
1(1)
Error Amp compensation circuit for stabilizing current−mode boost and flyback topologies operating with continuous inductor current.
Figure 29. Error Amplifier Compensation
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11
1.0mA
2R
R
5(9)
UC3844, UC3845, UC2844, UC2845
4.7W
115VA
C
8(14)
0.01
33k
4(7)
1.0nF
18k
4.7k
T1 − Primary: 45 Turns # 26 AWG
T1 − Secondary± 12 V: 9 Turns # 30 AWG
T1 − (2 strands) Bifiliar Wound
T1 − Secondary 5.0 V: 4 Turns (six strands)
T1 − #26 Hexfiliar Wound
T1 − Secondary Feedback: 10 Turns #30 AWG
T1 − (2 strands) Bifiliar Wound
T1 − Core: Ferroxcube EC35−3C8 T1 − Bobbin: Ferroxcube EC35PCB1 T1 − Gap≈ 0.01" for a primary inductance of 1.0 mH
L1 − 15 mH at 5.0 A, Coilcraft Z7156.
L2, L3 − 25 mH at 1.0 A, Coilcraft Z7157.
100pF
2(3)
1(1)
150k
+
−
Bias
OSC
+
EA
MDA
202
5(9)
5.0V
+
+
ref
+
−
− +
Comp/Latch
250
S
R
4.7k
56k
1N4935 1N4935
7(12)
100
+
+
−
T
Q
7(11)
6(10)
5(8)
3(5)
1N4937
1N5819
68
22W
1.0k
470pF
3300pF
++
47
MTP
4N50
0.5W
T1
680pF
2.7k
Figure 30. 27 Watt Off−Line Flyback Regulator
Test
Line Regulation: 5.0 V
Vin = 95 VAC to 130 VAC
± 12 V
Load Regulation: 5.0 V
± 12 V
Output Ripple: 5.0 V
Vin = 115 VAC, I V
= 115 VAC, I
in
mA
Vin = 115 VAC 40 mV
± 12 V
Efficiency Vin = 115 VAC 70%
All outputs are at nominal load currents, unless otherwise noted.
Conditions Results
= 1.0 A to 4.0 A
out
= 100 mA to 300
out
MBR1635
+
2200 1000
MUR110
+
1000
1000 10
++
MUR110
1N4937
L1
5.0V/4.0A
+
5.0V RTN
12V/0.3A
+L2
10
±12V RTN
−12V/0.3A
L3
D = 50 mV or± 0.5% D = 24 mV or± 0.1%
D = 300 mV or± 3.0% D = 60 mV or± 0.25%
pp
80 mV
pp
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12
UC3844, UC3845, UC2844, UC2845
Vin = 15V
10k
1.0nF
8(14)
4(7)
2(3)
1(1)
2.5V
R
R
+
−
Error
Amplifier
Internal
Oscillator
+
0.5mA
Bias
2R
UC3845
R
3.6V
1.0V
Reference
Regulator
+
−
+
−
UVLO
− +
V
CC
UVLO
V
ref
T
S
Q
R
PWM Latch
7(12)
+
− +
−
Current Sense Comparator
5(9)
The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor may be required when using tantalum or other low ESR capacitors. The converter’s output can provide excellent line and load regulation by connecting the R2/R1 resistor divider as shown.
Figure 31. Step−Up Charge Pump Converter
34V
7(11)
6(10)
5(8)
3(5)
15 10
V
O = 2.5
+
1N5819
Connect to Pin 2 for closed loop operation.
47
Output Load Regulation
(open loop configuration)
IO (mA) VO (V)
1N5819
+
R2
R2 R2
+ 1
R1
0 2 9 18 36
+
29.9
28.8
28.3
27.4
24.4
2 (Vin)
V
O
47
UC3845
10k
1.0nF
8(14)
4(7)
2(3)
1(1)
2.5V
R
R
+
−
Error
Amplifier
Internal
Oscillator
+
0.5mA
Bias
2R
R
3.6V
1.0V
Reference
Regulator
+
−
+
−
UVLO
− +
V
CC
UVLO
V
ref
T
S
Q
R
PWM Latch
Current Sense Comparator
5(9)
The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor may be required when using tantalum or other low ESR capacitors.
Vin = 15V
7(12)
+
−
34V
+
+
47
− 7(11)
6(10)
+
15 10
1N5819
1N5819
− (Vin)
V
+
O
47
5(8)
Output Load Regulation
3(5)
IO (mA) VO (V)
0 2 9 18 32
−14.4
−13.2
−12.5
−11.7
−10.6
Figure 32. Voltage−Inverting Charge Pump Converter
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13
UC3844, UC3845, UC2844, UC2845
ORDERING INFORMATION
Device Operating Temperature Range Package Shipping
UC3844D
UC3844DG
SOIC−14
SOIC−14
55 Units/Rail
55 Units/Rail
(Pb−Free)
UC3844DR2
UC3844DR2G
SOIC−14
SOIC−14
2500 Tape & Reel
2500 Tape & Reel
(Pb−Free)
UC3844N
UC3844NG
UC3845D
UC3845DG
T
= 0° to +70°C
A
PDIP−8
PDIP−8
(Pb−Free)
SOIC−14
SOIC−14
50 Units/Rail
50 Units/Rail
55 Units/Rail
55 Units/Rail
(Pb−Free)
UC3845DR2
UC3845DR2G
SOIC−14
SOIC−14
2500 Tape & Reel
2500 Tape & Reel
(Pb−Free)
UC3845N
UC3845NG PDIP−8
PDIP−8
50 Units/Rail
50 Units/Rail
(Pb−Free)
UC2844D
UC2844DG
SOIC−14
SOIC−14
55 Units/Rail
55 Units/Rail
(Pb−Free)
UC2844DR2
UC2844DR2G
SOIC−14
SOIC−14
2500 Tape & Reel
2500 Tape & Reel
(Pb−Free)
UC2844N
UC2844NG
PDIP−8
PDIP−8
50 Units/Rail
50 Units/Rail
(Pb−Free)
UC2845D
UC2845DG
A
SOIC−14
SOIC−14
55 Units/Rail
55 Units/Rail
T
= −25° to +85°C
(Pb−Free)
UC2845DR2
UC2845DR2G
SOIC−14
SOIC−14
2500 Tape & Reel
2500 Tape & Reel
(Pb−Free)
UC2845N
UC2845NG
PDIP−8
PDIP−8
50 Units/Rail
50 Units/Rail
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
†
PDIP−8
N SUFFIX
CASE 626
8
UC384xN
YYWWG
1
8
UC284xN
YYWWG
1
AWL
AWL
SOIC−14
D SUFFIX
CASE 751A
14
UC384xDG
AWLYWW
1
14
UC284xDG
AWLYWW
1
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14
SOIC−8
D1 SUFFIX
CASE 751
8
384x
ALYW
G
1
x = 4 or 5 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package
NOTE 2
−T−
SEATING PLANE
H
58
−B−
14
F
−A−
C
N
D
G
0.13 (0.005) B
UC3844, UC3845, UC2844, UC2845
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE L
L
J
K
M
M
A
T
M
M
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400 B 6.10 6.60 0.240 0.260 C 3.94 4.45 0.155 0.175 D 0.38 0.51 0.015 0.020 F 1.02 1.78 0.040 0.070 G 2.54 BSC 0.100 BSC H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012 K 2.92 3.43 0.115 0.135 L 7.62 BSC 0.300 BSC M −−− 10 −−− 10 N 0.76 1.01 0.030 0.040
INCHESMILLIMETERS
__
−T−
SEATING PLANE
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
−A−
14
1
G
D 14 PL
0.25 (0.010) A
8
−B−
P
7 PL
M
0.25 (0.010) B
7
X 45
C
R
K
M
S
B
T
S
M
_
M
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL
F
CONDITION.
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7
__ __
P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019
INCHESMILLIMETERS
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15
UC3844, UC3845, UC2844, UC2845
PACKAGE DIMENSIONS
SOIC−8
D1 SUFFIX
CASE 751−07
ISSUE AG
−Y−
−Z−
−X−
A
58
B
1
S
0.25 (0.010)
4
M
M
Y
K
G
C
SEATING PLANE
0.10 (0.004)
H
D
0.25 (0.010) Z
M
Y
SXS
N
X 45
_
M
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050
M 0 8 0 8
____
N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244
INCHES
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm
ǒ
inches
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
SENSEFET is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com
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For additional information, please contact your local Sales Representative
UC3844/D
16
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