NUP8011MU
Transient Voltage Suppressors
ESD Protection Diodes with Low
Clamping Voltage Array
This integrated transient voltage suppressor device (TVS) is
designed for applications requiring transient overvoltage protection. It
is intended for use in sensitive equipment such as computers, printers,
business machines, communication systems, and other applications.
Its integrated design provides very effective and reliable protection for
eight separate lines using only one package. These devices are ideal
for situations where board space is at a premium.
Features
• Low Clamping Voltage
• UDFN Package, 1.2 x 1.8 mm
• Standoff Voltage: 4.3 V
• Low Leakage Current
• IEC61000−4−2, Level 4 ESD Protection
• Moisture Sensitivity Level 1
• This is a Pb−Free Device
Benefits
• Provides Protection for ESD Industry Standards: IEC 61000, HBM
• Protects the Line Against Transient Voltage Conditions
• Minimize Power Consumption of the System
• Minimize PCB Board Space
Applications
• ESD Protection for Data Lines
• Wireless Phones
• Handheld Products
• Notebook Computers
• LCD Displays
MAXIMUM RATINGS (T
Characteristic Symbol Value Unit
Steady State Power − 1 Diode (Note 1) P
Thermal Resistance,
Junction−to−Ambient
Above 25°C, Derate
Maximum Junction Temperature T
Operating Temperature Range T
Storage Temperature Range T
Lead Solder Temperature (10 seconds
duration)
IEC 61000−4−2 (ESD)Contact $8.0 kV
Machine Model − Class C MM 400 V
Human Body Model − Class 3B HBM 8.0 kV
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Only 1 diode under power. For all 4 diodes under power, PD will be 25%.
Mounted on FR−4 board with min pad.
See Application Note AND8308/D for further description of
survivability specs.
= 25°C unless otherwise noted)
A
D
R
q
JA
Jmax
−40 to +85 °C
OP
−55 to +150 °C
stg
T
L
380 mW
327
3.05
150 °C
260 °C
°C/W
mW/°C
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1
2 7
3 6
4 5
(Top View)
8
1
UDFN8
CASE 517AD
P3 = Specific Device Code
M = Month Code
G = Pb−Free Package
PIN CONNECTIONS
14
ORDERING INFORMATION
Device Package Shipping
NUP8011MUTAG UDFN8
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
8
MARKING
DIAGRAM
P3 M
G
1
58
3000 / Tape & Reel
© Semiconductor Components Industries, LLC, 2009
September, 2009 − Rev. 2
1 Publication Order Number:
NUP8011MU/D
NUP8011MU
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol Parameter
V
I
V
RWM
V
P
Maximum Reverse Peak Pulse Current
PP
Clamping Voltage @ I
C
PP
Working Peak Reverse Voltage
I
R
BR
I
T
I
F
V
pk
Maximum Reverse Leakage Current @ V
Breakdown Voltage @ I
Test Current
Forward Current
Forward Voltage @ I
F
F
Peak Power Dissipation
T
RWM
VCV
BR
V
RWM
I
I
F
I
V
R
F
I
T
I
PP
Uni−Directional
V
C Capacitance @ VR = 0 and f = 1.0 MHz
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (T
Breakdown Voltage
VBR @ 1 mA (V)
Device
Device
Marking
Min Nom Max V
= 25°C)
A
Leakage Current
IRM @ V
RWM
RM
I
RWM
(mA)
Typ Capacitance
@ 0 V Bias (pF)
(Note 2)
Typ Capacitance
@ 3 V Bias (pF)
(Note 2)
Typ Max Typ Max
V
C
Per IEC61000−4−2
(Note 3)
NUP8011MUTAG P3 6.47 6.8 7.14 4.3 1.0 12 14 6.7 9.5 Figures 1 and 2
(See Below)
2. Capacitance of one diode at f = 1 MHz, VR = 0 V, TA = 25°C
3. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
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Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
2
NUP8011MU
IEC 61000−4−2 Spec.
Test
Voltage
Level
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
(kV)
ESD Gun
First Peak
Current
(A)
Current at
30 ns (A)
TVS
50 W
Cable
IEC61000−4−2 Waveform
I
peak
Current at
60 ns (A)
Figure 3. IEC61000−4−2 Spec
100%
90%
I @ 30 ns
I @ 60 ns
10%
Oscilloscope
50 W
tP = 0.7 ns to 1 ns
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
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3
NUP8011MU
TYPICAL ELECTRICAL CHARACTERISTICS
5.0
4.0
3.0
2.0
1.0
, REVERSE LEAKAGE (nA)
R
I
0
−100 0 100 150
−50 50
T, TEMPERATURE (°C)
Figure 5. Reverse Leakage versus
Temperature
1
0.1
14
12
10
8
(pF)
6
4
1 MHz FREQUENCY
TYPICAL CAPACITANCE
2
0
01 2 3 6
BIAS VOLTAGE (V)
TA = 25°C
45
Figure 6. Capacitance
0.01
, FORWARD CURRENT (A)
F
I
0.001
TA = 25°C
1.81.61.41.21.00.80.6
VF, FORWARD VOLTAGE (V)
Figure 7. Forward Voltage
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4
NUP8011MU
PACKAGE DIMENSIONS
UDFN8, 1.8x1.2, 0.4P
CASE 517AD−01
ISSUE C
2X
0.10 C
PIN ONE
REFERENCE
2X
8X
NOTE 4
0.10 C
0.05 C
0.05 C
DETAIL A
L8X
K8X
D
TOP VIEW
DETAIL B
SIDE VIEW
D2
1
8
e
e/2
BOTTOM VIEW
A1
A
B
E
A
J
E2
b
8X
(A3)
SEATING
C
PLANE
0.10 B
NOTE 3
0.05ACC
EXPOSED Cu
A1
CONSTRUCTIONS
(0.10)
L1
CONSTRUCTION
MOLD CMPD
A3
DETAIL B
ALTERNATE
DETAIL A
DETAIL A
OPTIONAL
0.05 MIN
L
7X
PACKAGE
OUTLINE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN MAX
A 0.45 0.55
A1 0.00 0.05
A3 0.13 REF
b 0.15 0.25
D 1.80 BSC
E 1.20 BSC
e 0.40 BSC
D2 0.90 1.10
E2 0.20 0.30
J 0.19 REF
K 0.20 −−−
L 0.20 0.30
L1 −−− 0.10
SOLDERING FOOTPRINT*
1.10
0.25
8X
0.45
1.50
0.35
1
0.35
0.40 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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5
NUP8011MU/D
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