ON NUP4202W1 Schematic [ru]

NUP4202W1

Transient Voltage
Suppressors

ESD Protection Diodes with Low
Clamping Voltage

The NUP4202W1 transient voltage suppressor is designed to

protect high speed data lines from ESD, EFT, and lightning.

Features

• Low Clamping Voltage

• Stand−Off Voltage: 5 V

• Low Leakage

• Protection for the Following IEC Standards:

IEC 61000−4−2 Level 4 ESD Protection

• UL Flammability Rating of 94 V−0

• This is a Pb−Free Device

Typical Applications

• High Speed Communication Line Protection

• USB 1.1 and 2.0 Power and Data Line Protection

• Digital Video Interface (DVI) and HDMI

• Monitors and Flat Panel Displays

• MP3

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SC−88 LOW CAPACITANCE

DIODE TVS ARRAY

500 WATTS PEAK POWER

6 VOLTS

PIN CONFIGURATION

AND SCHEMATIC

I/O 1

VN 2

I/O 3

6 I/O

5 V

4 I/O

P

MAXIMUM RATINGS (T

Rating Symbol Value Unit

Peak Power Dissipation
8 x 20 mS @ TA = 25°C (Note 1)

Operating Junction Temperature Range T

Storage Temperature Range T

Lead Solder Temperature −
Maximum (10 Seconds)

Human Body Model (HBM)
Machine Model (MM)
IEC 61000−4−2 Air (ESD)
IEC 61000−4−2 Contact (ESD)

IEC 61000−4−4 (5/50 ns) EFT 40 A

Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.

1. Nonrepetitive current pulse per Figure 5 (Pin 5 to Pin 2).

= 25°C unless otherwise noted)

J

P

pk

J

stg

T

L

ESD 16000

500 W

−40 to +125 °C

−55 to +150 °C

260 °C

V

400
20000
20000

See Application Note AND8308/D for further description of
survivability specs.

1

SC−88

CASE 419B

PLASTIC

MARKING DIAGRAM

6

63 MG

G

1

63 = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)

ORDERING INFORMATION

Device Package Shipping

NUP4202W1T2G SC−88

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

3000/Tape & Reel

© Semiconductor Components Industries, LLC, 2009

September, 2009 − Rev. 3

1 Publication Order Number:

NUP4202W1/D

NUP4202W1

ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol Parameter

I

V

V

RWM

V

V

P

*See Application Note AND8308/D for detailed explanations of

datasheet parameters.

ELECTRICAL CHARACTERISTICS (T

Reverse Working Voltage V

Breakdown Voltage V

Reverse Leakage Current I

Clamping Voltage V

Clamping Voltage V

Maximum Peak Pulse Current I

Junction Capacitance C

Junction Capacitance C

Clamping Voltage V

Clamping Voltage V

2. TVS devices are normally selected according to the working peak reverse voltage (V
or continuous peak operating voltage level.

3. VBR is measured at pulse test current IT.

4. Nonrepetitive current pulse per Figure 5 (Pin 5 to Pin 2).

5. Nonrepetitive current pulse per Figure 5 (Any I/O Pins).

6. Surge current waveform per Figure 5.

7. For test procedure see Figures 3 and 4 and Application Note AND8307/D.

Maximum Reverse Peak Pulse Current

PP

Clamping Voltage @ I

C

Working Peak Reverse Voltage

I

Maximum Reverse Leakage Current @ V

R

Breakdown Voltage @ I

BR

I

Test Current

T

I

Forward Current

F

Forward Voltage @ I

F

Peak Power Dissipation

pk

PP

VCV

RWM

T

F

C Capacitance @ VR = 0 and f = 1.0 MHz

=25°C unless otherwise specified)

J

Parameter Symbol Conditions Min Typ Max Unit

RWM

(Note 2) 5.0 V

IT = 1 mA, (Note 3) 6.0 V

BR

V

R

C

C

PP

J

J

C

C

= 5 V 5.0

RWM

IPP = 5 A (Note 4) 8.5 12.5 V

IPP = 8 A (Note 4) 8.9 20 V

8x20 ms Waveform (Note 4)

VR = 0 V, f = 1 MHz between I/O Pins and GND 3.0 5.0 pF

VR = 0 V, f = 1 MHz between I/O Pins 1.5 3.0 pF

@ IPP = 1 A (Notes 5 and 6) 14.5 V

Per IEC 61000−4−2 (Note 7) Figure 1 and 2 V

I

I

F

V

RWM

BR

I

V

R

F

I

T

I

PP

Uni−Directional TVS

28 A

), which should be equal or greater than the DC

RWM

V

mA

Figure 1. ESD Clamping Voltage Screenshot

Positive 8 kV Contact per IEC61000−4−2

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Figure 2. ESD Clamping Voltage Screenshot

Negative 8 kV Contact per IEC61000−4−2

2

NUP4202W1

IEC 61000−4−2 Spec.

Test

Voltage

Level

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

(kV)

ESD Gun

First Peak

Current

(A)

Current at

30 ns (A)

TVS

50 W
Cable

IEC61000−4−2 Waveform

I

peak

Current at

60 ns (A)

100%

90%

I @ 30 ns

I @ 60 ns

10%

Figure 3. IEC61000−4−2 Spec

Oscilloscope

50 W

tP = 0.7 ns to 1 ns

Figure 4. Diagram of ESD Test Setup

The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger

100

t

r

90

80

70

60

50

40

30

20

% OF PEAK PULSE CURRENT

10

0

020406080

PEAK VALUE I

t

P

Figure 5. 8 X 20 ms Pulse Waveform

systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.

@ 8 ms

RSM

PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms

HALF VALUE I

t, TIME (ms)

/2 @ 20 ms

RSM

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3

NUP4202W1

TYPICAL PERFORMANCE CURVES

(TJ = 25°C unless otherwise noted)

100

90

80

70

60

50

40

30

20

PEAK POWER DISSIPATION (%)

10

0

0 25 50 75 100 125 150 175 200

TA, AMBIENT TEMPERATURE (°C)

Figure 6. Pulse Derating Curve

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

JUNCTION CAPACITANCE (pF)

0.5

0.0
01

VBR, REVERSE VOLTAGE (V)

I/O−Ground

I/O lines

2345

Figure 7. Junction Capacitance vs Reverse Voltage

20

18

16

14

12

10

8

6

4

CLAMPING VOLTAGE (V)

2

0

010

20 30 40 50

PEAK PULSE CURRENT (A)

Figure 8. Clamping Voltage vs. Peak Pulse Current

(8 x 20 ms Waveform)

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4

NUP4202W1

APPLICATIONS INFORMATION

The new NUP4202W1 is a low capacitance TVS diode
array designed to protect sensitive electronics such as
communications systems, computers, and computer
peripherals against damage due to ESD events or transient
overvoltage conditions. Because of its low capacitance, it
can be used in high speed I/O data lines. The integrated
design of the NUP4202W1 offers surge rated, low
capacitance steering diodes and a TVS diode integrated in
a single package (SC−88). If a transient condition occurs, the
steering diodes will drive the transient to the positive rail of
the power supply or to ground. The TVS device protects the
power line against overvoltage conditions to avoid damage
to the power supply and any downstream components.

NUP4202W1 Configuration Options

The NUP4202W1 is able to protect up to four data lines
against transient overvoltage conditions by driving them to
a fixed reference point for clamping purposes. The steering
diodes will be forward biased whenever the voltage on the
protected line exceeds the reference voltage (Vf or V

CC

+
Vf). The diodes will force the transient current to bypass the
sensitive circuit.

Data lines are connected at pins 1, 3, 4 and 6. The negative
reference is connected at pin 2. This pin must be connected
directly to ground by using a ground plane to minimize the
PCB’s ground inductance. It is very important to reduce the
PCB trace lengths as much as possible to minimize parasitic
inductances.

Option 2

Protection of four data lines with bias and power supply

isolation resistor.

I/O 1

I/O 2

V

CC

1

2

3

I/O 3

I/O 4

6

10 k

5

4

The NUP4202W1 can be isolated from the power supply

by connecting a series resistor between pin 5 and VCC. A
10 kW resistor is recommended for this application. This
will maintain a bias on the internal TVS and steering diodes,
reducing their capacitance.

Option 3

Protection of four data lines using the internal TVS diode

as reference.

I/O 1

I/O 2

Option 1

Protection of four data lines and the power supply using
VCC as reference.

I/O 1

I/O 2

1

2

3

I/O 3

I/O 4

6

5

4

V

CC

For this configuration, connect pin 5 directly to the
positive supply rail (VCC), the data lines are referenced to
the supply voltage. The internal TVS diode prevents
overvoltage on the supply rail. Biasing of the steering diodes
reduces their capacitance.

1

2

3

I/O 3

I/O 4

6

5

4

NC

In applications lacking a positive supply reference or
those cases in which a fully isolated power supply is
required, the internal TVS can be used as the reference. For
these applications, pin 5 is not connected. In this
configuration, the steering diodes will conduct whenever the
voltage on the protected line exceeds the working voltage of
the TVS plus one diode drop (Vc = Vf + V

TVS

).

ESD Protection of Power Supply Lines

When using diodes for data line protection, referencing to
a supply rail provides advantages. Biasing the diodes
reduces their capacitance and minimizes signal distortion.
Implementing this topology with discrete devices does have
disadvantages. This configuration is shown below:

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5

NUP4202W1

Power

Supply

Protected

Device

Data Line

V

CC

D1

D2

I

ESDpos

I

ESDneg

I

ESDpos

VF + V

CC

I

ESDneg

−VF

Looking at the figure above, it can be seen that when a
positive ESD condition occurs, diode D1 will be forward
biased while diode D2 will be forward biased when a
negative ESD condition occurs. For slower transient
conditions, this system may be approximated as follows:

For positive pulse conditions:

Vc = VCC + Vf

D1

For negative pulse conditions:

Vc = −Vf

D2

ESD events can have rise times on the order of some
number of nanoseconds. Under these conditions, the effect
of parasitic inductance must be considered. A pictorial
representation of this is shown below.

inductance will provide significant benefits in transient
immunity.

Even with good board layout, some disadvantages are still
present when discrete diodes are used to suppress ESD
events across datalines and the supply rail. Discrete diodes
with good transient power capability will have larger die and
therefore higher capacitance. This capacitance becomes
problematic as transmission frequencies increase. Reducing
capacitance generally requires reducing die size. These
small die will have higher forward voltage characteristics at
typical ESD transient current levels. This voltage combined
with the smaller die can result in device failure.

The ON Semiconductor NUP4202W1 was developed to
overcome the disadvantages encountered when using
discrete diodes for ESD protection. This device integrates a
TVS diode within a network of steering diodes.

D1

D2

D3

D4

D5

D6

D7

D8

Power
Supply

V

CC

Protected

Device

D1

Data Line

D2

I

ESDpos

I

ESDpos

VC = VCC + Vf + (L diESD/dt)
I

ESDneg

VC = −Vf − (L diESD/

dt)

I

ESDneg

An approximation of the clamping voltage for these fast

transients would be:

For positive pulse conditions:

Vc = VCC + Vf + (L d

iESD

/dt)

For negative pulse conditions:

Vc = −Vf – (L d

iESD

/dt)

As shown in the formulas, the clamping voltage (Vc) not
only depends on the Vf of the steering diodes but also on the
L d

/dt factor. A relatively small trace inductance can

iESD

result in hundreds of volts appearing on the supply rail. This
endangers both the power supply and anything attached to
that rail. This highlights the importance of good board
layout. Taking care to minimize the effects of parasitic

0

Figure 9. NUP4202W1 Equivalent Circuit

During an ESD condition, the ESD current will be driven

to ground through the TVS diode as shown below.

Power

Supply

V

CC

I

ESDpos

D1

Protected

Device

Data Line

D2

The resulting clamping voltage on the protected IC will

be:

Vc = VF + V

TVS

.

The clamping voltage of the TVS diode is provided in
Figure 8 and depends on the magnitude of the ESD current.
The steering diodes are fast switching devices with unique
forward voltage and low capacitance characteristics.

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6

UPSTREAM

USB PORT

V

BUS

D+

D−

GND

V

BUS

NUP2202W1

V

BUS

NUP4202W1

TYPICAL APPLICATIONS

R

T

R

T

V

USB

Controller

C

C

T

T

R

T

R

T

C

C

T

T

Figure 10. ESD Protection for USB Port

BUS

NUP4202W1

V

BUS

V

BUS

D+

DOWNSTREAM

D−

USB PORT

GND

V

BUS

V

BUS

DOWNSTREAM

D+

D−

USB PORT

GND

PHY
Ethernet
(10/100)

TX+

TX−

Coupling

Transformers

RX+

RX−

NUP4202W1

V

CC

GND

N/C N/C

Figure 11. Protection for Ethernet 10/100 (Differential Mode)

RJ45

Connector

TX+

TX−

RX+

RX−

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7

RTIP

RRING

T1/E1

TRANCEIVER

TTIP

NUP4202W1

R1

R3

R2

V

CC

NUP4202W1

R4

T1

TRING

R5

T2

Figure 12. TI/E1 Interface Protection

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8

NUP4202W1

l

PACKAGE DIMENSIONS

SC−88/SC70−6/SOT−363

CASE 419B−02

ISSUE W

D

e

654

H

E

123

−E−

b 6 PL

A

MM

E0.2 (0.008)

A3

C

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. 419B−01 OBSOLETE, NEW STANDARD 419B−02.

MILLIMETERS

DIM MIN NOM MAX

A 0.80 0.95 1.10
A1 0.00 0.05 0.10
A3

b 0.10 0.21 0.30

C 0.10 0.14 0.25

D 1.80 2.00 2.20

E 1.15 1.25 1.35

e 0.65 BSC

L 0.10 0.20 0.30

H

E

0.20 REF 0.008 REF

2.00 2.10 2.20

INCHES

MIN NOM MAX

0.031 0.037 0.043

0.000 0.002 0.004

0.004 0.008 0.012

0.004 0.005 0.010

0.070 0.078 0.086

0.045 0.049 0.053

0.026 BSC

0.004 0.008 0.012

0.078 0.082 0.086

SOLDERING FOOTPRINT*

0.50

0.0197

A1

L

0.65

0.025

0.65

0.025

0.40

0.0157

1.9

0.0748

SCALE 20:1

mm

ǒ

inches

Ǔ

SC−88/SC70−6/SOT−363

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an
Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NUP4202W1/D