NUP412VP5
Low Capacitance
Quad Array for
ESD Protection
This integrated transient voltage suppressor device (TVS) is
designed for applications requiring transient overvoltage protection. It
is intended to be used in sensitive equipment such as wireless headsets,
PDAs, digital cameras, computers, printers, communication systems,
and other applications. The integrated design provides very effective
and reliable protection for four separate lines using only one package.
This device is ideal for situations where board space is at a premium.
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Features
• ESD Protection: IEC61000−4−2: Level 4
• Four Separate Unidirectional Configurations for Protection
• Low Leakage Current < 1 mA @ 9 V
• Small SOT−953 SMT Package
• Low Capacitance
• These are Pb−Free Devices
Benefits
• Provides Protection for ESD Industry Standards: IEC 61000, HBM
• Protects Four Lines Against Transient Voltage Conditions
• Minimize Power Consumption of the System
• Minimize PCB Board Space
Typical Applications
• Cellular and Portable Electronics
• Serial and Parallel Ports
• Microprocessor Based Equipment
• Notebooks, Desktops, Servers
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SOT−953
CASE 526AB
MARKING DIAGRAM
2M
1
2 = Specific Device Code
M = Date & Assembly Code
ORDERING INFORMATION
Device Package Shipping
NUP412VP5T5G SOT−953
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
4
†
8000 /
Tape & Reel
© Semiconductor Components Industries, LLC, 2008
May, 2008 − Rev. 1
1 Publication Order Number:
NUP412VP5/D
NUP412VP5
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol
V
QV
I
V
RWM
V
V
Z
I
Z
Maximum Reverse Peak Pulse Current
PP
Clamping Voltage @ I
C
Working Peak Reverse Voltage
I
Maximum Reverse Leakage Current @ V
R
Breakdown Voltage @ I
BR
I
Test Current
T
Maximum Temperature Coefficient of V
BR
I
Forward Current
F
Forward Voltage @ I
F
Maximum Zener Impedance @ I
ZT
Reverse Current
ZK
Maximum Zener Impedance @ I
ZK
MAXIMUM RATINGS (T
Parameter
PP
T
F
= 25°C unless otherwise noted)
A
ZT
ZK
BR
RWM
VCV
BR
V
RWM
I
I
F
I
V
R
F
I
T
I
PP
Uni−Directional
V
Characteristic Symbol Value Unit
Peak Power Dissipation (8 X 20 ms @ TA = 25°C) (Note 1)
Thermal Resistance Junction−to−Ambient
P
R
Above 25°C, Derate
Maximum Junction Temperature T
Jmax
Operating Junction and Storage Temperature Range TJ T
Lead Solder Temperature (10 seconds duration) T
Human Body Model (HBM)
ESD 8000
Machine Model (MM)
PK
q
JA
stg
L
18 W
560
4.5
°C/W
mW/°C
150 °C
−55 to +150 °C
260 °C
400
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Non−repetitive current.
ELECTRICAL CHARACTERISTICS (T
Device
= 25°C)
A
Device
Marking
Breakdown Voltage
@ 5 mA (Volts)
V
BR
Min Nom Max V
Leakage Current
@ V
I
RM
RM
I
RWM
(mA)
RWM
Typ Capacitance
@ 0 V Bias (pF)
(Note 2)
Typ Capacitance
@ 3 V Bias (pF)
(Note 2)
Typ Max Typ Max
NUP412VP5 (Note 3) 2 11.4 12 12.7 9.0 0.5 6.5 10 3.5 5.0
2. Capacitance of one diode at f = 1 MHz, TA = 25°C.
at 5 mA.
3. V
BR
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NUP412VP5
TYPICAL ELECTRICAL CHARACTERISTICS
0.0035
0.003
0.0025
0.002
0.0015
0.001
, REVERSE LEAKAGE (mA)
R
0.0005
I
0
−60 −40 −20 0 20 40 60 80 100 120 140 160
T, TEMPERATURE (°C)
Figure 1. Reverse Leakage versus
Temperature
100
t
r
90
80
70
60
50
40
30
20
% OF PEAK PULSE CURRENT
10
0
020406080
t
P
PEAK VALUE I
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I
t, TIME (ms)
RSM
@ 8 ms
RSM
/2 @ 20 ms
Figure 3. 8 × 20 ms Pulse Waveform
7.5
7
6.5
6
5.5
5
4.5
1 MHz FREQUENCY
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TYPICAL CAPACITANCE (pF)
3.5
3
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
1
0.1
0.01
, FORWARD CURRENT (A)
F
I
0.001
BIAS VOLTAGE (V)
Figure 2. Capacitance
TA = 25°C
1.81.61.41.21.00.80.6
VF, FORWARD VOLTAGE (V)
Figure 4. Forward Voltage
110
100
PP
90
80
70
60
50
40
30
20
% OF RATED POWER OR I
10
0
Figure 5. Power Derating Curve
1501251007550250
TA, AMBIENT TEMPERATURE (°C)
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NUP412VP5
PACKAGE DIMENSIONS
SOT−953
CASE 527AB−01
ISSUE B
D
45
12 3
e
−Y−
A
L
−X−
E
H
E
C
b
5X
X0.08
Y
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE MATERIAL.
MILLIMETERS
DIM MIN NOM MAX
A 0.34 0.42 0.50
b 0.10 0.15 0.20
C 0.05 0.10 0.15
D 0.95 1.00 1.05
E 0.75 0.80 0.85
e 0.35 BSC
L 0.05 0.10 0.15
H
E
0.95 1.00 1.05
INCHES
MIN NOM MAX
0.013 0.017 0.020
0.004 0.006 0.008
0.002 0.004 0.006
0.037 0.039 0.041
0.03 0.032 0.034
0.014 BSC
0.002 0.004 0.006
0.037 0.039 0.041
SOLDERING FOOTPRINT*
0.35
0.35
0.014
0.014
0.90
0.0354
0.20
0.08
0.20
0.08
mm
ǒ
SCALE 20:1
inches
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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PUBLICATION ORDERING INFORMATION
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NUP412VP5/D
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