ON NUP2114UCMR6T1G, NUP2114UPXV5T1G, SNUP2114UCMR6T1G Schematic [ru]

NUP2114 Series,
SNUP2114UCMR6T1G

Transient Voltage
Suppressors

Low Capacitance ESD Protection for
High Speed Data

The NUP2114 transient voltage suppressor is designed to protect
high speed data lines from ESD. Ultra−low capacitance and high level
of ESD protection makes this device well suited for use in USB 2.0
applications.

Features

 Low Capacitance 0.8 pF
 S Prefix for Automotive and Other Applications Requiring Unique

Site and Control Change Requirements

 AEC−Q101 Qualified and PPAP Capable − SNUP2114
 Low Clamping Voltage
 Stand Off Voltage: 5 V
 Low Leakage
 ESD Rating of Class 3B (Exceeding 8 kV) per Human Body model

and Class C (Exceeding 400 V) per Machine Model

 Protection for the Following IEC Standards:

IEC 61000−4−2 Level 4 ESD Protection

 UL Flammability Rating of 94 V−0
 These are Pb−Free Devices

Typical Applications

 High Speed Communication Line Protection
 USB 2.0 High Speed Data Line and Power Line Protection
 Monitors and Flat Panel Displays
 MP3
 Gigabit Ethernet
 Notebook Computers
 Digital Video Interface (DVI) and HDMI

MAXIMUM RATINGS (T

Rating

Operating Junction Temperature Range T

Storage Temperature Range T

Lead Solder Temperature −
Maximum (10 Seconds)

Human Body Model (HBM)
Machine Model (MM)
IEC 61000−4−2 Contact
IEC61000−4−2 Air

Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.

See Application Note AND8308/D for further description of
survivability specs.

= 25C unless otherwise noted)

J

Symbol Value Unit

J

stg

T

L

ESD 16000

−40 to +125 C

−55 to +150 C

260 C

V

400

8000

15000

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SOT−553

CASE 463B

I/O

MARKING DIAGRAMS

P2MG

G

1

SOT−553 TSOP−6

P2, P2M = Specific Device Code
M = Date Code
G = Pb−Free Package

(*Note: Microdot may be in either location)

PIN CONNECTIONS

15

V

P

2

V

N

34

NC

SOT−553

16

I/O

25

V

N

34

NC

TSOP−6

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.

TSOP−6

CASE 318G

V

P

V

N

P2M MG

1

G

I/O

I/O

I/O

V

NC

I/O

P

 Semiconductor Components Industries, LLC, 2012

March, 2012 − Rev. 1

1 Publication Order Number:

NUP2114/D

NUP2114 Series, SNUP2114UCMR6T1G

ELECTRICAL CHARACTERISTICS

(TA = 25C unless otherwise noted)

Symbol

V

I

V

RWM

V

V

P

Maximum Reverse Peak Pulse Current

PP

Clamping Voltage @ I

C

Working Peak Reverse Voltage

I

Maximum Reverse Leakage Current @ V

R

Breakdown Voltage @ I

BR

I

Test Current

T

I

Forward Current

F

Forward Voltage @ I

F

Peak Power Dissipation

pk

C Max. Capacitance @ VR = 0 and f = 1.0 MHz

*See Application Note AND8308/D for detailed explanations of

datasheet parameters.

ELECTRICAL CHARACTERISTICS (T

Parameter Symbol Conditions Min Typ Max Unit

Reverse Working Voltage V

Breakdown Voltage V

Reverse Leakage Current I

Clamping Voltage V

Clamping Voltage V

Maximum Peak Pulse Current I

Junction Capacitance C

Junction Capacitance C

Clamping Voltage V

Clamping Voltage V

1. TVS devices are normally selected according to the working peak reverse voltage (V
or continuous peak operating voltage level.

is measured at pulse test current IT.

2. V

BR

3. Nonrepetitive current pulse (Pin 5 to Pin 2)

4. Surge current waveform per Figure 5.

5. Typical waveform. For test procedure see Figures 3 and 4 and Application Note AND8307/D.

6. Include S-prefix devices where applicable.

Parameter

PP

T

F

RWM

BR

R

C

C

PP

J

J

C

C

V

RWM

=25C unless otherwise specified)

J

VCV

BR

RWM

(Note 1) 5.0 V

IT = 1 mA, (Note 2) 5.5 7.5 V

V

= 5 V 1.0

RWM

IPP = 5 A (Note 3) 9.0 V

IPP = 8 A (Note 3) 10 V

8x20 ms Waveform

VR = 0 V, f = 1 MHz between I/O Pins and GND 0.8 1.0 pF

VR = 0 V, f = 1 MHz between I/O Pins 0.5 pF

@ IPP = 1 A (Note 4) 12 V

Per IEC 61000−4−2 (Note 5) Figures 1 and 2 V

), which should be equal or greater than the DC

RWM

I

I

F

I

V

R

F

I

T

I

PP

Uni−Directional TVS

V

mA

12 A

Figure 1. ESD Clamping Voltage Screenshot

Positive 8 kV Contact per IEC61000−4−2

Figure 2. ESD Clamping Voltage Screenshot

Negative 8 kV Contact per IEC61000−4−2

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2

NUP2114 Series, SNUP2114UCMR6T1G

IEC 61000−4−2 Spec.

Test

Voltage

Level

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

(kV)

ESD Gun

First Peak

Current

(A)

Current at

30 ns (A)

TVS

50 W
Cable

IEC61000−4−2 Waveform

I

peak

Current at

60 ns (A)

100%

90%

I @ 30 ns

I @ 60 ns

10%

Figure 3. IEC61000−4−2 Spec

Oscilloscope

50 W

tP = 0.7 ns to 1 ns

Figure 4. Diagram of ESD Test Setup

The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger

100

t

r

90

80

70

60

50

40

30

20

% OF PEAK PULSE CURRENT

10

0

020406080

PEAK VALUE I

t

P

Figure 5. 8 X 20 ms Pulse Waveform

systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.

@ 8 ms

RSM

PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms

HALF VALUE I

t, TIME (ms)

/2 @ 20 ms

RSM

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3

NUP2114 Series, SNUP2114UCMR6T1G

Figure 6. 500 MHz Data Pattern

ORDERING INFORMATION

Device Marking Package Shipping

NUP2114UPXV5T1G P2 SOT−553

(Pb−Free)

NUP2114UCMR6T1G P2M TSOP−6

(Pb−Free)

SNUP2114UCMR6T1G P2M TSOP−6

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

4,000 / Tape & Reel

3,000 / Tape & Reel

3,000 / Tape & Reel

†

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4

NUP2114 Series, SNUP2114UCMR6T1G

PACKAGE DIMENSIONS

TSOP−6

CASE 318G−02

ISSUE U

E1

NOTE 5

0.05

A1

D

H

456

E

23

1

b

e

A

L

DETAIL Z

c

M

DETAIL Z

L2

GAUGE

PLANE

C

SEATING
PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.

4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.

5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.

DIMAMIN NOM MAX

A1 0.01 0.06 0.10

b 0.25 0.38 0.50

c 0.10 0.18 0.26
D 2.90 3.00 3.10
E 2.50 2.75 3.00

E1

e 0.85 0.95 1.05
L 0.20 0.40 0.60

L2

M

MILLIMETERS

0.90 1.00 1.10

1.30 1.50 1.70

0.25 BSC

0 10

−

RECOMMENDED

SOLDERING FOOTPRINT*

6X

0.60

3.20

6X

0.95

0.95
PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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5

D

−X−

45

12 3

e

NUP2114 Series, SNUP2114UCMR6T1G

E

−Y−

b

5 PL

0.08 (0.003) X

M

PACKAGE DIMENSIONS

SOT−553, 6 LEAD

CASE 463B−01

ISSUE B

A

Y

L

H

E

c

SOLDERING FOOTPRINT*

0.3

0.0118

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS

3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.

DIMAMIN NOM MAX MIN

b 0.17 0.22 0.27 0.007
c
D 1.50 1.60 1.70 0.059
E 1.10 1.20 1.30 0.043
e 0.50 BSC
L 0.10 0.20 0.30 0.004

H

E

MILLIMETERS

0.50 0.55 0.60 0.020

0.08 0.13 0.18

1.50 1.60 1.70 0.059 0.063 0.067

0.003 0.005 0.007

INCHES

NOM MAX

0.022 0.024

0.009 0.011

0.063 0.067

0.047 0.051

0.020 BSC

0.008 0.012

0.45

0.0177

1.0

1.35

0.0394

0.0531

0.5

0.5

0.0197

0.0197

mm

ǒ

SCALE 20:1

inches

Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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For additional information, please contact your local
Sales Representative

NUP2114/D