NL17SZ16
Single Input Buffer
The NL17SZ16 is a single input Buffer in two tiny footprint
packages. The device performs much as LCX multi−gate products in
speed and drive.
Features
• Tiny SOT−353 and SOT−553 Packages
• Source/Sink 24 mA at 3.0 Volts
• Over−Voltage Tolerant Inputs and Outputs
• Chip Complexity: FETs = 20
• Designed for 1.65 V to 5.5 V V
• Pb−Free Packages are Available
Operation
CC
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5
1
SOT−353/SC70−5/SC−88A
DF SUFFIX
CASE 419A
MARKING
DIAGRAMS
5
LR M G
G
1
NC
1
A
2
3
GND
Figure 1. Pinout (Top View)
A
1
Figure 2. Logic Symbol
5
1
5
V
CC
4
Y
*Date Code orientation and/or position may vary
SOT−553
XV5 SUFFIX
CASE 463B
LR = Device Code
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
depending upon manufacturing location.
5
LR M G
G
1
PIN ASSIGNMENT
Pin Function
Y
1
2
3 GND
4
5V
NC
IN A
OUT Y
CC
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 7
FUNCTION TABLE
A Input Y Output
L
HH
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
1 Publication Order Number:
NL17SZ16/D
NL17SZ16
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
V
I
I
OK
I
OUT
I
CC
I
GND
T
STG
T
T
q
P
MSL Moisture Sensitivity Level 1
F
ESD ESD Classification Human Body Model (Note 3)
I
Latchup
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. IO Absolute Maximum Rating Must be Obtained.
3. Tested to EIA/JESD22−A114−A, rated to EIA/JESD22−A114−B.
4. Tested to EIA/JESD22−A115−A, rated to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
DC Supply Voltage *0.5 to )7.0 V
CC
DC Input Voltage Output in High or Low State (Note 2) *0.5 v VI v )7.0 V
I
DC Output Voltage VI < GND *0.5 v VO v )7.0 V
O
DC Input Diode Current VO < GND *50 mA
IK
DC Output Diode Current *50 mA
DC Output Sink Current $50 mA
DC Supply Current per Supply Pin $100 mA
DC Ground per Supply Pin $100 mA
Storage Temperature Range *65 to )150 °C
Lead Temperature, 1 mm from Case for 10 Seconds 260 °C
L
Junction Temperature Under Bias )150 °C
J
Thermal Resistance SOT−353
JA
Power Dissipation in Still Air at 85°C SOT−353
D
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
R
SOT−553
SOT−553
350
360
150
180
Class IC
Machine Model (Note 4)
Charged Device Model (Note 5)
Class A
N/A
Latchup Performance Above VCC and Below GND at 85°C (Note 6) $500 mA
°C/W
mW
V
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
V
V
OUT
T
tr, t
DC Supply Voltage Operations Only
CC
DC Input Voltage 0 5.5 V
IN
Data Retention
1.65
1.5
DC Output Voltage 0 5.5 V
Operating Temperature Range *40 )85 °C
A
Input Rise and Fall Time VCC = 2.5 V $0.2 V
f
VCC = 3.0 V $0.3 V
VCC = 5.0 V $0.5 V
0
0
0
5.5
5.5
20
10
5
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2
V
ns/V
NL17SZ16
l
t
l
t
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
Time, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
DC ELECTRICAL CHARACTERISTICS
Symbo
V
IH
V
IL
V
OH
V
OL
I
IN
I
OFF
I
CC
Parameter Condition
High−Level Input Voltage 1.65 to 1.95
Low−Level Input Voltage 1.65 to 1.95
High−Level Output Voltage
VIN = V
or V
IL
IH
IOH = −100 mA
IOH = −3 mA
IOH = −8 mA
IOH = −12 mA
IOH = −16 mA
IOH = −24 mA
IOH = −32 mA
Low−Level Output Voltage
VIN = V
or V
IH
OH
IOL = 100 mA
IOL = 4 mA
IOL = 8 mA
IOL = 12 mA
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
Input Leakage Current VIN = VCC or GND 0 to 5.5 $0.1 $1.0
Power Off−Output Leakage
Current
V
= 5.5 V 0 1 10
OUT
Quiescent Supply Current VIN = VCC or GND 5.5 1 10
V
CC
(V)
2.3 to 5.5
2.3 to 5.5
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
= 130°C
= 120°C
= 110°C
= 100°C
= 90°C
J
J
J
T
T
J
T
T
= 80°C
J
J
T
T
1
1 10 100
NORMALIZED FAILURE RATE
TIME, YEARS
1000
Figure 3. Failure Rate vs. Time Junction Temperature
TA = 255C *405C v TA v 855C
Min Typ Max Min Max
0.75 V
CC
0.7 V
CC
VCC − 0.1
1.29
1.9
2.2
2.4
2.3
3.8
V
CC
1.52
2.1
2.4
2.7
2.5
4.0
0.0
0.08
0.20
0.22
0.28
0.38
0.42
0.25 V
0.3 V
0.1
0.24
0.3
0.4
0.4
0.55
0.55
CC
CC
0.75 V
CC
0.7 V
CC
VCC − 0.1
1.29
1.9
2.2
2.4
2.3
3.8
0.25 V
0.3 V
0.1
0.24
0.3
0.4
0.4
0.55
0.55
CC
CC
Uni
V
V
V
V
mA
mA
mA
AC ELECTRICAL CHARACTERISTICS t
Symbo
t
PLH
t
PHL
Parameter Condition
Propagation Delay
(Figure 4 and 5)
= tF = 3.0 ns
R
RL = 1 MW, C
RL = 500 W, C
= 15 pF
L
= 50 pF
L
V
CC
(V)
1.65
1.8
2.5 $ 0.2
3.3 $ 0.3
5.0 $ 0.5
3.3 $ 0.3
5.0 $ 0.5
TA = 255C *405C v TA v 855C
Min Typ Max Min Max
2.0
2.0
0.8
0.5
0.5
1.5
0.8
5.3
4.4
2.9
2.1
1.8
2.9
2.4
11.4
9.5
6.5
4.5
3.9
5.0
4.3
2.0
2.0
0.8
0.5
0.5
1.5
0.8
12
10
7.0
4.7
4.1
5.2
4.5
Uni
ns
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3
NL17SZ16
CAPACITIVE CHARACTERISTICS
Symbol Parameter Condition Typical Unit
C
C
7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
power consumption; PD = CPD V
Input Capacitance VCC = 5.5 V, VI = 0 V or V
IN
Power Dissipation Capacitance
PD
(Note 7)
2
fin + ICC VCC.
CC
10 MHz, VCC = 3.3 V, VI = 0 V or V
10 MHz, VCC = 5.5 V, VI = 0 V or V
= CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
)
CC(OPR
CC
CC
CC
u4 pF
25
pF
30
tf = 3 ns
INPUT
A and B
OUTPUT Y
90%
90%
t
PHL
50%
10%
50%
50%
Figure 4. Switching Waveform
t
50%
PLH
10%
tf = 3 ns
V
CC
GND
V
OL
V
OH
INPUT
R
L
A 1−MHz square input wave is recommended for
propagation delay tests .
Figure 5. Test Circuit
C
OUTPUT
L
ORDERING INFORMATION
Device Package Shipping
NL17SZ16DFT2 SOT−353/SC70−5/SC−88A
NL17SZ16DFT2G SOT−353/SC70−5/SC−88A
3000/Tape & Reel
(Pb−Free)
NL17SZ16XV5T2 SOT−553*
NL17SZ16XV5T2G SOT−553*
4000/Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*All Devices in Package SOT553 are Inherently Pb−Free.
†
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4
NL17SZ16
PACKAGE DIMENSIONS
SC−88A, SOT−353, SC−70
CASE 419A−02
ISSUE J
A
G
45
D 5 PL
−B−
MM
B0.2 (0.008)
S
12 3
N
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
INCHES
DIMAMIN MAX MIN MAX
B 1.15 1.350.045 0.053
C 0.80 1.100.031 0.043
D 0.10 0.300.004 0.012
G 0.65 BSC0.026 BSC
H −−− 0.10−−−0.004
J 0.10 0.250.004 0.010
K 0.10 0.300.004 0.012
N 0.20 REF0.008 REF
S 2.00 2.200.079 0.087
MILLIMETERS
1.80 2.200.071 0.087
J
C
H
K
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5
D
−X−
45
12 3
e
E
−Y−
b 5 PL
0.08 (0.003) X
M
NL17SZ16
PACKAGE DIMENSIONS
SOT−553, 5 LEAD
CASE 463B−01
ISSUE B
A
Y
SOLDERING FOOTPRINT*
L
H
E
c
0.3
0.0118
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
DIMAMIN NOM MAX MIN
b 0.17 0.22 0.27 0.007
c
D 1.50 1.60 1.70 0.059
E 1.10 1.20 1.30 0.043
e 0.50 BSC
L 0.10 0.20 0.30 0.004
H
E
MILLIMETERS
0.50 0.55 0.60 0.020
0.08 0.13 0.18
1.50 1.60 1.70 0.059 0.063 0.067
0.003 0.005 0.007
INCHES
NOM MAX
0.022 0.024
0.009 0.011
0.063 0.067
0.047 0.051
0.020 BSC
0.008 0.012
0.45
0.0177
1.0
1.35
0.0394
0.0531
0.5
0.5
0.0197
0.0197
mm
ǒ
SCALE 20:1
inches
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NL17SZ16/D
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