ON NCP81172MNTXG Schematic [ru]

NCP81172

2-Phase Synchronous Buck
Controller with Integrated
Gate Drivers and PWM VID
Interface

The NCP81172, a general−purpose two−phase synchronous buck
controller, integrates gate drivers and PWM VID interface in a
QFN−24 package and provides a compact−footprint power
management solution for new generation computing processors. It
receives power save command (PSI) from processors and operates in
1−phase diode emulation mode to obtain high efficiency in light−load
condition. Operating in high switching frequency up to 800 kHz
allows employing small size inductor and capacitors. The part is able
to support all−ceramic−capacitor applications.

Features

 4.5 V to 24 V Input Voltage Range
 Output Voltage up to 2.0 V with PWM VID Interface
 Differential Output Voltage Sense
 Integrated Gate Drivers
 200 kHz ~ 800 kHz Switching Frequency
 Power Saving Interface (PSI)
 Power Good Output
 Programmable Over Current Protection
 Over Voltage Protection
 Under Voltage Protection
 Temperature Sense and Alert Output
 Thermal Shutdown Protection
 QFN−24, 4 x 4 mm, 0.5 mm Pitch Package
 This is a Pb−Free Device

Typical Applications

 GPU and CPU Power
 Graphics Card Applications
 Desktop and Notebook Applications

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1

QFN24

CASE 485L

MARKING DIAGRAM

81172

ALYWG

G

81172 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package

PINOUT

HG2

BST2

PH219

LG220

PVCC21

PGND22

LG123

PH124

BST1

HG1

PGOOD

25

GND

EN

VCC

PSI

TALERT#

VID

131415161718

TSNS

COMP

FBRTN

VREF

REFIN

VIDBUF

654321

12

11

FB

10

9

FS

8

7

 Semiconductor Components Industries, LLC, 2013

April, 2013 − Rev. 1

(Top View)

ORDERING INFORMATION

Device Package Shipping

NCP81172MNTXG QFN24

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

1 Publication Order Number:

4000 / Tape &

†

Reel

NCP81172/D

NCP81172

+5 V

+3.3 V

EN

PSI

VID

PG

TALT

15 VCC

25 GND

3

EN

4

PSI

16

PGOOD

14

TALERT#

5

VID

13 TSNS

8 VREF

7 REFIN

NCP81172

21PVCC

22PGND

2HG1

1BST1

24PH1

23LG1

17HG2

18BST2

19PH2

20LG2

10FBRTN

+5 V

VIN

VOUT

VIN

6 VIDBUF

9 FS

11FB

12COMP

Figure 1. Typical Application Circuit with PWM−VID Interface

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NCP81172

+5 V

+3.3 V

EN

PSI

PG

TALT

15 VCC

25 GND

EN

3

PSI

4

16

PGOOD

14

TALERT#

5

VID

13 TSNS

8 VREF

7 REFIN

NCP81172

21PVCC

22PGND

2HG1

1BST1

24PH1

23LG1

17HG2

18BST2

19PH2

20LG2

10FBRTN

+5 V

VIN

VOUT

VIN

6 VIDBUF

9 FS

11FB

12COMP

Figure 2. Typical Application Circuit without PWM−VID Interface

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NCP81172

15

3

16

13

14

4

9

8

VCC

EN

PGOOD

TSNS

TALERT#

PSI

FS

VREF

UVLO

&

PGOOD

Thermal

Management

PSI

Control

Ramp

Generator

Reference

Voltage

FAULT

RAMP1

PH1

RAMP2

2/1 Phase

PWM

Control

&

Protections

(OVP, UVP, OCP)

PWM1

PWM2

Gate Drive

1

Gate Drive

2

PVCC

PVCC

PVCC

PVCC

BST1

HG1

PH1

LG1

PGND

BST2

HG2

PH2

LG2

21

1

2

24

23

22

18

17

19

20

5

6

7

11

10

25

12

VID

VIDBUF

REFIN

FB

FBRTN

GND

COMP

CS1

Current

CS2

Figure 3. Functional Block Diagram

Sense

PGND

PWM1

PH1

LG1

PWM2

PH2

LG2

GND

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NCP81172

PIN DESCRIPTION

Pin Name Type Description

1 BST1 Analog Power Bootstrap 1. Provides bootstrap voltage for the high−side gate drive of phase 1.

2 HG1 Analog Output High−Side Gate 1. Directly connected with the gate of the high−side power MOSFET

3 EN Logic Input Enable. Logic high enables the device and logic low makes the device in standby

4 PSI Logic Input Power Saving Interface. Logic high enables 2 phase CCM operation, mid level

5 VID Logic Input Voltage ID. Voltage ID input from processor.

6 VIDBUF Analog Output Voltage ID Buffer. VID PWM pulse output from an internal buffer.

7 REFIN Analog Input Reference Input. Reference voltage input for output voltage regulation. The pin is

8 VREF Analog Output Output Reference Voltage. Precise 2 V reference voltage output. A 10 nF ceramic

9 FS Analog Input Frequency Selection. A resistor from this pin to ground programs switching frequency.

10 FBRTN Analog Input Voltage Feedback Return Input. An inverting input of internal error amplifier.

11 FB Analog Input Feedback. An inverting input of internal error amplifier.

12 COMP Analog Output Compensation. Output pin of error amplifier.

13 TSNS Analog Input Temperature Sensing. Temperature sensing input.

14 TALERT# Logic Output Thermal Alert. Open drain output and active low indicates over temperature.

15 VCC Analog Power

16 PGOOD Logic Output Power GOOD. Open−drain output. Provides a logic high valid power good output

17 HG2 Analog Output High−Side Gate 2. Connected with the gate of the high−side power MOSFET in

18 BST2 Analog Power Bootstrap 2. Provides bootstrap voltage for the high−side gate drive of phase 2.

19 PH2 Analog Input Phase Node 2. Connected to interconnection between high−side MOSFET and

20 LG2 Analog Output Low−Side Gate 2. Connected with the gate of the low−side power MOSFET in

21 PVCC Analog Power Voltage Supply of Gate Drivers. Power supply input pin of internal gate drivers.

22 PGND Analog Ground Power Ground. Power ground of internal gate drivers. Must be connected to the

23 LG1 Analog Output Low−Side Gate 1. Connected with the gate of the low−side power MOSFET in

24 PH1 Analog Input Phase Node 1. Connected to interconnection between high−side MOSFET and

25 THERM/GND Analog Ground Thermal Pad and Analog Ground. Ground of internal control circuits. Must be

A 0.1 mF ~ 1 mF ceramic capacitor is required from this pin to PH1 (pin 24).

of phase 1.

mode.

enables 1−phase CCM operation, and logic low enables 1−phase CCM/DCM
operation.

connected to a non−inverting input of internal error amplifier.

capacitor is required from this pin to GND.

Voltage Supply of Controller. Power supply input pin of control circuits. A 1 mF or larger
ceramic capacitor bypasses this input to GND. This capacitor should be placed as
close as possible to this pin.

signal, indicating the regulator’s output is in regulation window.

phase 2.

A 0.1 mF ~ 1 mF ceramic capacitor is required from this pin to PH2 (pin 19).

low−side MOSFET in phase 2.

phase 2.

A 4.7 mF or larger ceramic capacitor bypasses this input to ground. This capacitor
should be placed as close as possible to this pin.

system ground.

phase 1.
A resistor may be applied between this pin and GND to program OCP threshold.

low−side MOSFET in phase 1.

connected to the system ground.

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