ON NCP6132AMNR2G, NCP6132BMNR2G Schematics

NCP6132A, NCP6132B

Dual Output 3 Phase & 2
Phase Controller with
Single SVID Interface for
Desktop and Notebook CPU
Applications

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The NCP6132A/NCP6132B dual output three plus two phase buck
solution is optimized for Intel IMVP−7 and VR12 compatible CPUs.
The controller combines true differential voltage sensing, differential
inductor DCR current sensing, input voltage feed−forward, and
adaptive voltage positioning to provide accurately regulated power for
both Desktop and Notebook applications. The control system is based
on Dual−Edge pulse−width modulation (PWM) combined with DCR
current sensing providing the fastest initial response to dynamic load
events and reduced system cost. It also sheds to single phase during
light load operation and can auto frequency scale in light load while
maintaining excellent transient performance.

There are three internal MOSFET drivers inside the chip. One of
these three integrated driver can be configured either to drive core
phase or aux phase. NCP6132A and NCP6132B have almost same
structure except that NCP6132A has two integrated drivers for the
core rail and one integrated driver for auxiliary rail, while the
NCP6132B has all three integrated drivers for the core rail.

Features

• Meets Intel’s VR12/IMVP7 Specifications

• Three Phase CPU Voltage Regulator, and Two Phase Auxiliary

Voltage Regulator, with Three Internal MOSFET Drivers in Total

• Current Mode Dual Edge Modulation for Fastest Initial Response to

Transient Loading

• Dual High Performance Operational Error Amplifier

• One Digital Soft Start Ramp for Both Rails

• Dynamic Reference Injection

• Accurate Total Summing Current Amplifier

• DAC with Droop Feed−forward Injection

• Dual High Impedance Differential Voltage and Total

Current Sense Amplifiers

• Phase−to−Phase Dynamic Current Balancing

• “Lossless” DCR Current Sensing for Current Balancing

• Summed Thermally Compensated Inductor Current

Sensing for Droop

• Power Saving Phase Shedding

• Start Up into Pre−charged Output Voltage

• Adaptive Voltage Positioning (AVP)

• Vin Feed Forward Ramp Slope

• Pin Programming for Internal SVID Parameters

• Over Voltage Protection (OVP) & Under Voltage

Protection (UVP)

• Over Current Protection (OCP)

• Dual Power Good Output with Internal Delays

• Pb−free and Halide−free Packages are Available

• True Differential Current Balancing Sense Amplifiers

for Each Phase

• Switching Frequency Range of 200 kHz − 600 kHz

Applications

• Desktop & Notebook Processors

MARKING
DIAGRAM

1

160

QFN60

CASE 485BB

x = A or B
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package

ORDERING INFORMATION

Device Package Shipping

NCP6132AMNR2G

NCP6132BMNR2G

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

QFN60

(Pb−Free)

NCP6132x

AWLYYWWG

2500/Tape

& Reel

†

© Semiconductor Components Industries, LLC, 2012

October, 2012 − Rev. 1

1 Publication Order Number:

NCP6132A/D

NCP6132A, NCP6132B

EN

GND

VCC

VDDBP

TSNS

TSNSA

VRHOT#

SDIO

SCLK

ALERT#

VBOOT

VSP

VSN

DROOP

DIFF

COMP

TRBST#

CSSUM

CSREF

CSCOMP

ILIM

IOUT

CSP1

CSP2

CSP3

ENABLE

UVLO & EN

THERMAL
MONITOR

ENABLE

SVID

INTERFACCE

DAC

GND

DIFFAMP

CSREF

1.3 V

FB

ERROR

−

AMP

ENABLE

VSPA

VSNA

DACA

DROOPA

DATA

REGISTERS

TRBST

AUX VR READY

COMPARATOR

DAC

AUX

DAC

VSPA

VSNA

VSP

VSN

ADC

DAC

AUX
DAC

AUX OVP

OVP

ENABLE

MUX

OVPA

OVP

VSP

VSN

DAC

DROOP

VR READY

COMPARATOR

VSPA − VSNA

VSP − VSN

TSNS
TSNSA
IMON
IMONA
IMAX
IMAXA

IOUTA

ILIMA

AUX

DIFFAMP

AUX

CS

AMP

AUX
DAC

GND

CSREFA

1.3 V

−

+

−

VRDYA

VRDY

VSPA

VSNA

DROOPA

DIFFA

CSSUMA

CSREFA

CSCOMPA

ILIMA

IOUTA

FBA

DETECT

CSREF

+

1.3 V

−

+

IOUT

ILIM

MAIN

CURRENT

BALANCE

CS

AMP

ENABLE

CORE PHASE

GENERATOR

COMP

OVP

RAMP1

RAMP2

RAMP3

ENABLE

RAMP

GENERATORS

TRBSTA
DETECT

RAMPA2

RAMPA1

AUX

ERROR

AMP

AUX

PWM

GENERATOR

+

AUX

CURRENT

BALANCE

ENABLE

COMPA

OVPA

1.3 V

COMPA

TRBSTA#

CSP1A

CSP2A

CSREFA

BSTA

HGA

SWA

PVCC

LGA

PVCC

LG1

PGND

BST1

HG1

SW1

PGND

PVCC

LG2

Figure 1. Block Diagram

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BST2

PGND

PWMA

HG2

SW2

PWM

VRMP

ROSC

DRVEN

2

VCC

VDDBP

VRDYA

EN

SDIO

ALERT#

SCLK

VBOOT

ROSC

VRMP

VRHOT#

VRDY

VSN

VSP

DIFF

NCP6132A, NCP6132B

FBA

DIFFA

VSNA

VSPA

60

1

15

16

COMPA

TRBSTA#

NCP6132A/NCP6132B

ILIMA

IOUTA

Tab: GND

DROOPA

CSSUMA

CSREFA

CSCOMPA

CSP2A

CSP1A

TSNSA

46

PWMA

45

BSTA

HGA

SWA

LGA

BST2

HG2

SW2

LG2

PVCC

PGND

LG1

SW1

HG1

31

BST1

30

FB

TRBST#

ILIM

IOUT

COMP

DROOP

CSREF

CSSUM

CSCOMP

CSP3

CSP1

CSP2

PWM

TSNS

DRVEN

Figure 2. QFN60 Pin Diagram

Table 1. QFN60 PIN LIST DESCRIPTION

Pin
No.

1 VCC Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground.

2 VDDBP

3 VRDYA Open drain output. High indicates that the aux output is regulating.

4 EN Logic input. Logic high enables both outputs and logic low disables both outputs.

5 SDIO Serial VID data interface.

6 ALERT# Serial VID ALERT#.

7 SCLK Serial VID clock.

8 VBOOT A resistor to GND on this pin sets the Core and Aux Boot−up Voltage

9 ROSC A resistance from this pin to ground programs the oscillator frequency. This pin supplies a trimmed

10 VRMP Feed−forward input of Vin for the ramp slope compensation. The current fed into this pin is used to

11 VRHOT# Thermal logic output for over temperature.

12 VRDY Open drain output. High indicates that the core output is regulating.

13 VSN Inverting input to the core differential remote sense amplifier.

14 VSP Non−inverting input to the core differential remote sense amplifier.

15 DIFF Output of the core differential remote sense amplifier.

16 TRBST# Compensation pin for the load transient boost.

17 FB Error amplifier voltage feedback for core output

18 COMP Output of the error amplifier and the inverting inputs of the PWM comparators for the core output.

19 IOUT Total output current monitor for core output. Short it to GND if IMON function is not needed.

20 ILIM Over current shutdown threshold setting for core output. Resistor to CSCOMP to set threshold.

21 DROOP Used to program droop function for core output. It’s connected to the resistor divider placed between

22 CSCOMP Output of total current sense amplifier for core output.

Symbol Description

Digital Logic power. Connect this pin to VCC with 10 W. Connect 0.1 mF capacitor from this pin to
ground

output voltage of 2 V.

control of the ramp of PWM slope

CSCOMP and CSREF summing node.

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NCP6132A, NCP6132B

Table 1. QFN60 PIN LIST DESCRIPTION

Pin
No.

23 CSSUM Inverting input of total current sense amplifier for core output.

24 CSREF Total output current sense amplifier reference voltage input. And inverting input to core current bal-

ance sense amplifiers.

25 CSP3 Non−inverting input to current balance sense amplifier for phase 3

26 CSP2 Non−inverting input to current balance sense amplifier for phase 2

27 CSP1 Non−inverting input to current balance sense amplifier for phase 1

28 TSNS Temp Sense input for the core converter.

29 DRVEN Bidirectional gate driver enable for external drivers for both core and aux rails. It should be left floating

if unused.

30 PWM Phase 3 PWM output. A resistor to ground on this pin programs IMAX.

31 BST1 High−Side Bootstrap supply for phase 1

32 HG1 High−Side gate drive output for phase 1

33 SW1 Current return for high−side gate drive for phase 1

34 LG1 Low−Side gate drive output for phase 1

35 PGND Power ground for gate drivers

36 PVCC Power Supply for gate drivers

37 LG2 Low−Side gate drive output for phase 2

38 SW2 Current return for high−side gate drive for phase 2

39 HG2 High−Side gate drive output for phase 2

40 BST2 High−Side Bootstrap supply for phase 2

41 LGA Low−Side gate drive output for aux phase 1

42 SWA Current return for high−side gate drive for aux phase 1

43 HGA High−Side gate drive output for aux phase 1

44 BSTA High−Side Bootstrap supply for aux phase 1

45 PWMA Aux Phase 2 PWM output. A resistor to ground on this pin programs IMAXA.

46 TSNSA Temp sense for the aux converter

47 CSP1A Non−inverting input to aux current balance sense amplifier for phase 1

48 CSP2A Non−inverting input to aux current balance sense amplifier for phase 2

49 CSREFA Total output current sense amplifier reference voltage input for aux. Inverting input to aux current

balance sense amplifier for phase 1 and 2

50 CSSUMA Inverting input of total current sense amplifier for aux output

51 CSCOMPA Output of total current sense amplifier for aux output

52 DROOPA Used to program droop function for aux output. It’s connected to the resistor divider placed between

CSCOMPA and CSREFA.

53 ILMA Over current shutdown threshold setting for aux output. Resistor to CSCOMPA to set threshold.

54 IOUTA Total output current monitor for aux output. Short to GND if IMON function is not needed.

55 COMPA Output of aux error amplifier and inverting input of PWM comparator for aux output

56 FBA Error amplifier voltage feedback for aux output

57 TRBSTA# Compensation pin for load transient boost

58 DIFFA Output of the aux differential remote sense amplifier

59 VSPA Non−inverting input to aux differential remote sense amplifier

60 VSNA Inverting input to aux differential remote sense amplifier

61 GND Analog ground

DescriptionSymbol

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NCP6132A, NCP6132B

ABSOLUTE MAXIMUM RATINGS

Table 2. ELECTRICAL INFORMATION

Pin Symbol V

MAX

COMP, COMPA VCC + 0.3 V −0.3 V 2 mA 2 mA

CSCOMP, CSCOMPA VCC + 0.3 V −0.3 V 2 mA 2 mA

VSN, VSNA GND + 300 mV GND – 300 mV 1 mA 1 mA

DIFF, DIFFA VCC + 0.3 V −0.3 V 2 mA 2 mA

VRDY, VRDYA VCC + 0.3 V −0.3 V N/A 2 mA

VDDPB, VCC, PVCC 6.5 V −0.3 V N/A N/A

ROSC VCC + 0.3 V −0.3 V 1 mA N/A

IOUT, IOUTA Output TBD −0.3 V

VRMP +25 V −0.3 V

SW1, SW2, SWA 28 V −5 V

BST1, BST2, BSTA 34 V wrt/ GND

6.5 V wrt/ SW

LG1, LG2, LGA VCC + 0.3 V −0.3 V

HG1, HG2, HGA BST + 0.3 V −0.3 V wrt/ SW

−2 V ≤ 200 ns wrt/ SW

All Other Pins VCC + 0.3 V −0.3 V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*All signals referenced to GND unless noted otherwise.

V

MIN

−10 V ≤ 200 ns

−0.3 V wrt/ SW

−5 V ≤ 200 ns

I

SOURCE

I

SINK

Table 3. THERMAL INFORMATION

Parameters Symbol Typical Units

Thermal Characteristic

QFN Package (Note 1)

Operating Junction Temperature Range (Note 2) T

Operating Ambient Temperature Range −10 to +100

Maximum Storage Temperature Range T

Moisture Sensitivity Level

QFN Package

*The maximum package power dissipation must be observed.

1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM

2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM

R

JA

J

STG

−10 to +125

−40 to +150

MSL 1

31

_C/W

_C

_C

_C

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NCP6132A, NCP6132B

Table 4. NCP6132A/NCP6132B (3+2) ELECTRICAL CHARACTERISTICS

Unless otherwise stated: −10°C < TA < 100°C; VCC = 5.0 V; C

Parameter

ERROR AMPLIFIER

Input Bias Current −400 400 nA

Open Loop DC Gain CL = 20 pF to GND,

Open Loop Unity Gain Bandwidth CL = 20 pF to GND,

Slew Rate

Maximum Output Voltage I

Minimum Output Voltage I

DIFFERENTIAL SUMMING AMPLIFIER

Input Bias Current −400 − 400 nA

VSP Input Voltage Range −0.3 − 3.0 V

VSN Input Voltage Range −0.3 − 0.3 V

−3 dB Bandwidth CL = 20 pF to GND,

Closed Loop DC gain VS to DIFF VS+ to VS− = 0.5 to 1.3 V 1.0 V/V

Droop Accuracy CSREF − DROOP = 80 mV

Maximum Output Voltage I

Minimum Output Voltage I

3. Guaranteed by design/characterization, not in production test

4. Guaranteed by characterization

= 0.1 mF

VCC

Test Conditions Min Typ Max Units

80 dB

RL = 10 kW to GND

55 MHz

RL = 10 kW to GND

DVin = 100 mV, G = −10 V/V,

DV

= 1.5 V – 2.5 V,

out

CL = 20 pF to GND,

20

DC Load = 10k to GND

= 2.0 mA 3.5 − − V

SOURCE

= 2.0 mA − − 1 V

SINK

12 MHz

RL = 10 kW to GND

DAC = 0.8 V to 1.2 V

−10°C ~ 100°C

−10°C ~ 85°C

= 2 mA 3.0 − − V

SOURCE

= 2 mA − − 0.5 V

SINK

78.5
79

81.5
81

V/ms

mV

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NCP6132A, NCP6132B

Table 5. ELECTRICAL CHARACTERISTICS Unless otherwise stated: −10°C < T

< 100°C; VCC = 5.0 V; C

A

VCC

= 0.1 mF

Parameter Test Conditions Min Typ Max Units

CURRENT SUMMING AMPLIFIER

Offset Voltage (Vos) −300 300

mV

Input Bias Current (CSSUM) CSSUM = CSREF = 1 V −7.5 7.5 nA

Open Loop Gain 80 dB

Current Sense Unity Gain Bandwidth CL = 20 pF to GND,

10 MHz

RL = 10 kW to GND

Maximum CSCOMP (A) Output Voltage I

Minimum CSCOMP(A) Output Voltage

= 2 mA 3.5 − − V

source

I

sink

= 500 mA

− − 0.1 V

CURRENT BALANCE AMPLIFIER

Input Bias Current CSPx = CSREF = 1.2 V −50 − 50 nA

Common Mode Input Voltage Range CSPx = CSREF 0 − 2.0 V

Differential Mode Input Voltage Range CSREF = 1.2 V −100 − 100 mV

Input Offset Voltage Matching CSPx = CSREF = 1.2 V,

−1.5 − 1.5 mV

Measured from the average

Current Sense Amplifier Gain 0 V < CSPx − CSREF < 0.1 V,

−10°C ~ 85°C

−10°C ~ 100°C

5.7

5.5

6.0

6.0

6.3

6.3

V/V

Multiphase Current Sense Gain Matching CSREF = CSP = 10 mV to 30 mV −3 3 %

−3 dB Bandwidth 8 MHz

BIAS SUPPLY

VCC Quiescent Current EN = high 20 27 35 mA

EN = low 10 70

mA

UVLO Threshold VCC rising 4.5 V

VCC falling 4.0 V

VCC UVLO Hysteresis 200 mV

VDDBP Quiescent Current EN = Low

EN = High

0.8

12.0

mA

DAC SLEW RATE

Soft Start Slew Rate 2.33

Slew Rate Slow 3.5

Slew Rate Fast 13.5

AUX Soft Start Slew Rate 2.33

AUX Slew Rate Slow 3.5

AUX Slew Rate Fast 13.5

mv/ms

mv/ms

mv/ms

mv/ms

mv/ms

mv/ms

ENABLE INPUT

Enable High Input Leakage Current External 1k pull−up to 3.3 V − 1.0

Upper Threshold V

Lower Threshold V

Total Hysteresis V

UPPER

UPPER

LOWER

– V

LOWER

Enable Delay Time Measure time from Enable transitioning HI

to when DRON goes high, V

is not 0 V

boot

0.8 V

0.35 V

95 mV

5.0 ms

mA

3. Guaranteed by design/characterization, not in production test

4. Guaranteed by characterization

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NCP6132A, NCP6132B

Table 5. ELECTRICAL CHARACTERISTICS Unless otherwise stated: −10°C < T

< 100°C; VCC = 5.0 V; C

A

VCC

= 0.1 mF

Parameter UnitsMaxTypMinTest Conditions

DRVEN

Output High Voltage

Output Low Voltage

Rise Time

Fall Time − 2 − ns

Sourcing 500 mA

Sinking 500 mA

CL (PCB) = 20 pF,

DVo = 10% to 90%

Internal Pull Down Resistance EN = Low 70

3.5 V

0.1 V

− 255 − ns

kW

IOUT / IOUTA OUTPUT

Maximum Output Voltage R

Input Referred Offset Voltage I

Output Source Current

Current Gain (IOUT

R

I

limit

CURRENT

= 8.0 kW , Temp range: 0°C to 60°C

OUT

= 5k 2.5 V

lim

to CSREF −2.5 2.5 mV

limit

sink current = 80 mA

) / (ILIM

CURRENT

), R

ILIM

=

9.5 10 10.5

840

mA

OSCILLATOR

Switching Frequency Range 200 − 800 kHz

Switching Frequency Accuracy 200 kHz < Fsw < 800 kHz −10 − 10 %

3 Phase Operation

Rosc Output Voltage

R

osc

R

osc

= 67.4 kW

= 67.4 kW

360 400 440 kHz

1.95 2.00 2.05 V

OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)

Over Voltage Threshold During Soft−Start &

1.7 1.75 1.8 V

DVID

Over Voltage Threshold Above DAC VSP(A) Rising 225 250 275 mV

Over Voltage Delay VSP(A) rising to PWMx low 50 ns

Under Voltage Threshold Below DAC−DROOP VSP(A) Falling 350 400 450 mV

Under−voltage Hysteresis VSP(A) Rising 25 mV

Under−voltage Delay 5

VR12 DAC

System Voltage Accuracy −105C ~ 855C

1.0 V ≤ DAC < 1.52 V

0.8 V< DAC < 0.995 V

0.5 V < DAC < 0.795 V

0.25 V < DAC < 0.495 V

−0.5

−5

−8

−8

+0.5

+5
+8
+8

mV
mV
mV

−105C ~ 1005C

1.0 V ≤ DAC < 1.52 V

0.8 V< DAC < 0.995 V

0.5 V < DAC < 0.795 V

0.25 V < DAC < 0.495 V

Droop Feed−Forward Current Measure on DROOP pin 60 66 72

1

−12

−12

−12

1
+12
+12
+12

mV
mV
mV

mA

Droop Feed−Forward Pulse On−Time 0.16

OVERCURRENT PROTECTION

ILIM Threshold Current
(OCP shutdown after 50 ms delay)

Aux/Core Multiphase, PS0, R

Aux/Core 1−phase, PS1/2/3, R

Aux 2−phase, PS1, R

Core 2−phase, PS1, R

lim

lim

Aux/Core 2−phase, PS2/3, R

Core 3−phase, PS1/2/3, R

= 20 kW

lim

= 20 kW

lim

= 20 kW

= 20 kW

= 20 kW

lim

= 20 kW

lim

9.0 10 11.0

10

10

6.5

6.5

4.0

mA

mA

mA

mA

mA

mA

3. Guaranteed by design/characterization, not in production test

4. Guaranteed by characterization

ms

%

%

ms

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NCP6132A, NCP6132B

Table 5. ELECTRICAL CHARACTERISTICS Unless otherwise stated: −10°C < T

< 100°C; VCC = 5.0 V; C

A

VCC

= 0.1 mF

Parameter UnitsMaxTypMinTest Conditions

OVERCURRENT PROTECTION

ILIM Threshold Current
(immediate OCP shutdown)

Aux/Core Multiphase, PS0, R

Aux/Core 1−phase, PS1/2/3, R

Aux 2−phase, PS1, R

Core 2−phase, PS1, R

lim

lim

Aux/Core 2−phase, PS2/3, R

Core 3−phase, PS1/2/3, R

= 20 kW

lim

= 20 kW

lim

= 20 kW

= 20 kW

= 20 kW

lim

= 20 kW

lim

13.5 15 16.5

15

15

10

10

6

mA

mA

mA

mA

mA

mA

MODULATORS (PWM COMPARATORS) FOR CORE & AUX

Minimum Pulse Width Fsw = 350 kHz 60 ns

0% Duty Cycle COMP voltage when the PWM outputs

1.3 − V

remain LO

100% Duty Cycle COMP voltage when the PWM outputs

remain HI V

RMP

= 12.0 V

− 2.5 − V

PWM Ramp Duty Cycle Matching COMP = 2 V, PWM Ton matching −20 20 %

PWM Phase Angle Error Between adjacent phases −25 25 deg

Ramp Feed−forward Voltage range 5 22 V

TRBST#

TRBST/COMP offset TRBST Starts Sinking Current 350 mV

TRBST Sink Capability 500

mA

TRBSTA#

TRBSTA/COMPA offset TRBSTA Starts Sinking Current 350 mV

TRBSTA Sink Capability 500

mA

VRHOT#

Output Low Voltage I_VRHOT = −4 mA 0.3 V

Output Leakage Current High Impedance State −1.0 − 1.0

mA

TSNS/TSNSA

Alert# Assert Threshold 515 mV

Alert# De−assert Threshold 533 mV

VRHOT# Assert Threshold 496 mV

VRHOT# Rising Threshold 515 mV

TSNS Bias Current 115 120 125

mA

ADC

Voltage Range 0 2 V

Total Unadjusted Error (TUE) −1 +1 %

Differential Nonlinearity (DNL) 8−bit 1 LSB

Power Supply Sensitivity +/−1 %

Conversion Time 30

Round Robin 90

ms

ms

VRDY, VRDYA (Power Good) OUTPUT

Output Low Saturation Voltage I

= 4 mA − − 0.3 V

VRDY(A)

3. Guaranteed by design/characterization, not in production test

4. Guaranteed by characterization

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NCP6132A, NCP6132B

Table 5. ELECTRICAL CHARACTERISTICS Unless otherwise stated: −10°C < T

< 100°C; VCC = 5.0 V; C

A

VCC

= 0.1 mF

Parameter UnitsMaxTypMinTest Conditions

VRDY, VRDYA (Power Good) OUTPUT

Rise Time

Fall Time

Output Voltage at Power−up

External pull−up of 1 kW to 3.3 V,

C

= 45 pF, DVo = 10% to 90%

TOT

External pull−up of 1 kW to 3.3 V,

C

= 45 pF, DVo = 90% to 10%

TOT

VRDY, VRDYA pulled up to 5 V via 2 kW

− 100 ns

10 ns

− − 1.0 V

Output Leakage Current When High VRDY & VRDYA = 5.0 V −1.0 − 1.0

VRDY Delay (rising) DAC = TARGET to VRDY 500

VRDY Delay (falling) From OCP or OVP − 5 −

PWM, PWMA OUTPUTS

Output High Voltage

Sourcing 500 mA

VCC –

− − V

1.0 V

Output Mid Voltage No Load, SetPS = 02 1.3 2.0 2.7 V

Output Low Voltage

Rise and Fall Time

Sinking 500 mA

CL (PCB) = 50 pF, DVo = GND to VCC

− − 0.7 V

− 10 ns

Tri−State Output Leakage Gx = 2.0 V, x = 1−4, EN = Low −1.0 − 1.0

PHASE DETECTION

CSP1A, CSP2A, CSP2, CSP3

4.2 V

Pin Threshold Voltage

SCLK, SDIO

V

V

V

V

R

IL

IH

HYS

OH

ON

Input Low Voltage 0.45 V

Input High Voltage 0.65 V

Hysteresis Voltage 50 mV

Output High Voltage 1.05 V

Buffer On Resistance

4 13

(data line, ALERT#, and VRHOT#)

Leakage Current −100 100

Pad Capacitance (Note 3) 4.0 pF

VR clock to data delay (Tco) (Note 3) 4 8.3 ns

Setup time (Tsu) (Note 3) 7 ns

Hold time (Thld) (Note 3) 14 ns

HIGH−SIDE MOSFET DRIVER

Pull−up Resistance, Sourcing Current (Note 4) BST = PVCC 1.2 2.0

High Side Driver Sourcing Current BST = PVCC 4.17 A

Pull−down Resistance, Sinking Current

BST = PVCC 0.8 2.0

(Note 4)

High Side Driver Sinking Current BST = PVCC 6.25 A

HG1, HG2, HGA Rise Time VCC = 5 V, 3 nF load, BST − SW = 5 V 6 16 30 ns

HG1, HG2, HGA Fall Time VCC = 5 V, 3 nF load, BST − SW = 5 V 6 11 30 ns

HG1, HG2, HGA Turn−On Propagation Delay
tpdh

DRVH

C

= 3 nF 16 40 47 ns

LOAD

SW1, SW2, SWA Pull−Down Resistance SW to PGND 2

HG1, HG2, HGA Pull−Down Resistance HG to SWBST−SW = 0 V 260

3. Guaranteed by design/characterization, not in production test

4. Guaranteed by characterization

mA

ms

ms

mA

W

mA

W

W

kW

kW

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