ON NCP5901DR2G, NCP5901MNTBG Schematic [ru]

NCP5901

VR12 Compatible
Synchronous Buck MOSFET
Drivers

The NCP5901 is a high performance dual MOSFET gate driver
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. It can drive up to 3 nF
load with a 25 ns propagation delay and 20 ns transition time.

Adaptive anti−cross−conduction and power saving operation
circuit can provide a low switching loss and high efficiency solution
for notebook and desktop systems. Bidirectional EN pin can provide
a fault signal to controller when the gate driver fault detect under
OVP, UVLO occur. Also, an under−voltage lockout function
guarantees the outputs are low when supply voltage is low.

Features

• Faster Rise and Fall Times

• Adaptive Anti−Cross−Conduction Circuit

• Pre OV function

• ZCD Detect

• Floating Top Driver Accommodates Boost Voltages of up to 35 V

• Output Disable Control Turns Off Both MOSFETs

• Under−voltage Lockout

• Power Saving Operation Under Light Load Conditions

• Direct Interface to NCP6151 and Other Compatible PWM

Controllers

• Thermally Enhanced Package

• These are Pb−Free Devices

Typical Applications

• Power Solutions for Desktop Systems

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8

1

SOIC−8 NB

D SUFFIX

CASE 751

MARKING DIAGRAMS

8

N5901

ALYW

1

N5901 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package

1

AJMG

AJ = Specific Device Code
M = Date Code
G = Pb−Free Device

DFN8

MN SUFFIX

CASE 506AA

G

G

1

© Semiconductor Components Industries, LLC, 2013

June, 2013 − Rev. 2

ORDERING INFORMATION

Device Package Shipping

NCP5901MNTBG DFN8

(Pb−Free)

NCP5901DR2G SOIC−8

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

1 Publication Order Number:

3000 / Tape & Reel

2500 / Tape & Reel

†

NCP5901/D

NCP5901

VCC

PWM

BST

1

PWM

EN

VCC

(Top View)

Figure 1. Pin Diagram

Logic

FLAG

9

DRVH

SW

GND

DRVL

Anti−Cross

Conduction

BST

DRVH

SW

VCC

DRVL

EN

Fault

UVLO

Pre−OV

ZCD

Detection

Figure 2. Block Diagram

Table 1. Pin Descriptions

Pin No. Symbol Description

1 BST Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin

2 PWM Control input. The PWM signal has three distinctive states: Low = Low Side FET Enabled, Mid = Diode

3 EN Logic input. A logic high to enable the part and a logic low to disable the part.

4 VCC Power supply input. Connect a bypass capacitor (0.1 mF) from this pin to ground.

5 DRVL Low side gate drive output. Connect to the gate of low side MOSFET.

6 GND Bias and reference ground. All signals are referenced to this node (QFN Flag).

7 SW Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET.

8 DRVH High side gate drive output. Connect to the gate of high side MOSFET.

9 FLAG Thermal flag. There is no electrical connection to the IC. Connect to ground plane.

and the SW pin.

Emulation Enabled, High = High Side FET Enabled.

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2

12V_POWER

TP4

PWM

DRON

R1

1.02

C5

1uF

CR1
MMSD4148

R143

0.0

R164

0.0

NCP5901

BST

PWM

EN

VCC

PAD

HG

SW

GND

LG

C4

0.027uF

TP3

VREG_SW1_HG

VREG_SW1_OUT

VREG_SW1_LG

TP8

NCP5901

R142

0.0

TP6

TP7

Q9 Q10
NTMFS4851N NTMFS4851N

Figure 3. Application Circuit

TP2

TP1

TP5

Q1
NTMFS4821N

R3

2.2

C6
2700pF

C1 C2 C3 CE9

4.7uF 4.7uF 4.7uF 390uF

L

+

VCCP

235nH

JP13_ETCH

JP14_ETCH

CSN11

CSP11

Table 2. ABSOLUTE MAXIMUM RATINGS

Pin Symbol Pin Name V

MAX

VCC Main Supply Voltage Input 15 V −0.3 V

BST Bootstrap Supply Voltage 35 V wrt/ GND

40 V ≤ 50 ns wrt/ GND

15 V wrt/ SW

SW Switching Node

(Bootstrap Supply Return)

35 V

40 V ≤ 50 ns

DRVH High Side Driver Output BST+0.3 V −0.3 V wrt/SW

−2 V (<200 ns) wrt/SW

DRVL Low Side Driver Output VCC+0.3 V −0.3 V DC

PWM DRVH and DRVL Control Input 6.5 V −0.3 V

EN Enable Pin 6.5 V −0.3 V

GND Ground 0 V 0 V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

V

MIN

−0.3 V wrt/SW

−5 V

−10 V (200 ns)

−5 V (<200 ns)

Table 3. THERMAL INFORMATION (All signals referenced to AGND unless noted otherwise)

Symbol Parameter Value Unit

R

q

JA

T

J

T

A

T

STG

MSL Moisture Sensitivity Level SOIC Package

* The maximum package power dissipation must be observed.

1. I in2 Cu, 1 oz thickness.

2. Operation at −40°C to −10°C guaranteed by design, not production tested.

Thermal Characteristic SOIC Package (Note 1)

DFN Package (Note 1)

123

74

°C/W

Operating Junction Temperature Range (Note 2) 0 to 150 °C

Operating Ambient Temperature Range −10 to +125 °C

Maximum Storage Temperature Range −55 to +150 °C

1

DFN Package

1

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3

NCP5901

Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: −10°C < T

< +125°C; 4.5 V < VCC < 13.2 V,

A

4.5 V < BST−SWN < 13.2 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V)

Parameter Test Conditions Min. Typ. Max. Units

SUPPLY VOLTAGE

VCC Operation Voltage

4.5 13.2 V

Power ON Reset Threshold 2.75 3.2 V

UNDERVOLTAGE LOCKOUT

VCC Start Threshold 3.8 4.35 4.5 V

VCC UVLO Hysteresis 150 200 250 mV

Output Overvoltage Trip Threshold at

Power Startup time, VCC > POR 2.1 2.25 2.4 V

Startup

SUPPLY CURRENT

Normal Mode Icc + Ibst, EN = 5 V, PWM = OSC, Fsw = 100 KHz,

12.2 mA

Cload = 3 nF for DRVH, 3 nF for DRVL

Standby Current Icc + Ibst, EN = GND 0.5 1.9 mA

Standby Current ICC + I

No loading on DRVH & DRVL

Standby Current ICC + I

No loading on DRVH & DRVL

, EN = HIGH, PWM = LOW,

BST

, EN = HIGH, PWM = HIGH,

BST

2.1 mA

2.2 mA

PWM INPUT

PWM Input High 3.4 V

PWM Mid−State 1.3 2.7 V

PWM Input Low 0.7 V

ZCD Blanking Timer 250 ns

HIGH SIDE DRIVER (VCC = 12 V)

Output Impedance, Sourcing Current VBST − VSW = 12 V 2.0 3.5 W

Output Impedance, Sinking Current VBST − VSW = 12 V 1.0 2.0 W

DRVH Rise Time trDRVH V

DRVH Fall Time tfDRVH V

DRVH Turn−Off Propagation Delay
tpdh

DRVH

DRVH Turn−On Propagation Delay
tpdl

DRVH

= 12 V, 3 nF load, VBST−VSW = 12 V 16 30 ns

VCC

= 12 V, 3 nF load, VBST−VSW = 12 V 11 25 ns

VCC

C

= 3 nF 8.0 30 ns

LOAD

C

= 3 nF 30 ns

LOAD

SW Pull Down Resistance SW to PGND 45 kW

DRVH Pull Down Resistance DRVH to SW, BST−SW = 0 V 45 kW

HIGH SIDE DRIVER (VCC = 5 V)

Output Impedance, Sourcing Current VBST − VSW = 5 V 4.5 W

Output Impedance, Sinking Current VBST − VSW = 5 V 2.9 W

DRVH Rise Time tr

DRVH Fall Time tf

DRVH

DRVH

DRVH Turn−Off Propagation Delay
tpdh

DRVH

DRVH Turn−On Propagation Delay
tpdl

DRVH

V

= 5 V, 3 nF load, VBST − VSW = 5 V 30 ns

VCC

V

= 5 V, 3 nF load, VBST − VSW = 5 V 27 ns

VCC

C

= 3 nF 20 ns

LOAD

C

= 3 nF 27 ns

LOAD

SW Pull Down Resistance SW to PGND 45 kW

DRVH Pull Down Resistance DRVH to SW, BST−SW = 0 V 45 kW

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4

NCP5901

Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: −10°C < T

< +125°C; 4.5 V < VCC < 13.2 V,

A

4.5 V < BST−SWN < 13.2 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V)

Parameter UnitsMax.Typ.Min.Test Conditions

LOW SIDE DRIVER (VCC = 12 V)

Output Impedance, Sourcing Current 2.0 3.5 W

Output Impedance, Sinking Current 0.8 1.8 W

DRVL Rise Time tr

DRVL Fall Time tf

DRVL

DRVL

DRVL Turn−Off Propagation Delay
tpdl

DRVL

DRVL Turn−On Propagation Delay
tpdh

DRVL

C

= 3 nF 16 35 ns

LOAD

C

= 3 nF 11 20 ns

LOAD

C

= 3 nF 35 ns

LOAD

C

= 3 nF 8.0 30 ns

LOAD

DRVL Pull Down Resistance DRVL to PGND, VCC = PGND 45 kW

LOW SIDE DRIVER (VCC = 5 V)

Output Impedance, Sourcing Current 4.5 W

Output Impedance, Sinking Current 2.4 W

DRVL Rise Time tr

DRVL Fall Time tf

DRVL

DRVL

DRVL Turn−Off Propagation Delay
tpdl

DRVL

DRVL Turn−On Propagation Delay
tpdh

DRVL

C

= 3 nF 30 ns

LOAD

C

= 3 nF 22 ns

LOAD

C

= 3 nF 27 ns

LOAD

C

= 3 nF 12 ns

LOAD

DRVL Pull Down Resistance DRVL to PGND, VCC = PGND 45 kW

EN INPUT

Input Voltage High 2.0 V

Input Voltage Low 1.0 V

Hysteresis 500 mV

Normal Mode Bias Current −1 1 mA

Enable Pin Sink Current 4 30 mA

Propagation Delay Time 20 40 ns

SW Node

SW Node Leakage Current 20 mA

Zero Cross Detection Threshold Voltage SW to −20 mV, ramp slowly until BG goes off

−6 mV

(Start in DCM mode) (Note 3)

Table 5. DECODER TRUTH TABLE

PWM INPUT ZCD DRVL DRVH

PWM High ZCD Reset Low High

PWM Mid Positive current through the inductor High Low

PWM Mid Zero current through the inductor Low Low

PWM Low ZCD Reset High Low

3. Guaranteed by design; not production tested.

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5

PWM

NCP5901

1V

1V

Figure 4.

DRVH−SW

DRVL

IL

Figure 5. Timing Diagram

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6

NCP5901

C

APPLICATIONS INFORMATION

The NCP5901 gate driver is a single phase MOSFET driver
designed for driving N−channel MOSFETs in a synchronous
buck converter topology. The NCP5901 is designed to work
with ON Semiconductor’s NCP6131 multi−phase controller.
This gate driver is optimized for desktop applications.

Undervoltage Lockout

The DRVH and DRVL are held low until VCC reaches

4.5 V during startup. The PWM signals will control the gate
status when VCC threshold is exceeded. If VCC decreases to
250 mV below the threshold, the output gate will be forced
low until input voltage VCC rises above the startup threshold.

Power−On Reset

Power−On Reset feature is used to protect a gate driver
avoid abnormal status driving the startup condition. When
the initial soft−start voltage is higher than 2.75 V, the gate
driver will monitor the switching node SW pin. If SW pin
high than 2.25 V, bottom gate will be force to high for
discharge the output capacitor. The fault mode will be latch
and EN pin will force to be low, unless the driver is recycle.
When input voltage is higher than 4.5 V, and EN goes high,
the gate driver will normal operation, top gate driver
DRVH and bottom gate driver will follow the PWM signal
decode to a status.

Bi−directional EN Signal

Fault modes such as Power−On Reset and Undervoltage
Lockout will de−assert the EN pin, which will pull down
the DRON pin of controller as well. Thus the controller will
be shut down consequently.

PWM Input and Zero Cross Detect (ZCD)

The PWM input, along with EN and ZCD, control the
state of DRVH and DRVL.

When PWM is set high, DRVH will be set high after the
adaptive non−overlap delay. When PWM is set low, DRVL
will be set high after the adaptive non−overlap delay.

When the PWM is set to the mid state, DRVH will be set
low, and after the adaptive non−overlap delay, DRVL will
be set high. DRVL remains high during the ZCD blanking
time. When the timer is expired, the SW pin will be
monitored for zero cross detection. After the detection, the
DRVL will be set low.

Adaptive Nonoverlap

The nonoverlap dead time control is used to avoid the
shoot through damage the power MOSFETs. When the
PWM signal pull high, DRVL will go low after a
propagation delay, the controller will monitors the
switching node (SWN) pin voltage and the gate voltage of
the MOSFET to know the status of the MOSFET. When the
low side MOSFET status is off an internal timer will delay
turn on of the high–side MOSFET. When the PWM pull

low, gate DRVH will go low after the propagation delay
(tpd DRVH).

The time to turn off the high side MOSFET is depending
on the total gate charge of the high−side MOSFET. A timer
will be triggered once the high side MOSFET is turn off to
delay the turn on the low−side MOSFET.

Low−Side Driver Timeout

In normal operation, the DRVH signal tracks the PWM
signal and turns off the Q1 high−side switch with a few 10
ns delay (t

pdlDRVH

) following the falling edge of the input
signal. When Q1is turned off, DRVL is allowed to go high,
Q2 turns on, and the SW node voltage collapses to zero. But
in a fault condition such as a high−side Q1 switch
drain−source short circuit, the SW node cannot fall to zero,
even when DRVH goes low. This driver has a timer circuit
to address this scenario. Every time the PWM goes low, a
DRVL on−time delay timer is triggered.

If the SW node voltage does not trigger a low−side
turn−on, the DRVL on−time delay circuit does it instead,
when it times out with t

delay. If Q1 is still turned on,

SW(TO)

that is, its drain is shorted to the source, Q2 turns on and
creates a direct short circuit across the VDCIN voltage rail.
The crowbar action causes the fuse in the VDCIN current
path to open. The opening of the fuse saves the load (CPU)
from potential damage that the high−side switch short
circuit could have caused.

Layout Guidelines

Layout for DC−DC converter is very important. The
bootstrap and VCC bypass capacitors should be placed as
close as to the driver IC.

Connect GND pin to local ground plane. The ground
plane can provide a good return path for gate drives and
reduce the ground noise. The thermal slug should be tied to
the ground plane for good heat dissipation. To minimize the
ground loop for low side MOSFET, the driver GND pin
should be close to the low−side MOSFET source pin. The
gate drive trace should be routed to minimize the length,
the minimum width is 20 mils.

Gate Driver Power Loss Calculation

The gate driver power loss consists of the gate drive loss
and quiescent power loss.

The equation below can be used to calculate the power
dissipation of the gate driver. Where QGMF is the total gate
charge for each main MOSFET and QGSF is the total gate
charge for each synchronous MOSFET.

f

+ [

SW

2 n

ǒnMF Q

) nSF Q

GMF

P

DRV

Ǔ

) ICC] V

GSF

Also shown is the standby dissipation factor (ICC ⋅ VCC)

of the driver.

C

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7

−Y−

−Z−

NCP5901

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AK

−X−

B

H

A

58

1

4

G

D

0.25 (0.010) Z

M

S

Y

0.25 (0.010)

C

SEATING
PLANE

SXS

M

0.10 (0.004)

M

Y

K

N

X 45

_

M

J

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8

____

N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

INCHES

SOLDERING FOOTPRINT*

1.52

0.060

7.0

0.275

0.6

0.024

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

4.0

0.155

1.270

0.050

SCALE 6:1

ǒ

inches

mm

Ǔ

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8

NCP5901

a

PACKAGE DIMENSIONS

DFN8 2x2

CASE 506AA

ISSUE E

2X

NOTE 4

PIN ONE

REFERENCE

2X

C0.15

C0.15

DETAIL B

C0.10

C0.08

SIDE VIEW

DETAIL A

K

e/2

e

BOTTOM VIEW

D

TOP VIEW

(A3)

D2

1

8

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.20 MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.

MILLIMETERS

DIM MIN MAX

A 0.80 1.00
A1 0.00 0.05
A3 0.20 REF

b 0.20 0.30

D 2.00 BSC
D2 1.10 1.30

E 2.00 BSC
E2 0.70 0.90

e 0.50 BSC

0.30 REF

K

L 0.25 0.35

L1 −−− 0.10

RECOMMENDED

A1

A
B

L

L

L1

E

A

SEATING

C

PLANE

DETAIL A

OPTIONAL

CONSTRUCTIONS

MOLD CMPDEXPOSED Cu

DETAIL B

OPTIONAL

CONSTRUCTION

SOLDERING FOOTPRINT*

8X

4

L

PACKAGE
OUTLINE

1.30

E2

0.90

5

b8X

0.10 C

0.05 C

A BB

NOTE 3

8X

0.30

1

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

0.50

0.50
PITCH

8X

2.30

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf . SCILLC
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for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components
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Sales Representative

NCP5901/D

9