The NCP382 is a single input dual outputs high side
power−distribution switch designed for applications where heavy
capacitive loads and short−circuits are likely to be encountered. The
device includes an integrated 80 mW, P−channel MOSFET. The
device limits the output current to a desired level by switching into a
constant−current mode when the output load exceeds the current−limit
threshold or a short is present. The current−limit threshold is internally
fixed. The power−switches rise and fall times are controlled to
minimize current ringing during switching.
The FLAG
overtemperature conditions. The switch is controlled by a logic enable
input active high or low.
EN1IEnable 1 input, logic low/high (i.e. EN or EN) turns on power switch.
EN2IEnable 2 input, logic low/high (i.e. EN or EN) turns on power switch.
GNDPGround connection.
INP
FLAG1O
FLAG2O
OUT1O
OUT2O
Power−switch input voltage; connect a 1 mF or greater ceramic capacitor from IN to GND as close as possible to
the IC.
Active−low open−drain output 1, asserted during overcurrent or overtemperature conditions. Connect a 10 kW or
greater resistor pull−up, otherwise leave unconnected.
Active−low open−drain output 2, asserted during overcurrent or overtemperature conditions. Connect a 10 kW or
greater resistor pull−up, otherwise leave unconnected.
Power−switch output1; connect a 1 mF ceramic capacitor from OUT1 to GND, as close as possible to the IC.
This minimum value is recommended for USB requirement in terms of load transient response and strong short
circuits.
Power−switch output2; connect a 1 mF ceramic capacitor from OUT2 to GND, as close as possible to the IC.
This minimum value is recommended for USB requirement in terms of load transient response and strong short
circuits.
1
2
3
4
8
FLAG1
7
OUT1
6
OUT2
5
FLAG2
http://onsemi.com
2
NCP382
MAXIMUM RATINGS
RatingSymbolValueUnit
From IN to OUT1, From IN to OUT2 Supply Voltage (Note 1)V
IN, OUT1,OUT2, EN1, EN2, FLAG1, FLAG2 (Note 1)V
IN,
FLAG1, FLAG2 sink currentI
ESD Withstand Voltage (IEC 61000−4−2) (output only, when
bypassed with 1.0 mF capacitor minimum)
Human Body Model (HBM) ESD Rating are (Note 2)ESD HBM2000V
Machine Model (MM) ESD Rating are (Note 2)ESD MM200V
Latch−up protection (Note 3)
− Pins IN, OUT1, OUT2, FLAG1
, FLAG2
− EN1, EN2
Maximum Junction Temperature (Note 4)T
Storage Temperature RangeT
Moisture Sensitivity (Note 5)MSLLevel 1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. According to JEDEC standard JESD22−A108.
2. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) +/−2.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) +/−200 V per JEDEC standard: JESD22−A115 for all pins.
3. Latch up Current Maximum Rating: $100 mA per JEDEC standard: JESD78 class II.
4. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
V
IN ,
V
OUT1, VOUT2,
V
FLAG1
OUT1,VOUT2
V
EN1,
, V
FLAG2
SINK
V
EN2,
−7.0 to +7.0V
−0.3 to +7.0V
1.0mA
ESD IEC15 Air, 8 contactkV
LU
100
J
STG
−40 to + TSD°C
−40 to + 150°C
mA
OPERATING CONDITIONS
SymbolParameterConditionsMinTypMaxUnit
V
V
ENX
T
I
SINK
C
C
OUTX
R
q
T
I
OUTX
P
6. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation.
7. The R
final PCB layout.
8. The maximum power dissipation (P
Operational Power Supply2.55.5V
IN
Enable Voltage05.5
Ambient Temperature Range−4025+85°C
A
FLAG sink current1mA
Decoupling input capacitor1
IN
Decoupling output capacitorUSB port per Hub120
Thermal Resistance Junction−to−Air
JA
DFN−8 package (Notes 6 and 7)140°C/W
SOIC−8 package (Notes 6 and 7)210°C/W
Junction Temperature Range−4025+125°C
J
Recommended Maximum DC
current
Power Dissipation Rating (Note 8)TA v 25°C
D
DFN−8 package2A
SOIC−8 package1.5A
DFN−8 package850mW
SOIC−8 package570mW
TA = 85°C
DFN−8 package428mW
SOIC−8 package285mW
is dependent of the PCB heat dissipation. Announced thermal resistance is the unless PCB dissipation and can be improve with
q
JA
) is given by the following formula:
D
PD+
T
JMAX
R
qJA
* T
A
mF
mF
http://onsemi.com
3
NCP382
ELECTRICAL CHARACTERISTICS Min & Max Limits apply for T
between −40°C to +85°C and TJ up to + 125°C for VIN between
A
2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to T