ON NCP1589AMNTWG, NCP1589BMNTWG Schematic [ru]

NCP1589A, NCP1589B

Low Voltage Synchronous
Buck Controller

The NCP1589A/B is a low cost PWM controller designed to operate
from a 5 V or 12 V supply. This device is capable of producing an
output voltage as low as 0.8 V. This device is capable of converting
voltage from as low as 2.5 V. This 10−pin device provides an optimal
level of integration to reduce size and cost of the power supply.
Features include a 1.5 A gate driver design and an internally set
300 kHz or 600 kHz oscillator. In addition to the 1.5 A gate drive
capability, other efficiency enhancing features of the gate driver
include adaptive non−overlap circuitry. The NCP1589A/B also
incorporates an externally compensated error amplifier. Protection
features include programmable short circuit protection and
undervoltage lockout (UVLO).

Features

• V

Range from 4.5 V to 13.2 V

CC

• 300 kHz and 600 kHz Internal Oscillator

• Boost Pin Operates to 30 V

• Voltage Mode PWM Control

• Precision 0.8 V Internal Reference

• Adjustable Output Voltage

• Internal 1.5 A Gate Drivers

• 80% Max Duty Cycle

• Input Under Voltage Lockout

• Programmable Current Limit

• This is a Pb−Free Device

Applications

• Graphics Cards

• Desktop Computers

• Servers / Networking

• DSP & FPGA Power Supply

• DC−DC Regulator Modules

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MARKING DIAGRAM

1589x

DFN10

CASE 485C

1589x = Specific Device Code

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Device

(Note: Microdot may be in either location)

BOOT

LX

UG

LG

GND

ORDERING INFORMATION

Device Package Shipping

NCP1589AMNTWG

NCP1589BMNTWG

NCP1589AMNTXG

NCP1589BMNTXG

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

x = A or B

PIN CONNECTIONS

1

2

3

4

5

(Top View)

DFN10

(Pb−Free)

ALYWG

G

PGOOD

10

9 VOS

8

FB

7 COMP/EN

V

6

CC

3000 /

Tape & Reel

†

© Semiconductor Components Industries, LLC, 2009

August, 2009 − Rev. 0

1 Publication Order Number:

NCP1589A/D

NCP1589A, NCP1589B

3.878kW

= 4.5 V − 15 V

V

BST

1mF

VCC

PGOOD

C1

0.0015mF

R4

4.12kW

R1

R2

17.08kW

C2

0.007mF

C3

0.014mF

R3

74.2W

COMP/EN

BOOT

GNDFBVOS

R9 R10

UG

LX

LG

1.02k

0.1mF

ROCSET

1.02k

VIN = 2.5 V − 13.2 VVCC = 4.5 V − 13.2 V

2x0.22mF

VOUT

1.65 V

2x1800mF

GND

2.2

NTD4806 NTD4809

4.7nF

1500mF

1mH

1500mF

3x22mF

Figure 1. Typical Application Diagram

PGOOD

10

VOS

FB

COMP/EN

9

PGOOD

MONITOR

OV and UV

±10% of V

±25% of V

ref

ref

0.8 V
(V

)

ref

FAULT

8

−

+

+

−

0.8 V
(V

)

ref

CLOCK

RAMP

7

OSC

OSC

R

PWM

OUT

S

SOFT

START

POR

UVLO

LATCH

Q

FAULT

FAULT

VCC

6

+

VOCP

−

1

BOOT

UG

3

LX

+

2

−

2 V

+

−

VCC

LG

4

5

GND

Figure 2. Detailed Block Diagram

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2

NCP1589A, NCP1589B

PIN FUNCTION DESCRIPTION

Pin No. Symbol Description

1 BOOT Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired

2 LX Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top

3 UG Top gate MOSFET driver pin. Connect this pin to the gate of the top N−channel MOSFET.

4 LG Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N−channel MOSFET.

5 GND IC ground reference. All control circuits are referenced to this pin.

6 VCC

7 COMP/EN Compensation Pin. This is the output of the error amplifier (EA) and the non−inverting input of the PWM com-

8 FB This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to com-

9 VOS Voltage Offset Sense

10 PGOOD Power Good output. Pulled Low if VOS is ±10% of 0.8 V V

input voltage to this pin (cathode connected to BOOT pin). Connect a capacitor (C
the LX pin. Typical values for C

range from 0.1 mF to 1 mF. Ensure that C

BOOT

BOOT

) between this pin and

BOOT

is placed near the IC.

MOSFET.

Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 mF capacitor
to GND. Ensure that this decoupling capacitor is placed near the IC.

parator. Use this pin in conjunction with the FB pin to compensate the voltage−control feedback loop. Pull this
pin low for disable.

pensate the voltage−control feedback loop. Connect this pin to the output resistor divider (if used) or directly
to V

.

out

.

ref

ABSOLUTE MAXIMUM RATINGS

Pin Name Symbol V

MAX

Main Supply Voltage Input VCC 15 V −0.3 V

Bootstrap Supply Voltage Input BOOT 35 V wrt/GND

40 V < 100 ns

15 V wrt/LX

Switching Node (Bootstrap Supply Return) LX 35 V

40 V for < 100 ns

High−Side Driver Output (Top Gate) UG 30 V wrt/GND

15 V wrt/LX

40 V for < 100 ns

Low−Side Driver Output (Bottom Gate) LG VCC + 0.3 V −0.3 V

Feedback, VOS FB, VOS 5.0 V −0.3 V

COMP/EN COMP/EN 3.6 V −0.3 V

PGOOD PGOOD 7 V −0.3 V

V

MIN

−0.3 V

−0.3 V

−0.3 V

−5 V

−10 V for < 200 ns

−0.3 V wrt/LX

−2 V for < 200 ns

−5 V for < 200 ns

MAXIMUM RATINGS

Rating Symbol Value Unit

Thermal Resistance, Junction−to−Ambient

Thermal Resistance, Junction−to−Case

Operating Junction Temperature Range T

Operating Ambient Temperature Range T

Storage Temperature Range T

R

q

JA

R

q

JC

J

A

stg

Moisture Sensitivity Level MSL 1 −

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
This device is ESD sensitive. Use standard ESD precautions when handling.

165 °C/W

45 °C/W

0 to 150 °C

0 to 70 °C

−55 to +150 °C

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NCP1589A, NCP1589B

ELECTRICAL CHARACTERISTICS (0°C < T

C

= C

TG

Input Voltage Range 4.5 13.2 V

Boost Voltage Range 13.2 V wrt LX 4.5 30 V

= 1.0 nF, for min/max values unless otherwise noted.)

BG

Characteristic

< 70°C; 4.5 V < [BST−PHASE] < 13.2 V, 4.5 V < BST < 30 V, 0 V < PHASE < 21 V,

A

Conditions Min Typ Max Unit

Supply Current

Quiescent Supply Current (NCP1589A) VFB = 1.0 V, No Switching, VCC = 13.2 V 1.0 8.0 mA

Boost Quiescent Current VFB = 1.0 V, No Switching 0.1

Undervoltage Lockout

UVLO Threshold VCC Rising 3.8 4.0 4.2 V

UVLO Threshold VCC Falling 3.4 3.6 3.8 V

UVLO Hysteresis VCC Rising or VCC Falling 0.4 V

Switching Regulator

VFB Feedback Voltage (FB Tied to Comp. Measure FB Pin.) 0.7936 0.8 0.8064 V

Oscillator Frequency (NCP1589A) 270 300 330 kHz

Oscillator Frequency (NCP1589B) 540 600 660 kHz

Ramp−Amplitude Voltage 1.1 V

Minimum Duty Cycle 0 %

Maximum Duty Cycle 70 75 80 %

LG Minimum on Time 500 ns

Error Amplifier

Open Loop DC Gain (Note 1) 70 80 dB

Output Source Current
Output Sink Current

Input Offset Voltage (Note 1) −2.0 0 2.0 mV

Input Bias Current 0.1 1.0

Unity Gain Bandwidth (Note 1) 15 Mhz

Disable Threshold 0.6 0.8 V

Output Source Current During Disable 10 40

Vfb < 0.8 V
Vfb > 0.8 V

2.0

2.0

Gate Drivers

Upper Gate Source VCC = 5 V, VUG − VLX = 2.5 V 1.5 A

Upper Gate Sink 1.4

Lower Gate Source 1.5 A

Lower Gate Sink VCC = 12 V 1.0

UG Falling to LG Rising Delay VCC = 12 V, UG−LX < 2.0 V, LG > 2.0 V 12.4 18 ns

LG Falling to UG Rising Delay VCC = 12 V, LG < 2.0 V, UG > 2.0 V 12.4 18 ns

Soft−Start

Soft−Start time 3.0 7.0 ms

Power Good

Output Voltage Logic Low, Sinking 4 mA 0.4 V

OVP Threshold to PGOOD Output Low Ramp VOS from 0.7 to 1.2.

Monitor when PGOOD goes Low

OVP Threshold to Part Disable Ramp VOS from 0.8 to 1.2.

Monitor when outputs disable

UVP Threshold to PGOOD Output Low Ramp VOS from 800 mV to 500 mV.

Monitor when PGOOD goes Low

UVP Threshold to Part Disable Ramp VOS from 800 mV to 500 mV.

Monitor when utputs stop switching

0.65 0.72 V

0.5 0.6 V

0.88 1.0 V

1.0 1.2 V

Overcurrent Protection

OC Current Source (Note 1) Sourced from LG pin, before SS 9.0 10 11

1. Guaranteed by design but not tested in production.

mA

mA

mA

mA

W

W

mA

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