ON NCP1203D100G, NCP1203D100R2G, NCP1203D40G, NCP1203D40R2G, NCP1203D60G Schematic [ru]
...
NCP1203
PWM Current--Mode
Controller for Universal
Off-- Line S upplies Featuring
Standby and Short Circuit
Protection
Housed in SOIC--8 or PDIP--8 package, the NCP1203 represents a
major leap toward ultra--compact Switchmode Power Supplies and
represents an excellent candidate to replace the UC384X devices. Due
to its proprietary SMARTMOS Very High Voltage Technology, the
circuit allows the implementation of complete off--line AC--DC
adapters, battery charger and a high--power SMPS with few external
components.
With an internal structure operating at a fixed 40 kHz, 60 kHz or
100 kHz switching frequency, the controller features a high--voltage
startup FET which ensures a clean and loss--less startup sequence. Its
current--mode control naturally provides good audio--susceptibility
and inherent pulse--by--pulse control.
When the current setpoint falls below a given value, e .g. the output
power demand diminishes, the IC automatically enters the so--called
skip cycle mode and provides improved efficiency at light loads
while offering excellent performance in standby conditions. Because
this occurs at a user adjustable low peak current, no acoustic noise
takes place.
The NCP1203 also includes an efficient protective circuitry which,
in presence of an output over load condition, disables the output
pulses while the device enters a safe burst mode, trying to restart.
Once the default has gone, the device auto--recovers. Finally, a
temperature shutdown with hysteresis helps building safe and robust
power supplies.
Features
High--Voltage Startup Current Source
Auto--Recovery Internal Output Short--Circuit Protection
Extremely Low No--Load Standby Power
Current--Mode with Adjustable Skip--Cycle Capability
Internal Leading Edge Blanking
250 mA Peak Current Capability
Internally Fixed Frequency at 40 kHz, 60 kHz and 100 kHz
Direct Optocoupler Connection
Undervoltage Lockout at 7.8 V Typical
SPICE Models Available for TRANsient and AC Analysis
Pin to Pin Compatible with NCP1200
Pb--Free Packages are Available
http://onsemi.com
MARKING
DIAGRAM
8
SOIC--8
8
1
8
1
D1, D2 SUFFIX
CASE 751
x = 4, 6, or 1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb--Free Package
PDIP--8
N SUFFIX
CASE 626
xx = 40, 60, or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb--Free Package
PIN CONNECTIONS
Adj
1
FB
2
CS
3
GND
4
(Top View)
8
7
6
5
8
1
1
1203Pxx
YYWWG
HV
NC
V
CC
Drv
203Dx
ALYW
G
AWL
Applications
AC--DC Adapters for Notebooks, etc.
Offline Battery Chargers
Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
Semiconductor Components Industries, LLC, 2010
December, 2010-- Rev. 10
ORDERING INFORMATION
See detailed ordering and shipping information in thepackage
dimensions section on page 13 of this data sheet.
1
Publication Order Number:
NCP1203/D
NCP1203
*
+
EMI
FILTER
UNIVERSAL
INPUT
*Please refer to the application information section
+
NCP1203
HV
Adj
1
FB
2
CS
3
GND
4
V
CC
Drv
8
7
6
5
Aux.
+
Figure 1. Typical Application Example
PIN FUNCTION DESCRIPTION
Pin No. Pin Name Function Pin Description
1 Adj Adjust the skipping peak current This pin lets you adjust the level at which the cycle skipping process takes
2 FB Sets the peak current setpoint By connecting an optocoupler to this pin, the peak current setpoint is
3 CS Current sense input This pin senses the primary current and routes it to the internal comparator
4 GND The IC ground --
5 Drv Driving pulses The driver’s output to an external MOSFET.
6 V
7 NC -- This unconnected pin ensures adequate creepage distance.
8 HV Ensure a clean and lossless
CC
Supplies the IC
startup s equence
place. Shorting this pin to ground, permanently disables the skip cycle
feature.
adjusted accordingly to the output power demand. Skip cycle occurs when
FB falls below Vpin1.
viaanL.E.B.
This pin is connected to an external bulk capacitor of typically 22 mF.
Connected to the high--voltage rail, this pin injects a constant current into
the V
capacitor during the startup sequence.
CC
V
OUT
http://onsemi.com
2
NCP1203
Adj
FB
CURRENT
SENSE
GROUND
HV
1
8
HV CURRENT
SOURCE
80 k
1.2 V
2
SKIP CYCLE
COMPARATOR
+
--
INTERNAL V
UVLO HIGH AND LOW
INTERNAL REGULATOR
CC
NC
7
24 k
Q FLIP--FLOP
DCmax = 80%
3
250 ns
L.E.B.
40--60--100 kHz
CLOCK
20 k 57 k
V
4
REF
+
25 k
1V
SET
RESET
+
--
Q
OVERLOAD
MANAGEMENT
250 mA
V
6
Drv
5
CC
--
Figure 2. Internal Circuit Architecture
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage VCC,Drv 16 V
Power Supply Voltage on all other pins except Pin 5 (Drv), Pin 6 (VCC) and Pin 8 (HV) -- --0.3to10 V
Maximum Current into all pins except Pin 6 (VCC) and Pin 8 (HV) when
10 V ESD diodes are activated
Thermal Resistance, Junction--to--Air, PDIP--8 Version
Thermal Resistance, Junction--to--Air, SOIC Version
Thermal Resistance, Junction--to--Case
Maximum Junction Temperature TJ
R
R
R
--
θ
JA
θ
JA
θ
JC
MAX
Temperature Shutdown -- 170 C
Hysteresis in Shutdown -- 30 C
Operating Temperature Range T
Storage Temperature Range T
J
stg
ESD Capability, Human Body Model, All pins except Pin 6 (VCC) and Pin 8 (HV) -- 2.0 kV
ESD Capability, Machine Model -- 200 V
MaximumVoltageonPin8(HV)withPin6(VCC) Decoupled to Ground with 10mF
-- 500 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
5.0 mA
100
C/W
178
57
150 C
--40 to +125 C
--60 to +150 C
http://onsemi.com
3
NCP1203
ELECTRICAL CHARACTERISTICS (For typical values T
= 11 V unless otherwise noted.)
V
CC
Characteristic
=25C, for min/max values TJ=0C to +125C, Max TJ= 150C,
J
Symbol Pin Min Ty p Max Unit
Supply Section (All frequency versions, otherwise noted)
Turn--on Threshold Level, V
Minimum Operating Voltage after Turn--on V
VCCDecreasing Level at which the Latchoff Phase Ends V
Going Up V
CC
CC(on)
CC(min)
CClatch
6 12.2 12.8 14 V
6 7.2 7.8 8.4 V
6 -- 4.9 -- V
Internal IC Consumption, No Output Load on Pin 5 ICC1 6 -- 750 880
(Note 1)
Internal IC Consumption, 1.0 nF Output Load on Pin 5,
F
=40kHz
SW
Internal IC Consumption, 1.0 nF Output Load on Pin 5,
F
=60kHz
SW
Internal IC Consumption, 1.0 nF Output Load on Pin 5,
= 100 kHz
F
SW
ICC2 6 -- 1.2 1.4
(Note 2)
ICC2 6 -- 1.4 1.6
(Note 2)
ICC2 6 -- 2.0 2.2
(Note 2)
Internal IC Consumption, Latch--off Phase, VCC=6.0V ICC3 6 -- 250 --
Internal Startup Current Source (Pin8biasedat50V)
High--Voltage Current Source, V
=10V IC1 8 3.5 6.0 9.0 mA
CC
High--Voltage Current Source, VCC=0 IC2 8 -- 11 -- mA
Drive Output
Output Voltage Rise--Time @ CL = 1.0 nF, 10-- 90% of
T
r
5 -- 67 -- ns
Output Signal
Output Voltage Fall--Time @ CL = 1.0 nF, 10--90% of
T
f
5 -- 28 -- ns
Output Signal
Source Resistance R
Sink Resistance R
OH
OL
5 27 40 61
5 5.0 10 20
Current Comparator (Pin 5 loaded unless otherwise noted)
Input Bias Current @ 1.0 V Input Level on Pin 3
Maximum Internal Current Setpoint (Note 3) I
Default Internal Current Setpoint for Skip Cycle Operation I
Propagation Delay from Current Detection to Gate OFF
Limit
Lskip
T
I
IB
DEL
3 -- 0.02 --
3 0.85 0.92 1.0 V
3 -- 360 -- mV
3 -- 90 160 ns
State
Leading Edge Blanking Duration (Note 3) T
LEB
3 -- 230 -- ns
Internal Oscillator (VCC= 11 V, Pin 5 loaded by 1 nF)
Oscillation Frequency, 40 kHz Version
Oscillation Frequency, 60 kHz Version f
Oscillation Frequency, 100 kHz Version f
f
OSC
OSC
OSC
-- 37 42 47 kHz
-- 57 65 73 kHz
-- 90 103 11 5 kHz
Maximum Duty--Cycle Dmax -- 74 80 87 %
Feedback Section (VCC= 11 V, Pin 5 unloaded)
Internal Pullup Resistor
Rup 2 -- 20 --
Pin 3 to Current Setpoint Division Ratio Iratio -- -- 3.3 -- --
Skip Cycle Generation
Default S kip Mode Level
Vskip 1 1.0 1.2 1.4 V
Pin 1 Internal Output Impedance Zout 1 -- 22 --
1. Max value at TJ=0C.
2. Maximum value @ T
3. Pin 5 loaded by 1 nF.
=25C, please see characterization curves.
J
mA
mA
mA
mA
mA
Ω
Ω
mA
kΩ
kΩ
http://onsemi.com
4
NCP1203
14.0
13.8
13.6
13.4
13.2
13.0
THRESHOLD (V)
12.8
CC(on)
12.6
V
12.4
12.2
900
860
820
780
740
700
660
620
580
, CURRENT CONSUMPTION (mA)
540
CC
I
500
8.4
8.2
8.0
LEVEL (V)
7.8
7.6
CC(min)
V
7.4
7.2
--25 --25
TEMPERATURE (C) TEMPERATURE (C)
Figure 3. V
CC(on)
50
Threshold versus
75
100
-- 5 0 0
Figure 4. V
Temperature
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
, 1 nF LOAD CONSUMPTION (mA)
1.1
CC
I
-- 2 5
1251007550250-- 5 0
TEMPERATURE (C)
1.0
25250 125
CC(min)
Level versus Temperature
100 kHz
60 kHz
40 kHz
TEMPERATURE (C)
50 75 100
125-- 5 0
1251007550250-- 5 0 -- 2 5
HV CURRENT SOURCE (mA)
Figure 5. ICCurrent Consumption (No Load)
versus Temperature
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
-- 2 5
TEMPERATURE (C)
60 kHz
40 kHz
100 kHz
Figure 7. HV Current Source at VCC=10V
versus Temperature
400
350
300
=6V(mA)
CC
250
@V
CC
I
200
1251007550250-- 5 0
150
http://onsemi.com
5
Figure 6. ICCConsumption (Loaded by 1 nF)
versus Temperature
-- 2 5
TEMPERATURE (C)
Figure 8. ICConsumption at VCC=6V
versus Temperature
1251007550250-- 5 0
NCP1203
DRIVE SOURCE RESISTANCE (Ω)
MAXIMUM CURRENT SETPOINT (V)
60
55
50
45
40
35
30
25
20
15
0.99
0.97
0.95
0.93
0.91
0.89
0.87
0.85
75
100
-- 2 5 -- 2 5
TEMPERATURE (C) TEMPERATURE (C)
50
Figure 9. Drive Source Resistance versus
Temperature
-- 5 0
-- 2 5
TEMPERATURE (C) TEMPERATURE (C)
50
75
100250 125
20
18
16
14
12
10
8
6
DRIVE SINK RESISTANCE (Ω)
4
2
-- 5 0 0
Figure 10. Drive Sink Resistance versus
120
100
80
60
40
f, FREQUENCY (kHz)
20
0
-- 2 5
25250 125
50 75 100
Temperature
100 kHz
60 kHz
40 kHz
125-- 5 0
1251007550250-- 5 0
Figure 11. Maximum Current Setpoint versus
Temperature
http://onsemi.com
Figure 12. Frequency versus Temperature
6
NCP1203
APPLICATION INFORMATION
Introduction
The NCP1203 implements a standard current mode
architecture where the switch--off time is dictated by the
peak current setpoint. This component represents the ideal
candidate where low part--count is the key parameter,
particularly in low--cost AC--DC adapters, auxiliary
supplies etc. Due to its high--performance SMARTMOS
High--Voltage technology, the NCP1203 incorporates all the
necessary components normally needed in UC384X based
supplies: timing components, feedback devices, low--pass
filter and startup device. This later point emphasizes the fact
that ON Semiconductor’s NCP1203 does not need an
external startup resistance but supplies the startup current
directly from the high--voltage rail. On the other hand, more
and more applications are requiring low no--load standby
power, e.g. for AC--DC adapters, VCRs etc. UC384X series
have a lot of difficulty to reduce the switching losses at low
power levels. NCP1203 elegantly solves this problem by
12.8 V /4.9 V
+
--
6mAor0
skipping unwanted switching cycles at a user--adjustable
power level. By ensuring that skip cycles take place at low
peak current, the device ensures quiet, noise free operation.
Finally, an auto--recovery output short--circuit protection
(OCP) prevents from any lethal thermal runaway in
overload conditions.
Startup Sequence
When the power supply is first powered from the mains
outlet, the internal current source (typically 6.0 mA) is
biased and charges up the V
on this V
capacitor reaches the V
CC
capacitor. When the voltage
CC
level (typically
CC(on)
12.8 V), the current source turns off and no longer wastes
any power. At this time, the V
capacitor only supplies the
CC
controller and the auxiliary supply is supposed to take over
before V
collapses below V
CC
. Figure 13 shows the
CC(min)
internal arrangement of this structure:
8
6
HV
Figure 13. The Current Source Brings VCCAbove 12.8 V and then Turns Off
Once the power supply has started, the VCCshall be
constrained below 16 V, which is the maximum rating on
pin 6. Figure 14 portrays a typical startup sequence with a
V
regulated at 12.5 V:
CC
CV
CC
4
13.5
12.5
11. 5
10.5
9.5
Figure 14. A Typical Startup Sequence for
12.8 V
3.00 M 8.00 M 13.0 M 18.0 M 23.0 M
Aux
t, TIME (sec)
the NCP1203
REGULATION
http://onsemi.com
7
NCP1203
Current--Mode Operation
As the UC384X series, the NCP1203 features a
well--known current mode control architecture which
provides superior input audio--susceptibility compared to
traditional voltage--mode controllers. Primary current
pulse--by--pulse checking together with a fast over current
comparator offers greater security in the event of a difficult
fault condition, e.g. a saturating transformer.
Adjustable Skip Cycle Level
By offering the ability to tailor the level at which the skip
cycle takes place, the designer can make sure that the skip
operation only occurs at low peak current. This point
guarantees a noise--free operation with cheap transformers.
Skip cycle offers a proven mean to reduce the standby power
in no or light loads situations.
Wide Switching--Frequency Offer
Four different options are available: 40 kHz -- 65 kHz –
100 kHz. Depending on the application, the designer can
pick up the right device to help reducing magnetics or
improve the EMI signature before reaching the 150 kHz
starting point.
Overcurrent Protection (OCP)
When the auxiliary winding collapses below UVLOlow,
the controller stops switching and reduces its consumption.
It stays in this mode until Vcc reaches 4.9 V typical, where
the startup source is reactivated and a new startup sequence
is attempted. The power supply is thus operated in burst
mode and avoids any lethal thermal runaway. When the
default goes way, the power supply automatically resumes
operation.
Wide Duty--Cycle Operation
Wide mains operation requires a large duty--cycle
excursion. The NCP1203 can go up to 80% typically.
Low Standby Power
If SMPS naturally exhibit a good efficiency at nominal
load, they begin to be less efficient when the output power
demand diminishes. By skipping un--needed switching
cycles, the NCP1203 drastically reduces the power wasted
during light load conditions. In no--load conditions, the
NCP1203 allows the total standbypower to easily reachnext
International Energy Agency (IEA) recommendations.
No Acoustic Noise while Operating
Instead of skipping cycles at high peak currents, the
NCP1203 waits until the peak current demand falls below a
user--adjustable 1/3
rd
of the maximum limit. As a result,
cycle skipping can take place without having a singing
transformer You can thus select cheap magnetic
components free of noise problems.
External MOSFET Connection
By leaving the external MOSFET external to the IC, you
can select avalanche proof devices which, in certain cases
(e.g. low output powers), let you work without an active
clamping network. Also, by controlling the MOSFET gate
signal flow, you have an option to slow down the device
commutation, therefore reducing the amount of
ElectroMagnetic Interference (EMI).
SPICE Model
A dedicated model to run transient cycle--by--cycle
simulations is available but also an averaged version to help
you closing the loop. Ready--to--use templates can be
downloaded in OrCAD’sPspice and INTUSOFT’sfrom ON
Semiconductor web site, NCP1203 related section.
Overload Operation
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it is
interesting to implement a true short--circuit protection. A
short--circuit actually forces the output voltage to be at a low
level, preventing a bias current to circulate in the
optocoupler LED. As a result, the auxiliary voltage also
decreases because it also operates in Flyback and thus
duplicates the output voltage, providing the leakage
inductance between windings is keptlow.Toaccount for this
situation and properly protect the power supply, NCP1203
hosts a dedicated overload detection circuitry. Once
activated, this circuitry imposes to deliver pulses in a burst
manner with a low duty--cycle. The system auto--recovers
when the fault condition disappears.
During the startup phase, the peak current is pushed to the
maximum until the output voltage reaches its target and the
feedback loop takes over. The auxiliary voltage takes place
after a few switching cycles and self--supplies the IC. In
presence of a short circuit on the output, the auxiliary
voltage will go down until it crosses the undervoltage
lockout level of typically 7.8 V. When this happens,
NCP1203 immediately stops the switching pulses and
unbias all unnecessary logical blocks. The overall
consumption drops, while keeping the gate grounded, and
the V
slowly falls down. As soon as VCCreaches typically
CC
4.8 V, the startup source turns--on again and a new startup
sequence occurs, bringing V
toward 12.8 V as an attempt
CC
to restart. If the default has gone, then the power supply
normally restarts. If not, a new protective burst is initiated,
shielding the SMPS from any runaway. Figure 15, on the
following page, portrays the typical operating signals in
short circuit.
http://onsemi.com
8
NCP1203
12.8 V
Figure 15. Typical Waveforms in Short Circuit Conditions
Calculating the VCCCapacitor
7.8 V
4.9 V
The VCCcapacitor can be calculated knowing the IC
consumption as soon as V
reaches 12.8 V. Suppose that a
CC
NCP1203P60 is used and drives a MOSFET with a 30 nC
total gate charge (Qg). The total average current is thus made
of ICC1 (700 mA) plus the driver current, Fsw x Qg or
1.8 mA. The total current is therefore 2.5 mA. The ΔV
available to fully startup the circuit (e.g. never reach the
7.8 V UVLO during power on) is 12.8–7.8 = 5 V. We have
a capacitor who then needs to supply the NCP1203 with
2.5 mA during a given time until the auxiliary supply takes
over. Suppose that this time was measured at around 15 ms.
CV
C ≥ 7.5 mF
Skipping Cycle Mode
is calculated using the equation
CC
. Select a 22 mF/16 V and this will fit.
C =
Δt·i
ΔV
The NCP1203 automatically skips switching cycles when
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level (Vpin 1), the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so--called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 17).
Suppose we have the following component values:
Lp, primary inductance = 350 mH
Fsw , switching frequency = 61 kHz
Ip skip = 600 mA (or 333 mV/Rsense)
or
V
CC
DRIVING PULSES
The theoretical power transfer is therefore:
1
·Lp·Ip2·Fsw= 3.8 W
2
If this IC enters skip cycle mode with a bunch length of
10 ms overa recurrent period of 100 ms, then the total power
transfer is:
3.8 . 0.1 = 380 mW
.
To better understand how this skipcycle mode takesplace,
a look at the operation mode versus the FB level
immediately gives the necessary insight:
FB
4.2 V, FB Pin Open
3.2 V, Upper
NORMAL CURRENT
MODE OPERATION
SKIP CYCLE OPERATION
I
= 333 mV/R
P(min)
SENSE
Figure 16.
Dynamic Range
1V
When FB is above the skip cycle threshold (1.0 V by
default), the peak current cannot exceed 1.0 V/Rsense.
When the IC enters the skip cycle mode, the peak current
cannot go below Vpin1/3.3/Rsense. The user still has the
flexibility to alter this 1.0 V by either shunting pin 1 to
ground through a resistor or raising it through a resistor up
to the desired level. Grounding pin 1 permanently
invalidates the skip cycle operation. However, given the
extremely low standby power the controller can reach, the
PWM in no--load conditions can quickly enter the minimum
t
and still transfer too much power. An instability can take
on
place. We recommend in that case to leave a little bit of skip
level to always allow 0% duty cycle.
http://onsemi.com
9
NCP1203
Figure 17. Output Pulses at Various Power Levels (X = 5.0 ms/div) P1 < P2 < P3
Power P1
Power P2
Power P3
300 M
200 M
100 M
0
315.40 882.70 1.450 M 2.017 M 2.585 M
Figure 18. The Skip Cycle Takes Place at Low Peak Currents which Guaranties Noise--Free Operation
MAX PEAK
CURRENT
We recommend a pin 1 operation between 400 mV and
1.3 V that will fix the skip peak current level between
120 mV/Rsense and 390 mV/Rsense.
Non--Latching Shutdown
In some cases, it might be desirable to shut off the part
temporarily and authorize its restart once the default has
SKIP CYCLE
CURRENT LIMIT
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB below the Adj pin 1 level, the
output pulses are disabled as long as FB is pulled below
pin 1. As soon as FB is relaxed, the IC resumes its operation.
Figure 19 depicts the application example.
http://onsemi.com
10
NCP1203
ON/OFF
Figure 19. Another Way of Shutting Down the IC without a Definitive Latch--Off State
Full Latching Shutdown
Other applications require a full latching shutdown, e.g.
when an abnormal situation is detected (overtemperature or
overvoltage). This feature can easily be implemented
through two external transistors wired as a discrete SCR.
OVP
10 k
0.1 mF
10 k
8
7
6
5
Q1
When the V
1
2
3
4
level exceeds the zener breakdown voltage,
CC
the NPN biases the PNP and fires the equivalent SCR,
permanently bringing down the FB pin. The switching
pulses are disabled until the user unplugs the power supply.
Rhold
12 k
NCP1203
1
2
3
4
8
7
6
5
CV
CC
LAux
Figure 20. Two Bipolars Ensure a Total Latch--Off of the SMPS in Presence of an OVP
Rhold ensures that the SCR stays on when fired. The bias
current flowing through Rhold should be small enough to let
the V
ramp up (12.8 V) and down (4.9 V) when the SCR
CC
is fired. The NPN base can also receive a signal from a
temperature sensor. Typical bipolars can be MMBT2222
and MMBT2907 for the discrete latch. The MMBT3946
features two bipolars NPN+PNP in the same package and
could also be used.
Protecting the Controller Against Negative Spikes
As with any controller built upon a CMOS technology, it
is the designer’s duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if they are a low impedance
path is offered between V
and GND. If the current sense
CC
pin is often the seat of such spurious signals, the
high--voltage pin can also be the source of problems in
certain circumstances. During the turn--off sequence, e.g.
when the user un--plugs the power supply, the controller is
still fed by its V
capacitor and keeps activating the
CC
MOSFET ON and OFF with a peak current limited by
Rsense. Unfortunately, if the quality coefficient Q of the
resonating network formed by Lp and Cbulk is low (e.g. the
MOSFET Rdson + Rsense are small), conditions are met to
make the circuit resonate and thus negatively bias the
controller. Since we are talking about ms pulses, the amount
of injected charge (Q = I x t) immediately latches the
controller which brutally dischargesits V
V
capacitor is of sufficient value, its stored energy
CC
capacitor.If this
CC
damages the controller. Figure 21 depicts a typical negative
shot occurring on the HV pinwhere the brutal V
discharge
CC
testifies for latchup.
http://onsemi.com
11
NCP1203
Figure 21. A negative spike takes place on the Bulk capacitor at the switch--off sequence
Simple and inexpensive cures exist to prevent from
internal parasitic SCR activation. One of them consists in
inserting a resistor in series with the high--voltage pin to
keep the negative current to the lowest when the bulk
becomes negative (Figure 22). Please note that the negative
spike is clamped to –2 x Vf due to the diode bridge. Also, the
power dissipation of this resistor is extremely small since it
only heats up during the startup sequence.
Rbulk
>4.7k
+
Cbulk
1
2
3
4
Figure 22. A simple resistor in series avoids any
latchup in the controller
8
7
6
5
+
CV
CC
Another option (Figure 23) consists in wiring a diodefrom
V
to the bulk capacitor to force VCCto reach UVLOlow
CC
sooner and thus stops the switching activity before the bulk
capacitor gets deeply discharged. For security reasons, two
diodes can be connected in series.
+
Cbulk
1
2
3
4
Figure 23. or a diode forces VCCto reach
UVLOlow sooner
8
7
6
5
D3
1N4007
+
CV
CC
http://onsemi.com
12
NCP1203
ORDERING INFORMATION
Device Package Shipping
NCP1203P40G PDIP--8
(Pb--Free)
NCP1203D40R2G SOIC--8
(Pb--Free)
NCP1203P60G PDIP--8
(Pb--Free)
NCP1203D60R2 SOIC--8 2500 Units / Tape & Reel
NCP1203D60R2G SOIC--8
(Pb--Free)
NCP1203P100G PDIP --8
(Pb--Free)
NCP1203D100R2G SOIC--8
(Pb--Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
50 Units / Rail
2500 Units / Tape & Reel
50 Units / Rail
2500 Units / Tape & Reel
50 Units / Rail
2500 Units / Tape & Reel
†
http://onsemi.com
13
-- Z --
-- Y --
NCP1203
PACKAGE DIMENSIONS
SOIC--8 NB
CASE 751--07
ISSUE AJ
-- X --
B
H
A
58
1
4
G
D
0.25 (0.010) Z
M
S
Y
0.25 (0.010)
C
SEATING
PLANE
SXS
M
M
Y
N
X45
_
0.10 (0.004)
M
SOLDERING FOOTPRINT*
K
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION .
6. 751--01 THRU 751-- 06 ARE OBSOLETE. NEW
STANDARD IS 751 --07.
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0808
____
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
INCHES
1.52
0.060
7.0
0.275
0.6
0.024
4.0
0.155
1.270
0.050
SCALE 6:1
inches
mm
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
14
NOTE 5
l
D
D1
14
TOP VIEW
e/2
NCP1203
PACKAGE DIMENSIONS
8LEADPDIP
CASE 626--05
ISSUE M
NOTES:
A
58
E
E1
F
c
E2
END VIEW
NOTE 3
A
L
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSION E IS MEASURED WITH THE LEADS RESTRAINED PARALLEL AT WIDTH E2.
4. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM MIN NOM MAX
A -- -- -- -- -- -- -- -- 0 . 2 1 0
A1 0.015 -------- --------
b 0.014 0.018 0.022
C 0.008 0.010 0.014
D 0.355 0.365 0.400
D1 0.005 -------- --------
E 0.300 0.310 0.325
E1 0.240 0.250 0.280 6.10 6.35 7.11
E2
E3 -- -- -- -- -- -- -- -- 0 . 4 3 0 -- -- -- -- -- -- -- -- 1 0 . 9 2
e 0.100 BSC
L 0.115 0.130 0.150
INCHES
0.300 BSC 7.62 BSC
MILLIMETERS
MIN NOM MAX
-- -- -- -- -- -- -- -- 5 . 3 3
0 . 3 8 -- -- -- -- -- -- -- --
0.35 0.46 0.56
0.20 0.25 0.36
9.02 9.27 10.02
0 . 1 3 -- -- -- -- -- -- -- --
7.62 7.87 8.26
2.54 BSC
2.92 3.30 3.81
A1
e
8X
SIDE VIEW
SEATING
C
PLANE
b
M
0.010 CA
E3
END VIEW
SMARTMOS is a trademark of Motorola, Inc.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty,representation or guarantee regarding the suitabilityof its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical i mplant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303--675--2175 or 800-- 344--3860 Toll Free USA/Canada
Fax: 303--675--2176 or 800-- 344--3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
N. American Technical Support: 800 --282--9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81--3--5773-- 3850
http://onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loca
Sales Representative
NCP1203/D
15
Loading...