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ML4824

Power Factor Correction and PWM Controller
Combo

Features

• Internally synchronized PFC and PWM in one IC

• Low total harmonic distortion

• Reduces ripple current in the storage capacitor between
the PFC and PWM sections

• Average current, continuous boost leading edge PFC

• Fast transconductance error amp for voltage loop

• High efficiency trailing edge PWM can be configured for
current mode or voltage mode operation

• Average line voltage compensation with brownout
control

• PFC overvoltage comparator eliminates output
“runaway” due to load removal

• Current fed gain modulator for improved noise immunity

• Overvoltage protection, UVLO, and soft start

Block Diagram

15

2

4

3

7

8

6

5

9

V

FB

2.5V

I

AC

V

RMS

I

SENSE

RAMP 1

RAMP 2

V

DC

V

CC

SS

DC I

LIMIT

VEA

–
+

8V

50µA

8V

16

VEAO

GAIN

MODULATOR

1.25V

3.5kΩ

IEA

+

–

3.5kΩ

–

+

1

IEAO

(-2 VERSION ONLY)

–

+

POWER FACTOR CORRECTOR

+

–

OSCILLATOR

V

2.5V

x 2

–

FB

+

PULSE WIDTH MODULATOR

General Description

The ML4824 is a controller for power factor corrected,
switched mode power supplies. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk capacitors,
reduces power line loading and stress on the switching FETs,
and results in a power supply that fully complies with
IEC1000-2-3 specification. The ML4824 includes circuits
for the implementation of a leading edge, average current,
“boost” type power factor correction and a trailing edge,
pulse width modulator (PWM).

The device is av ailable in two versions; the ML4824-1 (f
= f

) and the ML4824-2 (f

PFC

switching frequency of the PWM allows the user to design
with smaller output components while maintaining the best
operating frequency for the PFC. An over-voltage compara­tor shuts down the PFC section in the event of a sudden
decrease in load. The PFC section also includes peak current
limiting and input voltage brown-out protection. The PWM
section can be operated in current or voltage mode at up to
250kHz and includes a duty cycle limit to prevent trans­former saturation.

OVP

+

2.7V

–

–1V

+

–

PFC I

LIMIT

DUTY CYCLE

LIMIT

VIN OK

1V

–

+

DC I

LIMIT

V

CCZ

V

CCZ

13.5V

PWM

= 2 x f

SRQ

SRQ

SRQ

UVLO

). Doubling the

PFC

13

V

CC

7.5V

REFERENCE

Q

Q

PWM OUT

Q

PFC OUT

V

REF

PWM

14

12

11

REV. 1.0.6 11/7/03

ML4824 PRODUCT SPECIFICATION

Pin Configuration

ML4824

16-Pin PDIP (P16)

16-Pin Wide SOIC (S16W)

IEAO

I

AC

I

SENSE

V

RMS

SS

V

DC

RAMP 1
RAMP 2

1
2
3
4
5
6
7
8

TOP VIEW

16

VEAO

15

V

FB

14

V

REF

13

V

CC

12

PFC OUT

11

PWM OUT

10

GND

9

DC I

LIMIT

Pin Description

PIN NAME FUNCTION

1 IEAO PFC transconductance current error amplifier output
2I
3I
4V

AC
SENSE

RMS

5 SS Connection point for the PWM soft start capacitor
6V

DC

7 RAMP 1 Oscillator timing node; timing set by R
8 RAMP 2 When in current mode, this pin functions as as the current sense input; when in voltage

9 DC I

LIMIT

10 GND Ground
11 PWM OUT PWM driver output
12 PFC OUT PFC driver output
13 V
14 V
15 V

CC
REF
FB

16 VEAO PFC transconductance voltage error amplifier output

PFC gain control reference input
Current sense input to the PFC current limit comparator
Input for PFC RMS line voltage compensation

PWM voltage feedback input

C

T

T

mode, it is the PWM input from PFC output (feed forward ramp).
PWM current limit comparator input

Positive supply (connected to an internal shunt regulator)
Buffered output for the internal 7.5V reference
PFC transconductance voltage error amplifier input

2

REV. 1.0.6 11/7/03

∆

∆

Ω

PRODUCT SPECIFICATION ML4824

Absolute Maximum Ratings

Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum
ratings are stress ratings only and functional device operation is not implied.

Parameter Min. Max. Units

V

Shunt Regulator Current 55 mA

CC

I
Voltage on Any Other Pin GND – 0.3 V
I
I
Peak PFC OUT Current, Source or Sink 500 mA
Peak PWM OUT Current, Source or Sink 500 mA
PFC OUT, PWM OUT Energy Per Cycle 1.5 µJ
Junction Temperature 150 °C
Storage Temperature Range –65 150 °C
Lead Temperature (Soldering, 10 sec) 260 °C
Thermal Resistance ( θ

Plastic DIP
Plastic SOIC

Voltage –35 V

SENSE

+ 0.3 V

CCZ

REF

Input Current 10 mA

AC

)

JA

20 mA

80

105

°C/W
°C/W

Operating Conditions

Temperature Range

Parameter Min. Max. Units

ML4824CX 0 70 °C
ML4824IX –40 85 °C

Electrical Characteristics

Unless otherwise specified, I

Symbol Parameter Conditions Min. Typ. Max. Units
Voltage Error Amplifier

Input Voltage Range 0 7 V
Transconductance V
Feedback Reference Voltage 2.46 2.53 2.60 V
Input Bias Current Note 2 -0.3 –1.0 µA
Output High Voltage 6.0 6.7 V
Output Low Voltage 0.6 1.0 V
Source Current
Sink Current
Open Loop Gain 60 75 dB
Power Supply Rejection Ratio V

Current Error Amplifier

Input Voltage Range –1.5 2 V
Transconductance V
Input Offset Voltage 0 8 15 mV

= 25mA, R

CC

= 52.3k Ω , C

T

NON INV

V

= ±0.5V, V

IN

V

= ±0.5V, V

IN

CCZ

NON INV

= 470pF, T

T

= V

- 3V < V

= V

= Operating Temperature Range (Note 1)

A

, VEAO = 3.75V 50 85 120 µ

INV

= 6V –40 –80 µA

OUT

= 1.5V 40 80 µA

OUT

< V

CC

, VEAO = 3.75V 130 195 310 µ

INV

- 0.5V 60 75 dB

CCZ

Ω

REV. 1.0.6 11/7/03

3

∆

∆

∆

ML4824 PRODUCT SPECIFICATION

Electrical Characteristics

Unless otherwise specified, I

CC

(continued)

= 25mA, R

= 52.3k Ω , C

T

= 470pF, TA = Operating Temperature Range (Note 1)

T

Symbol Parameter Conditions Min. Typ. Max. Units

Input Bias Current –0.5 –1.0 µA
Output High Voltage 6.0 6.7 V
Output Low Voltage 0.6 1.0 V
Source Current
Sink Current

V

= ±0.5V, V

IN

V

= ±0.5V, V

IN

= 6V –40 –90 µA

OUT

= 1.5V 40 90 µA

OUT

Open Loop Gain 60 75 dB
Power Supply Rejection Ratio V

CCZ

- 3V < V

CC

< V

- 0.5V 60 75 dB

CCZ

OVP Comparator

Threshold Voltage 2.6 2.7 2.8 V
Hysteresis 80 115 150 mV

PFC I

Comparator

LIMIT

Threshold Voltage –0.8 –1.0 –1.15 V

(PFC I

LIMIT

V

TH

- Gain

100 190 mV

Modulator Output)
Delay to Output 150 300 ns

DC I

Comparator

LIMIT

Threshold Voltage 0.97 1.02 1.07 V
Input Bias Current ±0.3 ±1 µA
Delay to Output 150 300 ns

V

OK Comparator

IN

Threshold Voltage 2.4 2.5 2.6 V
Hysteresis 0.8 1.0 1.2 V

Gain Modulator

Gain (Note 3) I

= 100µA, V

AC

I

= 50µA, V

AC

I

= 50µA, V

AC

I

= 100µA, V

AC

RMS
RMS
RMS

RMS

= V

= 0V 0.36 0.55 0.66

FB

= 1.2V, V
= 1.8V, V

= 3.3V, V

= 0V 1.20 1.80 2.24

FB

= 0V 0.55 0.80 1.01

FB

= 0V 0.14 0.20 0.26

FB

Bandwidth IAC = 100µA 10 MHz
Output Voltage I

= 250µA, V

AC

V

= 0V

FB

RMS

= 1.15V,

0.74 0.82 0.90 V

Oscillator

Initial Accuracy T
Voltage Stability V

= 25°C 717681kHz

A

CCZ

- 3V < V

CC

< V

- 0.5V 1 %

CCZ

Temperature Stability 2 %
Total Variation Line, Temp 68 84 kHz
Ramp Valley to Peak Voltage 2.5 V
Dead Time PFC Only 270 370 470 ns
C

Discharge Current V

T

RAMP 2

= 0V, V

RAMP 1

= 2.5V 4.5 7.5 9.5 mA

Reference

Output Voltage T

= 25˚C, I(V

A

) = 1mA 7.4 7.5 7.6 V

REF

4

REV. 1.0.6 11/7/03

PRODUCT SPECIFICATION ML4824

Electrical Characteristics (continued)

Unless otherwise specified, ICC = 25mA, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1)

Symbol Parameter Conditions Min. Typ. Max. Units

Line Regulation V
Load Regulation 1mA < I(V
Temperature Stability 0.4 %
Total Variation Line, Load, Temp 7.35 7.65 V
Long Term Stability T

PFC

Minimum Duty Cycle V
Maximum Duty Cycle V
Output Low Voltage I

Output High Voltage I

Rise/Fall Time CL = 1000pF 50 ns

PWM

Duty Cycle Range ML4824-1 0-44 0-47 0-50 %

Output Low Voltage I

Output High Voltage I

Rise/Fall Time CL = 1000pF 50 ns

Supply

Shunt Regulator Voltage (V
V

Load Regulation 25mA < ICC < 55mA ±100 ±300 mV

CCZ

V

Total Variation Load, Temp 12.4 14.6 V

CCZ

) 12.8 13.5 14.4 V

CCZ

Start-up Current VCC = 11.8V, CL = 0 0.7 1.0 mA
Operating Current VCC < V
Undervoltage Lockout Threshold 12 13 14 V
Undervoltage Lockout Hysteresis 2.7 3.0 3.3 V

Notes

1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

2. Includes all bias currents to other circuits connected to the V

3. Gain = K x 5.3V; K = (I

GAINMOD

- I

OFFSET

) x IAC x (VEAO - 1.5V)-1.

- 3V < VCC < V

CCZ

) < 20mA 2 15 mV

REF

= 125˚C, 1000 Hours 5 25 mV

J

> 4.0V 0 %

IEAO

< 1.2V 90 95 %

IEAO

= -20mA 0.4 0.8 V

OUT

I

= -100mA 0.8 2.0 V

OUT

I

= 10mA, VCC = 8V 0.7 1.5 V

OUT

= 20mA 10 10.5 V

OUT

I

= 100mA 9.5 10 V

OUT

- 0.5V 2 10 mV

CCZ

ML4824-2 0-37 0-40 0-45 %

= -20mA 0.4 0.8 V

OUT

I

= -100mA 0.8 2.0 V

OUT

I

= 10mA, VCC = 8V 0.7 1.5 V

OUT

= 20mA 10 10.5 V

OUT

I

= 100mA 9.5 10 V

OUT

- 0.5V, CL = 0 16 19 mA

CCZ

pin.

FB

REV. 1.0.6 11/7/03 5