ON MC74VHC1G50DF, MC74VHC1G50DT Schematic

MC74VHC1G50

Buffer

The MC74VHC1G50 is an advanced high speed CMOS buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

The internal circuit is composed of three stages, including a buffered output which provides high noise immunity and stable output.

The MC74VHC1G50 input structure provides protection when voltages up to 7.0 V are applied, regardless of the supply voltage. This allows the MC74VHC1G50 to be used to interface 5.0 V circuits to 3.0 V circuits.

• High Speed: t

• Low Power Dissipation: I

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

• Pin and Function Compatible with Other Standard Logic Families

• Chip Complexity: FET = 104; Equivalent Gate = 26

• These devices are available in Pb--free package(s). Specifications herein

apply to both standard and Pb--free devices. Please see our website at www.onsemi.com for specific Pb--free orderable part numbers, or contact your local ON Semiconductor sales office or representative.

= 3.5 ns (Typ) at VCC=5V

PD

=1mA(Max)atTA=25°C

CC

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SC--88A / SOT--353/SC--70

DF SUFFIX

CASE 419A

TSOP-- 5/SOT--23/SC--59

DT SUFFIX

CASE 483

MARKING

DIAGRAMS

d

VR

Pin 1 d = Date Code

d

VR

Pin 1 d = Date Code

1

NC

IN A

2

3

GND

Figure 1. Pinout (Top View)

IN A

1

Figure 2. Logic Symbol

5

4

OUT Y

V

CC

OUT Y

PIN ASSIGNMENT

1

2

3GND

4

5V

NC

IN A

OUT Y

CC

FUNCTION TABLE

A Input Y Output

L

H

L

H

ORDERING INFORMATION

See detailed ordering and shippinginformation in the package dimensions section on page 4 of this data sheet.

March, 2006 -- Rev. 12

1 Publication Order Number:

MC74VHC1G50/D

MC74VHC1G50

MAXIMUM RATINGS (Note 1)

Symbol

V

CC

V

IN

V

OUT

I

IK

I

OK

I

OUT

I

CC

P

D

θ

JA

T

L

T

J

T

stg

V

ESD

I

Latch--Up

DC Supply Voltage --0.5to+7.0 V

DC Input Voltage --0.5to+7.0 V

DC Output Voltage VCC=0

Input Diode Current -- 2 0 mA

Output Diode Current V

DC Output Current, per Pin +25 mA

DC Supply Current, VCCand GND +50 mA

Power dissipation in still air SC--88A, TSOP-- 5 200 mW

Thermal resistance SC--88A, TSOP--5 333 °C/W

Lead temperature, 1 mm from case for 10 s 260 °C

Junction temperature under bias +150 °C

Storage temperature --65 to +150 °C

ESD Withstand Voltage Human Body Model (Note 2)

Latch--Up Performance Above VCCand Below GND at 125°C(Note5) ±500 mA

1. Maximum Ratings are those values beyond which damage to the device may occur.Exposure to these conditions or conditions beyond those

indicated may adversely affect device reliability. Functional operation under absolute--maximum--rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions.

2. Tested to EIA/JESD22--A114--A

3. Tested to EIA/JESD22--A115--A

4. Tested to JESD22--C101--A

5. Tested to EIA/JESD78

Characteristics Value Unit

High or Low State

< GND; V

OUT

OUT>VCC

Machine Model (Note 3)

Charged Device Model (Note 4)

--0.5to7.0

--0.5toV

CC

+0.5

+20 mA

> 2000

> 200

N/A

V

RECOMMENDED OPERATING CONDITIONS

Symbol Characteristics Min Max Unit

V

CC

V

IN

V

OUT

T

A

tr,t

DC Supply Voltage 2.0 5.5 V

DC Input Voltage 0.0 5.5 V

DC Output Voltage 0.0 V

CC

Operating Temperature Range -- 5 5 +125 °C

Input Rise and Fall Time VCC=3.3V± 0.3 V

f

V

=5.0V± 0.5 V

CC

0 0

100

20

Device Junction Temperature versus Time to 0.1% Bond Failures

Junction

Temperature °C

Time, Hours Time, Years

80 1,032,200 117.8

90 419,300 47.9

100 178,700 20.4

110 79,600 9.4

120 37,000 4.2

130 17,800 2.0

140 8,900 1.0

FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR

= 130 C°

J

T

J

T

=110 C°

= 120 C°

1

NORMALIZED FAILURE RATE

1 10 100

TIME, YEARS

Figure 3. Failure Rate vs. Time

C°

=80

=90

= 100 C°

J

T

J

T

1000

Junction Temperature

V

ns/V

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2

DC ELECTRICAL CHARACTERISTICS

Symbol Parameter Test Conditions

V

IH

V

IL

V

OH

V

OL

I

IN

I

CC

Minimum High--Level Input Voltage

Maximum Low--Level Input Voltage

Minimum High--Level Output Voltage

IN=VIH

or V

IL

V

Maximum Low--Level Output Voltage

IN=VIH

or V

IL

V

Maximum Input Leakage Current

Maximum Quiescent Supply Current

VIN=VIHor V IOH=--50mA

VIN=VIHor V IOH=--4mA

=--8mA

I

OH

VIN=VIHor V IOL=50mA

VIN=VIHor V IOL=4mA

=8mA

I

OL

IL

VIN=5.5VorGND 0to

VIN=VCCor GND 5.5 1.0 20 40

MC74VHC1G50

V

CC

(V)

2.0

3.0

4.5

5.5

2.0

3.0

4.5

5.5

2.0

3.0

4.5

3.0

4.5

2.0

3.0

4.5

3.0

4.5

5.5

TA=25°C TA≤ 85°C -- 5 5 ≤ TA≤ 125°C

Min Typ Max Min Max Min Max

1.5

2.1

3.15

3.85

1.9

2.0

2.9

3.0

4.4

4.5

2.58

3.94

0.0

0.5

0.9

1.35

1.65

0.1

0.36

1.5

2.1

3.15

3.85

0.5

0.9

1.35

1.65

1.9

2.9

4.4

2.48

3.80

0.1

0.44

1.5

2.1

3.15

3.85

0.5

0.9

1.35

1.65

1.9

2.9

4.4

2.34

3.66

0.1

0.52

±0.1 ±1.0 ±1.0

Unit

V

mA

AC ELECTRICAL CHARACTERISTICS C

= 50 pF, Input tr=tf=3.0ns

load

TA=25°C TA≤ 85°C -- 5 5 ≤ TA≤ 125°C

Symbol Parameter Test Conditions

t

PLH

t

PHL

,

Maximum Propagation Delay, Input A to

Y

VCC=3.3± 0.3 V CL=15pF

C

VCC=5.0± 0.5 V CL=15pF

C

IN

Maximum Input Capacitance

=50pF

L

=50pF

L

Min Typ Max Min Max Min Max

4.5

6.4

3.5

4.5

7.1

10.6

5.5

7.5

8.5

12.0

6.5

8.5

10.0

14.5

8.0

10.0

4 10 10 10 pF

Unit

ns

Typical @ 25°C, VCC=5.0V

C

PD

Power Dissipation Capacitance (Note 6)

8.0

pF

6. CPDis defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: I power consumption; P

D=CPD

¯ V

CC

2

¯ fin+ICC¯ VCC.

=CPD¯ VCC¯ fin+ICC.CPDis used to determine the no --load dynamic

)

CC(OPR

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3

ON MC74VHC1G50DF, MC74VHC1G50DT Schematic [ru]