ON MC74VHC1G08DFT1G, MC74VHC1G08DTT1G, NLVVHC1G08DFT1G Schematic [ru]
MC74VHC1G08
Single 2-Input AND Gate
The MC74VHC1G08 is an advanced high speed CMOS 2−input
AND gate fabricated with silicon gate CMOS technology.
The internal circuit is composed of multiple stages, including a
buffer output which provides high noise immunity and stable output.
The MC74VHC1G08 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G08 to be used to interface 5.0 V circuits to
3.0 V circuits.
Features
• High Speed: t
• Low Power Dissipation: I
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 62
• These Devices are Pb−Free and are RoHS Compliant
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
= 3.5 ns (Typ) at VCC = 5.0 V
PD
= 1.0 mA (Max) at TA = 25°C
CC
IN B
1
V
5
CC
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MARKING
DIAGRAMS
5
M
SC−88A / SOT−353 / SC−70
DF SUFFIX
CASE 419A
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
CASE 483
V2 = Device Code
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
V2 M G
G
1
5
V2 M G
G
1
IN A
2
GND
3
Figure 1. Pinout (Top View)
IN A
IN B
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2013
February, 2013 − Rev. 20
PIN ASSIGNMENT
1
2
3 GND
4
OUT Y
4
5V
IN B
IN A
OUT Y
CC
FUNCTION TABLE
Inputs Output
AB
&
OUT Y
1 Publication Order Number:
L
L
H
H
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
L
H
L
H
Y
L
L
L
H
MC74VHC1G08/D
MC74VHC1G08
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
V
OUT
I
I
OK
I
OUT
I
CC
T
STG
T
T
q
P
MSL Moisture Sensitivity Level 1
F
V
ESD
I
LATCHUP
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
V
V
V
OUT
T
t
r
Device Junction Temperature versus
Time to 0.1% Bond Failures
Temperature °C
DC Supply Voltage *0.5 to )7.0 V
CC
DC Input Voltage −0.5 to +7.0 V
IN
DC Output Voltage *0.5 to V
DC Input Diode Current −20 mA
IK
CC
DC Output Diode Current $20 mA
DC Output Sink Current $12.5 mA
DC Supply Current per Supply Pin $25 mA
Storage Temperature Range *65 to )150 °C
Lead Temperature, 1 mm from Case for 10 Seconds 260 °C
L
Junction Temperature Under Bias )150 °C
J
Thermal Resistance SC70−5/SC−88A (Note 1)
JA
Power Dissipation in Still Air at 85°CSC70−5/SC−88A
D
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
R
TSOP−5
TSOP−5
ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
350
230
150
200
u2000
u200
N/A
Latchup Performance Above VCC and Below GND at 125°C (Note 5) $500 mA
DC Supply Voltage 2.0 5.5 V
CC
DC Input Voltage 0.0 5.5 V
IN
DC Output Voltage 0.0 V
Operating Temperature Range −55 +125 °C
A
, t
Input Rise and Fall Time VCC = 3.3 V ± 0.3 V
f
V
= 5.0 V ± 0.5 V
CC
0
0
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Junction
Time, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
= 130 C°
J
T
J
J
T
T
= 110 C°
= 120 C°
1
NORMALIZED FAILURE RATE
1 10 100
TIME, YEARS
C°
= 90
= 100 C°
J
J
T
T
120 37,000 4.2
130 17,800 2.0
Figure 3. Failure Rate vs. Time
Junction Temperature
140 8,900 1.0
)0.5 V
°C/W
CC
100
20
C°
= 80
J
T
1000
mW
V
V
ns/V
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DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
V
V
V
V
I
Minimum High−Level
IH
Input Voltage
Maximum Low−Level
IL
Input Voltage
Minimum High−Level
OH
Output Voltage
V
Maximum Low−Level
OL
Output Voltage
V
I
Maximum Input
IN
Leakage Current
Maximum Quiescent
CC
Supply Current
= VIH or V
IN
= VIH or V
IN
VIN = VIH or V
IL
VIN = VIH or V
IL
IOH = −50 mA
IL
IOH = −4 mA
IOH = −8 mA
VIN = VIH or V
IL
VIN = VIH or V
IL
IOL = 50 mA
IL
IOL = 4 mA
IOL = 8 mA
VIN = 5.5 V or GND 0 to 5.5 $0.1 $1.0 $1.0
VIN = VCC or GND 5.5 1.0 10 40
MC74VHC1G08
V
CC
(V)
2.0
3.0
4.5
5.5
2.0
3.0
4.5
5.5
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
TA = 255C TA v 855C *555C to 1255C
Min Typ Max Min Max Min Max
1.5
2.1
3.15
3.85
1.9
2.9
4.4
2.58
3.94
2.0
3.0
4.5
0.0
0.0
0.0
0.5
0.9
1.35
1.65
0.1
0.1
0.1
0.36
0.36
1.5
2.1
3.15
3.85
1.9
2.9
4.4
2.48
3.80
0.5
0.9
1.35
1.65
0.1
0.1
0.1
0.44
0.44
1.5
2.1
3.15
3.85
1.9
2.9
4.4
2.34
3.66
0.5
0.9
1.35
1.65
0.1
0.1
0.1
0.52
0.52
Unit
V
V
V
V
mA
mA
AC ELECTRICAL CHARACTERISTICS Input t
Symbol
t
PLH
t
PHL
C
IN
,
Parameter
Maximum Propagation Delay,
Input A or B to Y
Maximum Input Capacitance
Test Conditions
VCC = 3.3 ± 0.3 V CL = 15 pF
VCC = 5.0 ± 0.5 V CL = 15 pF
r
= t
= 3.0 ns
f
C
L
C
L
= 50 pF
= 50 pF
Min
TA = 25°C
Typ
4.1
5.9
3.5
4.2
5.5
Max
8.8
12.3
5.9
7.9
10
TA ≤ 85°C
Min
−55 ≤ TA ≤ 125°C
Max
10.5
14.0
7.0
9.0
10
Min
Max
12.5
16.5
9.0
11.0
10
Unit
ns
pF
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Note 6)
11
pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
power consumption; P
= CPD V
D
2
fin + ICC VCC.
CC
= CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
)
CC(OPR
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