ON MC33151DG, MC33151VDR2G, MC34151DG, MC33151PG, MC34151PG Schematic [ru]

MC34151, MC33151

High Speed Dual
MOSFET Drivers

The MC34151/MC33151 are dual inverting high speed drivers
specifically designed for applications that require low current digital
circuitry to drive large capacitive loads with high slew rates. These
devices feature low input current making them CMOS and LSTTL
logic compatible, input hysteresis for fast output switching that is
independent of input transition time, and two high current totem pole
outputs ideally suited for driving power MOSFETs. Also included is
an undervoltage lockout with hysteresis to prevent erratic system
operation at low supply voltages.

Typical applications include switching power supplies, dc to dc
converters, capacitor charge pump voltage doublers/inverters, and
motor controllers.

These devices are available in dual−in−line and surface mount
packages.

Features

• Two Independent Channels with 1.5 A Totem Pole Output

• Output Rise and Fall Times of 15 ns with 1000 pF Load

• CMOS/LSTTL Compatible Inputs with Hysteresis

• Undervoltage Lockout with Hysteresis

• Low Standby Current

• Efficient High Frequency Operation

• Enhanced System Performance with Common Switching Regulator

Control ICs

• Pin Out Equivalent to DS0026 and MMH0026

• These are Pb−Free and Halide−Free Devices

V

CC

6

+

+

Logic Input A

Logic Input B

-

+

+

2

+

4

5.7V

+

Drive Output A

7

100k

+

Drive Output B

5

100k

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MARKING

DIAGRAMS

8

YYWWG

1

G

MC3x151P

AWL

8

3151V

ALYWG

G

1

PDIP−8

P SUFFIX

8

1

8

1

(Note: Microdot may be in either location)

CASE 626

8

SOIC−8

D SUFFIX

CASE 751

x = 3 or 4
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package

3x151

ALYWG

1

MC3x151 MC33151V

PIN CONNECTIONS

1 8 N.C.N.C.

2 7 Drive Output ALogic Input A

GND

36V

4 5 Drive Output BLogic Input B

(Top View)

CC

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.

GND

Figure 1. Representative Block Diagram

© Semiconductor Components Industries, LLC, 2013

August, 2013 − Rev. 9

3

1 Publication Order Number:

MC34151/D

MC34151, MC33151

MAXIMUM RATINGS

Rating Symbol Value Unit

Power Supply Voltage V

Logic Inputs (Note 1) V

CC

in

Drive Outputs (Note 2)

Totem Pole Sink or Source Current
Diode Clamp Current (Drive Output to V

CC

)

I

O

I

O(clamp)

Power Dissipation and Thermal Characteristics

D Suffix SOIC−8 Package Case 751

Maximum Power Dissipation @ T

= 50°C

A

Thermal Resistance, Junction−to−Air

P

D

R

q

JA

P Suffix 8−Pin Package Case 626

Maximum Power Dissipation @ T
Thermal Resistance, Junction−to−Air

Operating Junction Temperature T

Operating Ambient Temperature

= 50°C

A

P

D

R

q

JA

J

T

A

MC34151
MC33151
MC33151V

Storage Temperature Range T

Electrostatic Discharge Sensitivity (ESD) (Note 3)

stg

ESD
Human Body Model (HBM)
Machine Model (MM)
Charged Device Model (CDM)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

1. For optimum switching speed, the maximum input voltage should be limited to 10 V or V

2. Maximum package power dissipation limits must be observed.

, whichever is less.

CC

3. ESD protection per JEDEC Standard JESD22−A114−F for HBM
per JEDEC Standard JESD22−A115−A for MM
per JEDEC Standard JESD22−C101D for CDM.

20 V

−0.3 to V

CC

1.5

1.0

0.56
180

1.0

100

W

°C/W

W

°C/W

+150 °C

°C

0 to +70

−40 to +85

−40 to +125

−65 to +150 °C

2000

200

1500

V

A

V

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2

MC34151, MC33151

ELECTRICAL CHARACTERISTICS (V

= 12 V, for typical values TA = 25°C, for min/max values TA is the only operating

CC

ambient temperature range that applies [Note 3], unless otherwise noted.)

Characteristics

Symbol Min Typ Max Unit

LOGIC INPUTS

Input Threshold Voltage − Output Transition High to Low State

Output Transition Low to High State

Input Current − High State (VIH = 2.6 V)

Input Current − Low State (V

= 0.8 V)

IL

V

IH

V

IL

I

IH

I

IL

−

0.8

−

−

DRIVE OUTPUT

Output Voltage − Low State (I

Output Voltage − Low State (I
Output Voltage − Low State (I
Output Voltage − High State (I
Output Voltage − High State (I
Output Voltage − High State (I

= 10 mA)

Sink

= 50 mA)

Sink

= 400 mA)

Sink

Source

Source

Source

= 10 mA)
= 50 mA)
= 400 mA)

Output Pulldown Resistor R

V

OL

−

−

−

V

OH

10.5

10.4

9.5

PD

− 100 −

SWITCHING CHARACTERISTICS (TA = 25°C)

= 2.5 nF

L

= 2.5 nF

= 1.0 nF)

L

t

PLH(in/out)

t

PHL(in/out)

t

r

t

f

−

−

−

−

−

−

Propagation Delay (10% Input to 10% Output, C

Logic Input to Drive Output Rise
Logic Input to Drive Output Fall

Drive Output Rise Time (10% to 90%) CL = 1.0 nF

Drive Output Rise Time (10% to 90%) C

Drive Output Fall Time (90% to 10%) CL = 1.0 nF

Drive Output Fall Time (90% to 10%) C

L

TOTAL DEVICE

Power Supply Current

Standby (Logic Inputs Grounded)
Operating (C

= 1.0 nF Drive Outputs 1 and 2, f = 100 kHz)

L

Operating Voltage V

I

CC

−

−

CC

6.5 − 18 V

1. For optimum switching speed, the maximum input voltage should be limited to 10 V or VCC, whichever is less.

2. Maximum package power dissipation limits must be observed.

3. T

=0°C for MC34151 T

low

−40°C for MC33151 +85°C for MC33151

= +70°C for MC34151

high

1.75

2.6

1.58

20020500

100

0.8

1.2

1.1

1.5

1.7

2.5

11.2

11.1

10.9

3536100

100

14

30

31

16

30

32

6.0

10.51015

V

−

mA

V

−

−

−

kW

ns

ns

−

ns

−

mA

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3

Logic Input

MC34151, MC33151

12

V

4.7 0.1

+

6

+

+

-

+

5.7V

+

2

+

Drive Output

7

50 C

+

4

3

100k

+

5

100k

L

Logic Input

t

r

, tf ≤ 10 ns

5.0 V

0 V

10%

t

PHL

90%

t

PLH

90%

Drive Output

t

f

10%

Figure 2. Switching Characteristics Test Circuit Figure 3. Switching Waveform Definitions

2.4

VCC = 12 V
T

= 25°C

2.0

A

1.6

1.2

0.8

, INPUT CURRENT (mA)

in

I

0.4

0

0 2.0 4.0 6.0 8.0 10 12 -55 -25 0 25 50 75 100 125

Vin, INPUT VOLTAGE (V)

Figure 4. Logic Input Current versus

Input Voltage

2.2

2.0

1.8

1.6

1.4

, INPUT THRESHOLD VOLTAGE (V)

1.2

th

V

1.0

VCC = 12 V

Upper Threshold

Low State Output

Lower Threshold

High State Output

TA, AMBIENT TEMPERATURE (°C)

Figure 5. Logic Input Threshold Voltage

versus Temperature

t

r

200

Overdrive Voltage is with Respect

to the Logic Input Lower Threshold

160

VCC = 12 V
CL = 1.0 nF
T

= 25°C

A

120

80

40

, DRIVE OUTPUT PROPAGATION DELAY (ns)

V

0

-1.6 -1.2 -0.8 -0.4 0 0 1.0 2.0 3.0 4.0
V

, INPUT OVERDRIVE VOLTAGE BELOW LOWER THRESHOLD (V)

PLH(IN/OUT)

in

t

th(lower)

Figure 6. Drive Output Low−to−High Propagation

Delay versus Logic Overdrive Voltage

200

160

Overdrive Voltage is with Respect

to the Logic Input Lower Threshold

VCC = 12 V
C
T

120

80

40

, DRIVE OUTPUT PROPAGATION DELAY (ns)

V

0

Vin, INPUT OVERDRIVE VOLTAGE ABOVE UPPER THRESHOLD (V)

PHL(IN/OUT)

t

th(upper)

Figure 7. Drive Output High−to−Low Propagation

Delay versus Logic Input Overdrive Voltage

= 1.0 nF

L

= 25°C

A

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4

MC34151, MC33151

90%

10%

Logic Input

Drive Output

VCC = 12 V
V

= 5 V to 0 V

in

C

= 1.0 nF

L

TA = 25°C

50 ns/DIV

Figure 8. Propagation Delay Figure 9. Drive Output Clamp Voltage

0

-1.0

V

CC

Source Saturation

(Load to Ground)

-2.0

-3.0

3.0

2.0

, OUTPUT SATURATION VOLTAGE(V)

1.0

sat

V

0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Sink Saturation

(Load to V

CC

IO, OUTPUT LOAD CURRENT (A)

GND

)

VCC = 12 V
80 ms Pulsed Load
120 Hz Rate
T

= 25°C

A

3.0

2.0

High State Clamp

(Drive Output Driven Above V

)

CC

VCC = 12 V
80 ms Pulsed Load
120 Hz Rate
T

= 25°C

1.0

V

0

CC

, OUTPUT CLAMP VOLTAGE (V)

0

clamp

V

-1.0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

GND

, OUTPUT LOAD CURRENT (A)

I

O

(Drive Output Driven Below Ground)

A

Low State Clamp

versus Clamp Current

0

Source Saturation

-0.5

-0.7

-0.9

(Load to Ground)

V

CC

I

source

I

source

= 10 mA

= 400 mA

-1.1

1.9

1.7

I

= 400 mA

sink

1.5

1.0

, OUTPUT SATURATION VOLTAGE(V)

0.8

sat

V

Sink Saturation

0.6
(Load to V

0

-55 -25 0 25 50 75 100 125

)

CC

I

sink

GND

= 10 mA

TA, AMBIENT TEMPERATURE (°C)

VCC = 12 V

90%

10%

Figure 10. Drive Output Saturation Voltage

versus Load Current

Figure 11. Drive Output Saturation Voltage

versus Temperature

90%

VCC = 12 V
Vin = 5 V to 0 V
C

= 1.0 nF

L

T

= 25°C

A

VCC = 12 V
V

= 5 V to 0 V

in

C

= 1.0 nF

L

T

10 ns/DIV

= 25°C

A

10%

10 ns/DIV

Figure 12. Drive Output Rise Time Figure 13. Drive Output Fall Time

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5

MC34151, MC33151

80

VCC = 12 V
V

= 0 V to 5.0 V

IN

60

T

= 25°C

A

40

t

20

f

-t , OUTPUT RISE‐FALL TIME(ns)
r

t

0

0.1 1.0 10 0.1 1.0 10
CL, OUTPUT LOAD CAPACITANCE (nF)

f

t

r

Figure 14. Drive Output Rise and Fall Time

versus Load Capacitance

80

Both Logic Inputs Driven
0 V to 5.0 V,
50% Duty Cycle

60

Both Drive Outputs Loaded
T

= 25°C

A

= 18 V, CL = 2.5 nF

1 - V

40

, SUPPLY CURRENT (mA)

20

CC

I

CC

2 - V

= 12 V, CL = 2.5 nF

CC

3 - V

= 18 V, CL = 1.0 nF

CC

4 - V

= 12 V, CL = 1.0 nF

CC

1

2

3

4

80

VCC = 12 V
Both Logic Inputs Driven
0 V to 5.0 V

60

50% Duty Cycle
Both Drive Outputs Loaded
T

= 25°C

A

40

, SUPPLY CURRENT (mA)

20

CC

I

0

f = 500 kHz

, OUTPUT LOAD CAPACITANCE (nF)

C

L

f = 200 kHz

f = 50 kHz

Figure 15. Supply Current versus Drive Output

Load Capacitance

8.0
TA = 25°C

6.0

4.0

, SUPPLY CURRENT (mA)

2.0

CC

I

Logic Inputs at V

Low State Drive Outputs

CC

Logic Inputs Grounded

High State Drive Outputs

0

10 k

100 1.0 M

f, INPUT FREQUENCY (Hz)

0

0 4.0 8.0 12 16

VCC, SUPPLY VOLTAGE (V)

Figure 16. Supply Current versus Input Frequency Figure 17. Supply Current versus Supply Voltage

APPLICATIONS INFORMATION

Description

The MC34151 is a dual inverting high speed driver
specifically designed to interface low current digital
circuitry with power MOSFETs. This device is constructed
with Schottky clamped Bipolar Analog technology which
offers a high degree of performance and ruggedness in
hostile industrial environments.

Input Stage

The Logic Inputs have 170 mV of hysteresis with the input
threshold centered at 1.67 V. The input thresholds are
insensitive to V

making this device directly compatible

CC

with CMOS and LSTTL logic families over its entire
operating voltage range. Input hysteresis provides fast
output switching that is independent of the input signal
transition time, preventing output oscillations as the input
thresholds are crossed. The inputs are designed to accept a
signal amplitude ranging from ground to V

. This allows

CC

the output of one channel to directly drive the input of a
second channel for master−slave operation. Each input has
a 30 kW pulldown resistor so that an unconnected open input
will cause the associated Drive Output to be in a known high
state.

Output Stage

Each totem pole Drive Output is capable of sourcing and

sinking up to 1.5 A with a typical ‘on’ resistance of 2.4 W at

1.0 A. The low ‘on’ resistance allows high output currents
to be attained at a lower VCC than with comparative CMOS
drivers. Each output has a 100 kW pulldown resistor to keep
the MOSFET gate low when V

is less than 1.4 V. No over

CC

current or thermal protection has been designed into the
device, so output shorting to V

or ground must be

CC

avoided.

Parasitic inductance in series with the load will cause the

driver outputs to ring above V

during the turn−on

CC

transition, and below ground during the turn−off transition.
With CMOS drivers, this mode of operation can cause a
destructive output latchup condition. The MC34151 is
immune to output latchup. The Drive Outputs contain an
internal diode to V
transients. When operating with V

for clamping positive voltage

CC

at 18 V, proper power

CC

supply bypassing must be observed to prevent the output
ringing from exceeding the maximum 20 V device rating.
Negative output transients are clamped by the internal NPN
pullup transistor. Since full supply voltage is applied across

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6

MC34151, MC33151

the NPN pullup during the negative output transient, power
dissipation at high frequencies can become excessive.
Figures 20, 21, and 22 show a method of using external
Schottky diode clamps to reduce driver power dissipation.

Undervoltage Lockout

An undervoltage lockout with hysteresis prevents erratic
system operation at low supply voltages. The UVLO forces
the Drive Outputs into a low state as V

rises from 1.4 V

CC

to the 5.8 V upper threshold. The lower UVLO threshold is

5.3 V, yielding about 500 mV of hysteresis.

Power Dissipation

Circuit performance and long term reliability are
enhanced with reduced die temperature. Die temperature
increase is directly related to the power that the integrated
circuit must dissipate and the total thermal resistance from
the junction to ambient. The formula for calculating the
junction temperature with the package in free air is:

T

where: T

T
P

R

q

=TA + PD (R

J

= Junction Temperature

J

= Ambient Temperature

A

= Power Dissipation

D

Thermal Resistance Junction to Ambient

JA =

)

JA

q

There are three basic components that make up total
power to be dissipated when driving a capacitive load with
respect to ground. They are:

P

D =PQ

+ PC + P

T

where: PQ = Quiescent Power Dissipation

P

= Capacitive Load Power Dissipation

C

P

= Transition Power Dissipation

T

The quiescent power supply current depends on the
supply voltage and duty cycle as shown in Figure 17. The
device’s quiescent power dissipation is:

where: I

PQ = VCC I

= Supply Current with Low State Drive

CCL

(1−D) + I

CCL

CCH

(D)

Outputs

I

= Supply Current with High State Drive

CCH

Outputs

D = Output Duty Cycle

The capacitive load power dissipation is directly related
to the load capacitance value, frequency, and Drive Output
voltage swing. The capacitive load power dissipation per
driver is:

P

=VCC (VOH − VOL) CL f

C

where: V

= High State Drive Output Voltage

OH

V

= Low State Drive Output Voltage

OL

C

= Load Capacitance

L

f = frequency

When driving a MOSFET, the calculation of capacitive
load power P
gate to source capacitance C

is somewhat complicated by the changing

C

as the device switches. To aid

GS

in this calculation, power MOSFET manufacturers provide

gate charge information on their data sheets. Figure 18
shows a curve of gate voltage versus gate charge for the ON
Semiconductor MTM15N50. Note that there are three
distinct slopes to the curve representing different input
capacitance values. To completely switch the MOSFET
‘on’, the gate must be brought to 10 V with respect to the
source. The graph shows that a gate charge Q

of 110 nC is

g

required when operating the MOSFET with a drain to source
voltage V

16

12

8.0

4.0

, GATE-TO-SOURCE VOLTAGE (V)

GS

V

0

of 400 V.

DS

MTM15N50
I

= 15 A

D

TA = 25°C

V

CGS =

= 400 V

DS

D Q

D V

g

GS

VDS = 100 V

8.9 nF

2.0 nF

0 40 80 120 160

Qg, GATE CHARGE (nC)

Figure 18. Gate−To−Source Voltage

versus Gate Charge

The capacitive load power dissipation is directly related to
the required gate charge, and operating frequency. The
capacitive load power dissipation per driver is:

P

C(MOSFET)

= VC Qg f

The flat region from 10 nC to 55 nC is caused by the
drain−to−gate Miller capacitance, occurring while the
MOSFET is in the linear region dissipating substantial
amounts of power. The high output current capability of the
MC34151 is able to quickly deliver the required gate charge
for fast power efficient MOSFET switching. By operating
the MC34151 at a higher V

, additional charge can be

CC

provided to bring the gate above 10 V. This will reduce the
‘on’ resistance of the MOSFET at the expense of higher
driver dissipation at a given operating frequency.

The transition power dissipation is due to extremely short
simultaneous conduction of internal circuit nodes when the
Drive Outputs change state. The transition power
dissipation per driver is approximately:

PT = VCC (1.08 VCC CL f − 8 y 10−4)
P

must be greater than zero.

T

Switching time characterization of the MC34151 is
performed with fixed capacitive loads. Figure 14 shows that
for small capacitance loads, the switching speed is limited
by transistor turn−on/off time and the slew rate of the
internal nodes. For large capacitance loads, the switching
speed is limited by the maximum output current capability
of the integrated circuit.

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7

MC34151, MC33151

LAYOUT CONSIDERATIONS

High frequency printed circuit layout techniques are

imperative to prevent excessive output ringing and overshoot.

Do not attempt to construct the driver circuit on
wire−wrap or plug−in prototype boards. When driving

large capacitive loads, the printed circuit board must contain
a low inductance ground plane to minimize the voltage spikes
induced by the high ground ripple currents. All high current
loops should be kept as short as possible using heavy copper
runs to provide a low impedance high frequency path. For

V

CC

0.1

47

6

TL494

or

TL594

+

++

-

+

5.7V

+

2

100k100k

+

+

4

V

in

7

5

optimum drive performance, it is recommended that the
initial circuit design contains dual power supply bypass
capacitors connected with short leads as close to the V

CC

pin

and ground as the layout will permit. Suggested capacitors are
a low inductance 0.1 mF ceramic in parallel with a 4.7 mF
tantalum. Additional bypass capacitors may be required
depending upon Drive Output loading and circuit layout.

Proper printed circuit board layout is extremely
critical and cannot be over emphasized.

V

in

+

R

g

D

100k

1

1N5819

3

The MC34151 greatly enhances the drive capabilities of common switching
regulators and CMOS/TTL logic devices.

Figure 19. Enhanced System Performance with

Common Switching Regulators

+

+

7

100k100k

+

3

4 X

1N5819

+

5

Series gate resistor Rg may be needed to damp high frequency parasitic
oscillations caused by the MOSFET input capacitance and any series
wiring inductance in the gate-source circuit. R
MOSFET switching speed. Schottky diode D
power dissipation due to excessive ringing, by preventing the output pin
from being driven below ground.

will decrease the

g

can reduce the driver's

1

Figure 20. MOSFET Parasitic Oscillations

+

100k

3

Isolation

Boundary

1N

5819

Output Schottky diodes are recommended when driving inductive loads at
high frequencies. The diodes reduce the driver's power dissipation by
preventing the output pins from being driven above V

and below ground.

CC

Figure 21. Direct Transformer Drive Figure 22. Isolated MOSFET Drive

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8

MC34151, MC33151

V

in

I

B

+

+

R

g(on)

0

-

Base Charge

Removal

+

C

100k

R

g(off)

1

100k

In noise sensitive applications, both conducted and radiated EMI can
be reduced significantly by controlling the MOSFET's turn-on and
turn-off times.

The totem-pole outputs can furnish negative base current for enhanced
transistor turn-off, with the addition of capacitor C

1

Figure 23. Controlled MOSFET Drive Figure 24. Bipolar Transistor Drive

= 15 V

V

CC

4.7 0.1

+

6

V

in

.

+

+

-

+

5.7V

+

2

+

4

330pF

3

10k

The capacitor's equivalent series resistance limits the Drive Output Current
to 1.5 A. An additional series resistor may be required when using tantalum or
other low ESR capacitors.

Figure 25. Dual Charge Pump Converter

+

100k

6.8 10

7

1N5819

+

+

47

+ V

≈ 2.0 V

O

CC

+

100k

5

6.8 10
1N5819

+

47

+

- V

≈ - V

O

CC

Output Load Regulation

IO (mA) +VO (V) −VO (V)

0 27.7 −13.3

1.0 27.4 −12.9
10 26.4 −11.9
20 25.5 −11.2
30 24.6 −10.5
50 22.6 −9.4

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9

MC34151, MC33151

ORDERING INFORMATION

Device Package Shipping

MC34151DG SOIC−8

(Pb−Free)

MC34151DR2G SOIC−8

(Pb−Free)

MC34151PG PDIP−8

(Pb−Free)

MC33151DG SOIC−8

(Pb−Free)

MC33151DR2G SOIC−8

(Pb−Free)

MC33151PG PDIP−8

(Pb−Free)

MC33151VDR2G SOIC−8

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

98 Units / Rail

2500 Tape & Reel

50 Units / Rail

98 Units / Rail

2500 Tape & Reel

50 Units / Rail

2500 Tape & Reel

†

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10

MC34151, MC33151

PACKAGE DIMENSIONS

PDIP−8

P SUFFIX

CASE 626−05

ISSUE N

NOTE 8

A1

D1

D

A

58

E1

14

b2

B

TOP VIEW

e/2

A2

A

L

e

8X

b

SIDE VIEW

0.010 CA

NOTE 3

SEATING
PLANE

C

M

H

E

END VIEW

WITH LEADS CONSTRAINED

NOTE 5

M

eB

END VIEW

MBM

NOTE 6

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK­AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.

4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.

5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.

6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.

c

7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.

8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).

INCHES

DIM MIN MAX

A −−−− 0.210
A1 0.015 −−−−
A2 0.115 0.195 2.92 4.95

b 0.014 0.022
b2

0.060 TYP 1.52 TYP

C 0.008 0.014

D 0.355 0.400
D1 0.005 −−−−

E 0.300 0.325

E1 0.240 0.280 6.10 7.11

e 0.100 BSC
eB −−−− 0.430 −−− 10.92

L 0.115 0.150 2.92 3.81

M −−−− 10

MILLIMETERS

MIN MAX

−−− 5.33

0.38 −−−

0.35 0.56

0.20 0.36

9.02 10.16

0.13 −−−

7.62 8.26

2.54 BSC

−−− 10

°°

http://onsemi.com

11

−Y−

−Z−

MC34151, MC33151

PACKAGE DIMENSIONS

SOIC−8

D SUFFIX

CASE 751−07

ISSUE AK

NOTES:

−X−
A

58

B

1

S

0.25 (0.010)

4

M

M

Y

K

G

C

SEATING
PLANE

0.10 (0.004)

H

D

0.25 (0.010) Z

M

Y

SXS

N

X 45

_

M

J

SOLDERING FOOTPRINT*

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010

J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8

____

N 0.25 0.50 0.010 0.020

S 5.80 6.20 0.228 0.244

INCHES

1.52

0.060

7.0

0.275

0.6

0.024

4.0

0.155

1.270

0.050

SCALE 6:1

ǒ

inches

mm

Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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For additional information, please contact your local
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MC34151/D