ON MC100EL1648 Schematic

MC100EL1648

5 V ECL Voltage Controlled Oscillator Amplifier

Description

The MC100EL1648 is a voltage controlled oscillator amplifier that requires an external parallel tank circuit consisting of the inductor (L) and capacitor (C). A varactor diode may be incorporated into the tank circuit to provide a voltage variable input for the oscillator (VCO). This device may also be used in many other applications requiring a fixed frequency clock.

The MC100EL1648 is ideal in applications requiring a local oscillator, systems that include electronic test equipment, and digital high−speed telecommunications.

The MC100EL1648 is based on the VCO circuit topology of the MC1648. The MC100EL1648 uses advanced bipolar process technology which results in a design which can operate at an extended frequency range.

The ECL output circuitry of the MC100EL1648 is not a traditional open emitter output structure and instead has an on−chip termination emitter resistor, R direct ac−coupling of the output signal into a transmission line. Because of this output configuration, an external pull−down resistor is not required to provide the output with a dc current path. This output is intended to drive one ECL load (3.0 pF). If the user needs to fanout the signal, an ECL buffer such as the EL16 (EL11, EL14) type Line Receiver/Driver should be used.

Features

• Typical Operating Frequency Up to 1100 MHz

• Low−Power 19 mA at 5.0 Vdc Power Supply

• PECL Mode Operating Range: V

• NECL Mode Operating Range: V

to −5.5 V

• Input Capacitance = 6.0 pF (TYP)

• Pb−Free Packages are Available

NOTE: The MC100EL1648 is NOT useable as a crystal oscillator.

EXTERNAL

TANK

CIRCUIT

, with a nominal value of 510 W. This facilitates

E

= 4.2 V to 5.5 V with VEE = 0 V

CC

= 0 V with VEE = −4.2 V

CC

V

CC

V

BIAS POINT

TANK

OUTPUT

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MARKING

DIAGRAMS*

8

1

8

1

14

1

A = Assembly Location L = Wafer Lot Y = Year W = Work Week M G or G = Pb−Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

SOIC−8 D SUFFIX CASE 751

1

8

TSSOP−8

DT SUFFIX

CASE 948R

1

14

SOEIAJ−14

M SUFFIX CASE 965

1

DFN8

MN SUFFIX

CASE 506AA

= Date Code

K1648 ALYW

G

1648

ALYWG

G

KEL1648

ALYWG

G

6L M G

14

V

Figure 1. Logic Diagram

August, 2008 − Rev. 8

EE

V

EE

AGC

See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet.

1 Publication Order Number:

ORDERING INFORMATION

MC100EL1648/D

BIAS

MC100EL1648

V

EE

AGC

V

EE

568

NC TANK NC BIAS NC V

V

CC

1314 12 11 10 9 8

EE

12374

VCCV

TANK

CC

8 Lead

Table 1. PIN DESCRIPTION

Pin No.

8 Lead 14 Lead

1

2, 3

4

5

6, 7

8

Thermal

Exposed

Pad

12

1, 14

3

5

7, 8

10

2, 4, 7, 9, 11, 13

21 34567

OUT

VCCNC OUT NC AGC NC V

Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.

Figure 2. Pinout Assignments

Symbol Description

TANK

V

CC

OUT

AGC

V

EE

BIAS

NC

EP

OSC Input Voltage

Positive Supply

ECL Output

Automatic Gain Control Input

Negative Output

OSC Input Reference Voltage

No Connect

(DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open.

EE

14 Lead

Table 2. ATTRIBUTES

Characteristic Value

Internal Input Pulldown Resistor N/A

Internal Input Pullup Resistor N/A

ESD Protection Human Body Model

Machine Model

Charged Device Model

> 1 kV

> 100 V

> 1 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg

SOIC−8

TSSOP−8

SOEIAJ−14

DFN8

Level 1 Level 1 Level 3 Level 1

Level 1 Level 3 Level 3 Level 1

Flammability Rating Oxygen Index: 23 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 11

Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test

1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.

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2

MC100EL1648

Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

V

CC

V

EE

V

I

out

T

A

T

stg

q

JA

q

JC

q

JA

q

JC

q

JA

q

JC

q

JA

T

sol

q

JC

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

Power Supply PECL Mode VEE = 0 V 7 to 0 V

Power Supply NECL Mode VCC = 0 V −7 to 0 V

PECL Mode Input Voltage NECL Mode Input Voltage

Output Current Continuous

VEE = 0 V V

= 0 V

CC

Surge

VI  V VI  V

CC

EE

6 to 0

−6 to 0

50

100

V V

mA mA

Operating Temperature Range −40 to +85 °C

Storage Temperature Range −65 to +150 °C

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

SOIC−8 SOIC−8

190 130

°C/W °C/W

Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 °C/W

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

TSSOP−8 TSSOP−8

185 140

°C/W °C/W

Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 °C/W

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

SOIC−14 SOIC−14

150 110

°C/W °C/W

Thermal Resistance (Junction−to−Case) Standard Board SOIC−14 41 to 44 °C/W

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

Wave Solder Pb

Pb−Free

<2 to 3 sec @ 248°C <2 to 3 sec @ 260°C

DFN8 DFN8

129

84

265 265

°C/W °C/W

°C

Thermal Resistance (Junction−to−Case) (Note 1) DFN8 35 to 40 °C/W

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MC100EL1648

Table 4. PECL DC CHARACTERISTICS V

= 5.0 V; V

CC

= 0.0 V +0.8 / −0.5 V (Note 2)

EE

−40°C 25°C 85°C

Symbol

I

EE

V

OH

V

OL

Characteristic

Power Supply Current 13 19 25 13 19 25 13 19 25 mA

Output HIGH Voltage (Note 3) 3950 4170 4610 3950 4170 4610 3950 4170 4610 mV

Output LOW Voltage (Note 3) 3040 3410 3600 3040 3410 3600 3040 3410 3600 mV

Min Ty p Max Min Ty p Max Min Typ Max

Unit

AGC Automatic Gain Control Input 1690 1980 1690 1980 1690 1980 mV

V

I

BIAS

IL

IH

L

Bias Voltage (Note 4) 1650 1800 1650 1800 1650 1800 mV

1.5 1.35 1.2 V

2.0 1.85 1.7 V

Input Current −5.0 −5.0 −5.0 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

2. Output parameters vary 1:1 with V

3. 1.0 MW impedance.

CC

.

4. This measurement guarantees the dc potential at the bias point for purposes of incorporating a varactor tuning diode at this point.

Table 5. NECL DC CHARACTERISTICS V

= 0.0 V; V

CC

= −5.0 V +0.8 / −0.5 V (Note 5)

EE

−40°C 25°C 85°C

Symbol

I

EE

V

OH

V

OL

Characteristic

Power Supply Current 13 19 25 13 19 25 13 19 25 mA

Output HIGH Voltage (Note 6) −1050 −830 −399 −1050 −830 −399 −1050 −830 −399 mV

Output LOW Voltage (Note 6) −1960 −1590 −1400 −1960 −1590 −1400 −1960 −1590 −1400 mV

Min Ty p Max Min Typ Max Min Typ Max

Unit

AGC Automatic Gain Control Input −3310 −3020 −3310 −3020 −3310 −3020 mV

V

I

BIAS

IL

IH

L

Bias Voltage (Note 7) −3350 −3200 −3350 −3200 −3350 −3200 mV

−3.5 −3.65 −3.8 V

−3.0 −3.15 −3.3 V

Input Current −5.0 −5.0 −5.0 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

5. Output parameters vary 1:1 with V

6. 1.0 MW impedance.

CC

.

7. This measurement guarantees the dc potential at the bias point for purposes of incorporating a varactor tuning diode at this point.

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MC100EL1648

GENERIC TEST CIRCUITS: Bypass to Supply Opposite GND

V

CC

0.1 mF0.1 mF

V

IN

1 KW

0.1mF

Test Point

Tank #1

Tank #2

8 (10)

C

*

1 (12)

V

EE

3 (1) 2 (14)

L

F

4 (3)

OUT

**

L = Micro Metal torroid #T20−22, 8 turns #30

Enameled Copper wire (@ 40 nH)

5 (5)6 (7) 7 (8)

C = MMBV609

* Use high impedance probe (>1.0 MW must be used).

0.1 mF 0.1 mF0.01 mF100 mF

** The 1200 W resistor and the scope termination impedance constitute a 25:1 attenuator probe.

Coax shall be CT−070−50 or equivalent.

8 pin (14 pin) Lead Package

Tank Circuit Option #1, Varactor Diode

V

CC

0.1 mF0.1 mF

8 (10)

3 (1) 2 (14)

L = Micro Metal torroid #T20−22, 8 turns #30

Enameled Copper wire (@ 40 nH)

4 (3)

L

C

F

1 (12)

V

EE

5 (5)6 (7) 7 (8)

C = 3.0−35pF Variable Capacitance (@ 10 pF)

OUT

Note 1 Capacitor for tank may be variable type.

(See Tank Circuit #3.)

Note 2 Use high impedance probe (> 1 MW ).

8 pin (14 pin) Lead Package

0.1 mF 0.1 mF0.01 mF100 mF

Tank Circuit Option #2, Fixed LC

Figure 3. Typical Test Circuit with Alternate Tank Circuits

V

P-P

50%

t

a

t

b

PRF = 1.0MHz Duty Cycle (Vdc) -

t

a

t

b

Figure 4. Output Waveform

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MC100EL1648

OPERATION THEORY

Figure 5 illustrates the simplified circuit schematic for the MC100EL1648. The oscillator incorporates positive feedback by coupling the base of transistor Q6 to the collector of Q7. An automatic gain control (AGC) is incorporated to limit the current through the emitter−coupled pair of transistors (Q7 and Q6) and allow optimum frequency response of the oscillator. In order to maintain the high quality factor (Q) on the oscillator, and provide high spectral purity at the output, transistor Q4 is used to translate the oscillator signal to the output differential pair Q2 and Q3. Figure 16 indicates the high spectral purity of the oscillator output (pin 4 on 8−pin SOIC). Transistors

V

2 (14) 3 (1)

CC

800 W 1.36 KW

Q9

1.6 KW

Q2 and Q3, in conjunction with output transistor Q1, provide a highly buffered output that produces a square wave. The typical output waveform can be seen in Figure 4. The bias drive for the oscillator and output buffer is provided by Q9 and Q11 transistors. In order to minimize current, the output circuit is realized as an emitter−follower buffer with an on chip pull−down resistor R

3.1 KW

660 W 167 W

Q3 Q2

Q4

.

E

V

CC

Q1

OUTPUT

4 (3)

400 W

Q10Q11

D2

EE

TANKBIASV

Q7 Q6

330 W

Q8

EE

1 (12) 5 (5)8 (10)7 (8) 6 (7)

D1

16 KW

Q5

82 W 400 W 660 W 510 W

AGCV

8 pin (14 pin) Lead Package

Figure 5. Circuit Schematic

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ON MC100EL1648 Schematic [ru]