MC74VHC1GT66
SPST (NO) Normally Open
Analog Switch
The MC74VHC1GT66 is a Single Pole Single Throw (SPST)
analog switch. It achieves high speed propagation delays and low ON
resistances while maintaining low power dissipation. This bilateral
switch controls analog and digital voltages that may vary across the
full power−supply range (from V
The MC74VHC1GT66 is compatible in function to a single gate of
the High Speed CMOS MC74VHCT4066 and the metal−gate CMOS
MC14066. The device has been designed so that the ON resistances
(R
) are much lower and more linear over input voltage than RON of
ON
the metal−gate CMOS or High Speed CMOS analog switches.
The ON/OFF Control input is compatible with TTL−type input
thresholds allowing the device to be used as a logic−level translator
from 3 V CMOS logic to 5 V CMOS logic or from 1.8 V CMOS logic
to 3 V CMOS logic while operating at the high−voltage power supply.
The input protection circuitry on this device allows overvoltage
tolerance on the input, which provides protection when voltages of up
to 7 V are applied, regardless of the supply voltage. This allows the
MC74VHC1GT66 to be used to interface 5 V circuits to 3 V circuits.
Features
• High Speed: t
= 20 ns (Typ) at VCC = 5 V
PD
• Low Power Dissipation: I
• Diode Protection Provided on Inputs and Outputs
• Improved Linearity and Lower ON Resistance over Input Voltage
• On/Off Control Input Has OVT
• Chip Complexity: FETs = 11; Equivalent Gates = 3
• Pb−Free Packages are Available
to GND).
CC
= 1.0 mA (Max) at TA = 25°C
CC
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MARKING
DIAGRAMS
5
1
5
1
VE = Device Code
M = Date Code*
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
1
2
3 GND
4
5V
SC−88A
DF SUFFIX
CASE 419A
TSOP−5
DT SUFFIX
CASE 483
PIN ASSIGNMENT
ON/OFF CONTROL
5
1
5
1
IN/OUT X
OUT/IN Y
CC
M
VE MG
VE MG
G
A
A
G
© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. 15
FUNCTION TABLE
On/Off Control Input State of Analog Switch
L
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
1 Publication Order Number:
Off
On
MC74VHC1GT66/D
MC74VHC1GT66
IN/OUT X
OUT/IN Y
GND
1
A
2
A
3
5
4
V
CC
ON/OFF
CONTROL
(SC−88A, TSOP−5)
Figure 1. Pinout Diagram
ON/OFF CONTROL
IN/OUT X
A
X 1
1
U U
1
OUT/IN Y
A
Figure 2. Logic Symbol
MAXIMUM RATINGS
Symbol Characteristics Value Unit
V
V
V
I
T
q
MSL Moisture Sensitivity Level 1
V
I
Latchup
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
DC Supply Voltage −0.5 to +7.0 V
CC
DC Input Voltage −0.5 to +7.0 V
IN
Analog Output Voltage −0.5 to 7.0 V
IS
I
Input Diode Current −20 mA
IK
DC Supply Current, VCC and GND +25 mA
CC
Storage Temperature Range *65 to )150 °C
STG
T
Lead Temperature, 1 mm from Case for 10 Seconds 260 °C
L
T
Junction Temperature Under Bias )150 °C
J
Thermal Resistance SC70−5 (Note 1)
JA
P
Power Dissipation in Still Air at 85°CSC70−5
D
F
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
R
ESD Withstand Voltage Human Body Model (Note 2)
ESD
Machine Model (Note 3)
SOT23−5
SOT23−5
Charged Device Model (Note 4)
350
230
150
200
u2000
u200
N/A
Latchup Performance Above VCC and Below GND at 125°C (Note 5) $500 mA
°C/W
mW
V
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2
MC74VHC1GT66
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
V
V
V
t
Device Junction Temperature versus
Time to 0.1% Bond Failures
Temperature °C
DC Supply Voltage 2.0 5.5 V
CC
Digital Input Voltage GND 5.5 V
IN
Analog Input Voltage GND V
IS
T
Operating Temperature Range −55 +125 °C
A
, tfInput Rise and Fall Time VCC = 3.3 V ± 0.3 V
r
Junction
Time, Hours Time, Years
V
= 5.0 V ± 0.5 V
CC
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
0
0
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
=120 C°
= 130 C°
J
T
=110 C°
J
J
T
T
1
1 10 100
NORMALIZED FAILURE RATE
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
= 90 C°
=100 C°
J
J
T
T
CC
100
20
ns/V
= 80 C°
J
T
1000
V
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MC74VHC1GT66
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
V
V
I
I
CCT
R
I
OFF
Minimum High−Level
IH
Input Voltage
ON/OFF Control Input
Maximum Low−Level
IL
Input Voltage
ON/OFF Control Input
I
Maximum Input
IN
Leakage Current
ON/OFF Control Input
Maximum Quiescent
CC
Supply Current
Quiescent
Supply Current
Maximum ”ON”
ON
Resistance
Maximum Off−Channel
Leakage Current
RON = Per Spec
RON = Per Spec
VIN = VCC or GND 0 to
VIN = VCC or GND
VIO = 0 V
ON/OFF Control at
3.4 V
VIN = V
IH
VIS = VCC or GND
|IIS| ≤ 10 mA (Figure 4)
VIN = V
IL
VIS = VCC or GND
Switch Off (Figure 5)
V
(V)
3.0
4.5
5.5
3.0
4.5
5.5
TA = 25°C TA ≤ 85°C −55°C ≤ TA ≤ 125°C
CC
Min Max Min Max Min Max
1.2
2.0
2.0
0.53
0.8
0.8
1.2
2.0
2.0
0.53
0.8
0.8
Unit
1.2
2.0
2.0
0.53
0.8
0.8
±0.1 ±1.0 ±1.0
5.5
5.5 1.0 20 40
5.5 1.35 1.5 1.65 mA
3.0
4.5
5.5
60
45
40
70
50
45
100
60
55
5.5 0.1 0.5 1.0
V
V
mA
mA
W
mA
AC ELECTRICAL CHARACTERISTICS C
Symbol
t
PLH
t
PHL
t
,
PLZ
t
PHZ
t
,
PZL
t
PZH
C
IN
,
Parameter Test Conditions
Maximum Propagation
YA = Open
Delay, Input X to Y
(Figures 7, 14)
Maximum Propagation
RL = 1000 W
Delay, ON/OFF Control
to Analog Output
Maximum Propagation
(Figures 8, 15)
RL = 1000 W
Delay, ON/OFF Control
to Analog Output
Maximum Input
Capacitance
(Figures 8, 15)
ON/OFF Control Input 0.0 3 10 10 10
Control Input = GND
Analog I/O
Feedthrough
= 50 pF, Input tr/t
load
= 3.0 ns
f
V
CC
(V)
2.0
3.0
4.5
5.5
2.0
3.0
4.5
5.5
2.0
3.0
4.5
5.5
TA = 25°C TA ≤ 85°C −55°C ≤ TA ≤ 125°C
Min Typ Max Min Max Min Max
1
0.6
0.6
0.6
32
28
24
20
32
28
24
20
5
2
1
1
40
35
30
25
40
35
30
25
6
3
1
1
45
40
35
30
45
40
35
30
5.0
4410
10
10
10
50
45
40
35
50
45
40
35
10
10
Unit
7
ns
4
2
1
ns
ns
pF
Typical @ 25°C, VCC = 5.0 V
C
Power Dissipation Capacitance (Note 6)
PD
18
pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
power consumption; P
= CPD V
D
2
fin + ICC VCC.
CC
= CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
)
CC(OPR
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4
MC74VHC1GT66
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol Parameter Test Conditions V
BW Maximum On−Channel Bandwidth
or Minimum Frequency Response
(Figure 10)
ISO
NOISE
Off−Channel Feedthrough Isolation
off
(Figure 11)
Feedthrough Noise Control to
feed
Switch
(Figure 12)
THD Total Harmonic Distortion
(Figure 13)
PLOTTER
fin = 1 MHz Sine Wave
Adjust f
Increase fin = frequency until dB meter reads −3 dB
R
voltage to obtain 0 dBm at V
in
= 50 W
L
OS
fin = Sine Wave
Adjust f
fin = 10 kHz, RL = 600 W
voltage to obtain 0 dBm at V
in
IS
Vin ≤ 1 MHz Square Wave (tr = tf = 2ns)
= 600 W
R
L
fin = 1 kHz, RL = 10 kW
THD = THD
VIS = 3.0 VPP sine wave
Measured
− THD
Source
VIS = 5.0 VPP sine wave
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.3
5.5
Limit 25°C Unit
CC
150
175
180
−80
−80
−80
45
60
130
0.30
0.15
MHz
dB
mV
PP
%
POWER
SUPPLY
COMPUTER
DC PARAMETER
ANALYZER
+−
V
CC
V
CC
51
2
43
V
IH
V
CC
A
2
Figure 4. On Resistance Test Set−Up Figure 5. Maximum Off−Channel Leakage Current
Test Set−Up
V
CC
A
51
V
CC
51
V
CC
51
V
IL
43
V
CC
N/C
2
V
IH
43
Figure 6. Maximum On−Channel Leakage Current
Test Set−Up
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TEST
POINT
2
V
IH
43
Figure 7. Propagation Delay Test Set−Up
5
MC74VHC1GT66
Switch to Position 2 when testing t
Switch to Position 1 when testing t
PLZ
PHZ
and t
and t
TEST POINT
V
CC
1
51
2
R
L
2
V
CC
1
CL*
43
2
*Includes all probe and jig capacitance.
Figure 8. Propagation Delay Output Enable/Disable
Test Set−Up
V
OS
0.1 mF
f
in
2
51
PZL
PZH
V
CC
V
CC
A
N/C
N/C
2
51
43
Figure 9. Power Dissipation Capacitance
Test Set−Up
V
IS
V
CC
f
in
0.1 mF
V
OS
V
CC
51
2
dB
Meter
*Includes all probe and jig capacitance.
Figure 10. Maximum On−Channel Bandwidth
Test Set−Up
(VCC)/2
R
R
L
V
OS
L
51
I
2
S
43
43
V
CC
VINv 1MHz
t
r
+ tf+ 2ns
V
dB
Meter
R
L
*Includes all probe and jig capacitance.
Figure 11. Off−Channel Feedthrough Isolation
Test Set−Up
To Distortion
Meter
)/2
IH
GND
(V
CC
R
f
L
in
V
OS
0.1 mF
V
IS
2
43
V
CC
51
V
IH
43
*Includes all probe and jig capacitance.
Figure 12. Feedthrough Noise, ON/OFF Control to
Analog Out, Test Set−Up
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*Includes all probe and jig capacitance.
Figure 13. Total Harmonic Distortion Test Set−Up
6
MC74VHC1GT66
V
X
A
1.5 V
1.5 V
CC
t
PLH
Y
A
50% V
CC
t
PHL
V
OH
V
OL
Figure 14. Propagation Delay, Analog In to Analog Out Waveforms
Control
10%
50% V
Analog Out
50% V
t
r
90%
t
PZL
CC
CC
t
PZH
t
f
V
IH
1.5 V
t
PLZ
High
Impedance
10%
90%
V
OL
V
OH
High
t
Impedance
PHZ
Figure 15. Propagation Delay, ON/OFF Control
ORDERING INFORMATION
Device Package Shipping
M74VHC1GT66DFT1G SC−88A
(Pb−Free)
MC74VHC1GT66DFT2 SC−88A
M74VHC1GT66DFT2G SC−88A
(Pb−Free)
3000 / Tape & Reel
MC74VHC1GT66DTT1 TSOP−5
M74VHC1GT66DTT1G TSOP−5
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
†
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7
MC74VHC1GT66
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE K
A
G
45
D
5 PL
−B−
MM
B0.2 (0.008)
S
12 3
N
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
INCHES
DIMAMIN MAX MIN MAX
B 1.15 1.350.045 0.053
C 0.80 1.100.031 0.043
D 0.10 0.300.004 0.012
G 0.65 BSC0.026 BSC
H --- 0.10---0.004
J 0.10 0.250.004 0.010
K 0.10 0.300.004 0.012
N 0.20 REF0.008 REF
S 2.00 2.200.079 0.087
MILLIMETERS
1.80 2.200.071 0.087
J
C
H
K
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
SCALE 20:1
0.0748
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ǒ
inches
mm
Ǔ
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8
MC74VHC1GT66
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
NOTE 5
2X
2X
T0.10
T0.20
54
123
L
G
D
0.205XC AB
M
S
B
K
DETAIL Z
A
J
DETAIL Z
C
0.05
H
SEATING
PLANE
T
SOLDERING FOOTPRINT*
1.9
0.95
0.037
0.074
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
MILLIMETERS
DIM MIN MAX
A 3.00 BSC
B 1.50 BSC
C 0.90 1.10
D 0.25 0.50
G 0.95 BSC
H 0.01 0.10
J 0.10 0.26
K 0.20 0.60
L 1.25 1.55
M 0 10
__
S 2.50 3.00
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm
ǒ
inches
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74VHC1GT66/D
9
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