ESDR0502B
Transient Voltage Suppressor
ESD Protection Diodes with Ultra−Low
Capacitance
The ESDR0502B is designed to protect voltage sensitive
components from damage due to ESD in applications that require ultra
low capacitance to preserve signal integrity. Excellent clamping
capability, low leakage and fast response time are combined with an
ultra low diode capacitance of 0.5 pF to provide best in class
protection from IC damage due to ESD. The small SC−75 package is
ideal for designs where board space is at a premium. The ESDR0502B
can be used to protect two uni−directional lines or one bi−directional
line. When used to protect one bi−directional line, the effective
capacitance is 0.25 pF. Because of its low capacitance, it is well suited
for protecting high frequency signal lines such as USB2.0 high speed
and antenna line applications.
Specification Features:
• Low Capacitance 0.5 pF Typical
• Low Clamping Voltage
• Small Body Outline Dimensions:
0.063” x 0.063” (1.60 mm x 1.60 mm)
• Low Body Height: 0.031″ (0.8 mm)
• Stand−off Voltage: 5 V
• Low Leakage
• Response Time is Typically < 1.0 ns
• IEC61000−4−2 Level 4 ESD Protection
• This is a Pb−Free Device
Mechanical Characteristics:
CASE:
Void-free, transfer-molded, thermosetting plastic
Epoxy Meets UL 94 V−0
LEAD FINISH: 100% Matte Sn (Tin)
MOUNTING POSITION: Any
QUALIFIED MAX REFLOW TEMPERATURE: 260°C
Device Meets MSL 1 Requirements
MAXIMUM RATINGS
Rating Symbol Value Unit
IEC 61000−4−2 (ESD) Contact ±8.0 kV
Peak Surge Power (8 x 20 ms)
Peak Surge Current (8 x 20 ms)
Total Power Dissipation on FR−5 Board
(Note 1) @ T
Storage Temperature Range T
Junction Temperature Range T
Lead Solder Temperature − Maximum
(10 Second Duration)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
= 25°C
A
P
pk
I
pp
P
D
stg
J
T
L
See Application Note AND8308/D for further description of survivability specs.
20 W
2.0 A
150 mW
−55 to +150 °C
−55 to +150 °C
260 °C
PIN 1. CATHODE
3
ESDR0502BT1G SC−75
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
See specific marking information in the device marking
column of the Electrical Characteristics tables starting on
page 2 of this data sheet.
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1
2. CATHODE
3. ANODE
2
MARKING
DIAGRAM
SC−75
CASE 463
2
1
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
STYLE 4
AD = Device Code
M = Date Code*
G = Pb−Free Package
AD M G
G
1
ORDERING INFORMATION
Device Package Shipping
(Pb−Free)
3000/Tape & Reel
DEVICE MARKING INFORMATION
3
†
© Semiconductor Components Industries, LLC, 2010
June, 2010 − Rev. 0
1 Publication Order Number:
ESDR0502B/D
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol
V
I
V
RWM
V
V
P
Maximum Reverse Peak Pulse Current
PP
Clamping Voltage @ I
C
Working Peak Reverse Voltage
I
Maximum Reverse Leakage Current @ V
R
Breakdown Voltage @ I
BR
I
Test Current
T
I
Forward Current
F
Forward Voltage @ I
F
Peak Power Dissipation
pk
C Capacitance @ VR = 0 and f = 1.0 MHz
Parameter
PP
T
F
ESDR0502B
RWM
VCV
V
RWM
BR
Uni−Directional TVS
I
I
F
I
V
R
F
I
T
I
PP
V
ELECTRICAL CHARACTERISTICS (T
V
RWM
(V)
= 25°C unless otherwise noted, VF = 1.1 V Max. @ IF = 10 mA for all types)
A
I
R
@ V
(mA)
RWM
VBR (V)
@ I
T
(Note 2)
I
T
C (pF),
uni−directional
(Note 3)
C (pF),
bi−directional
(Note 4)
VC (V)
@ I
PP
(Note 5)
= 1 A
V
Per
IEC61000−
4−2
(Note 6)
Device
Device
Marking
Max Max Min mA Typ Max Ty p Max Max
ESDR0502B AD 5.0 1.0 5.8 1.0 0.5 0.9 0.25 0.45 15 Figures 1
and 2
2. VBR is measured with a pulse test current IT at an ambient temperature of 25°C.
3. Uni−directional capacitance at f = 1 MHz, V
4. Bi−directional capacitance at f = 1 MHz, V
5. Surge current waveform per Figure 5.
= 0 V, TA = 25°C (pin1 to pin 3; pin 2 to pin 3).
R
= 0 V, TA = 25°C (pin1 to pin 2).
R
6. Typical waveform. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
C
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV contact per IEC 61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV contact per IEC 61000−4−2
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2
ESDR0502B
IEC 61000−4−2 Spec.
Test
Voltage
Level
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
(kV)
ESD Gun
First Peak
Current
(A)
Current at
30 ns (A)
TVS
50 W
Cable
IEC61000−4−2 Waveform
I
peak
Current at
60 ns (A)
100%
90%
I @ 30 ns
I @ 60 ns
10%
Figure 3. IEC61000−4−2 Spec
Oscilloscope
50 W
tP = 0.7 ns to 1 ns
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
100
t
r
90
80
70
60
50
40
30
20
% OF PEAK PULSE CURRENT
10
0
020406080
PEAK VALUE I
t
P
Figure 5. 8 X 20 ms Pulse Waveform
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
@ 8 ms
RSM
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I
t, TIME (ms)
/2 @ 20 ms
RSM
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3
ESDR0502B
PACKAGE DIMENSIONS
SC−75/SOT−416
CASE 463−01
ISSUE F
3 PL
b
0.20 (0.008) D
M
C
−E−
3
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2
e
−D−
1
0.20 (0.008) E
H
E
A
2. CONTROLLING DIMENSION: MILLIMETER.
MILLIMETERS
DIM MIN NOM MAX
A 0.70 0.80 0.90
A1 0.00 0.05 0.10
b
0.15 0.20 0.30 0.006 0.008 0.012
C 0.10 0.15 0.25
D 1.55 1.60 1.65
E
0.70 0.80 0.90 0.027 0.031 0.035
e 1.00 BSC
L 0.10 0.15 0.20
H
1.50 1.60 1.70
E
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. ANODE
INCHES
MIN NOM MAX
0.027 0.031 0.035
0.000 0.002 0.004
0.004 0.006 0.010
0.059 0.063 0.067
0.04 BSC
0.004 0.006 0.008
0.061 0.063 0.065
A1
SOLDERING FOOTPRINT*
0.356
0.014
1.803
0.071
0.508
0.020
0.787
0.031
1.000
0.039
SCALE 10:1
ǒ
inches
mm
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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ESDR0502B/D
4
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