ON ESD11N5.0ST5G Schematic [ru]

ESD11N5.0ST5G

Transient Voltage
Suppressors

Micro−Packaged Diodes for ESD Protection

The ESD11N is designed to protect voltage sensitive components
that require ultra−low capacitance from ESD and transient voltage
events. Excellent clamping capability, low capacitance, low leakage,
and fast response time, make these parts ideal for ESD protection on
designs where board space is at a premium. Because of its low
capacitance, it is suited for use in high frequency designs such as USB

2.0 high speed and antenna line applications.

http://onsemi.com

Specification Features

• Low Capacitance 0.6 pF

• Low Clamping Voltage

• Small Body Outline Dimensions: 0.60 mm x 0.30 mm

• Low Body Height: 0.3 mm

• Stand−off Voltage: 5.0 V

• Low Leakage

• Response Time is < 1 ns

• IEC61000−4−2 Level 4 ESD Protection

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Mechanical Characteristics
MOUNTING POSITION:
QUALIFIED MAX REFLOW TEMPERATURE: 260°C

Device Meets MSL 1 Requirements

MAXIMUM RATINGS

Rating Symbol Value Unit

IEC 61000−4−2 (ESD) Contact

Total Power Dissipation on FR−5 Board
(Note 1) @ T
Thermal Resistance, Junction−to−Ambient

Junction and Storage Temperature Range TJ, T

Lead Solder Temperature − Maximum
(10 Second Duration)

Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.

1. FR−5 = 1.0 x 0.75 x 0.62 in.

= 25°C

A

Any

Air

°PD°

R

q

T

JA

−40 to +125 °C

stg

L

±8.0

±15

250

400

260 °C

mW

°C/W

kV

MARKING
DIAGRAM

PIN 1

DSN2

CASE 152AA

XXXX = Specific Device Code
YYY = Year Code

ORDERING INFORMATION

Device Package Shipping

ESD11N5.0ST5G DSN2

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

XXXX

YYY

†

5000/Tape & Reel

See Application Note AND8308/D for further description of survivability specs.

© Semiconductor Components Industries, LLC, 2010

October, 2010 − Rev. 4

1 Publication Order Number:

ESD11N5.0S/D

ESD11N5.0ST5G

ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol

V

I

PP

V

RWM

I

V

I

Maximum Reverse Peak Pulse Current

Clamping Voltage @ I

C

Working Peak Reverse Voltage

Maximum Reverse Leakage Current @ V

R

Breakdown Voltage @ I

BR

Test Current

T

*See Application Note AND8308/D for detailed explanations of

Parameter

PP

RWM

T

BR

V

RWM

VCV

Bi−Directional TVS

I

I

PP

I

T

I

R

I

V

RWM

V

R

I

T

I

PP

BR

V

V

C

datasheet parameters.

ELECTRICAL CHARACTERISTICS (T

Device

Device

Marking

= 25°C unless otherwise noted)

A

V

RWM

(V)

I

R

@ V

(mA)

RWM

VBR (V) @ I

(Note 2)

T

I

T

C (pF)

Max Max Min mA Typ Max

VC (V) @

= 1 A

I

PP

Max

(Note 3)

V

C

Per IEC61000−4−2

(Note 4)

ESD11N5.0ST5G N5S0 5.0 1.0 5.8 1.0 0.6 0.9 12 Figures 1 and 2

See Below

2. VBR is measured with a pulse test current IT at an ambient temperature of 25°C.

3. Surge current waveforms per Figure 5.

4. For test procedure see Figures 3 and 4 and Application Note AND8307/D.

Figure 1. ESD Clamping Voltage Screenshot

Positive 8 kV Contact per IEC61000−4−2

http://onsemi.com

Figure 2. ESD Clamping Voltage Screenshot

Negative 8 kV Contact per IEC61000−4−2

2

ESD11N5.0ST5G

IEC 61000−4−2 Spec.

Test

Voltage

Level

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

(kV)

ESD Gun

First Peak

Current

(A)

Current at

30 ns (A)

TVS

50 W

Cable

IEC61000−4−2 Waveform

I

peak

Current at

60 ns (A)

100%

90%

I @ 30 ns

I @ 60 ns

10%

Figure 3. IEC61000−4−2 Spec

Oscilloscope

50 W

tP = 0.7 ns to 1 ns

Figure 4. Diagram of ESD Test Setup

The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger

100

t

r

90

80

70

60

50

40

30

20

% OF PEAK PULSE CURRENT

10

0

020406080

PEAK VALUE I

t

P

Figure 5. 8 X 20 ms Pulse Waveform

systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.

@ 8 ms

RSM

PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms

HALF VALUE I

t, TIME (ms)

/2 @ 20 ms

RSM

http://onsemi.com

3