ON DAP006 Schematic [ru]

Customer Specific Device from ON Semiconductor
PWM Current−Mode
DAP006
Controller for Free Running Quasi−Resonant Operation
5.0 s timer prevents the free−run frequency to exceed the 150 kHz CISPR−22 EMI starting limit while the skip adjustment capability lets the user select the frequency at which the burst foldback takes place.
The Dynamic Self−Supply (DSS) drastically simplifies the transformer design in avoiding the use of an auxiliary winding. This feature is particularly useful in applications where the output voltage varies during operation (e.g. battery chargers). Due to its high−voltage technology, the IC is directly connected to the high−voltage DC rail. The DSS also offers a better overload trip point.
The transformer core reset detection is done through an auxiliary winding which, brought via a dedicated pin, also enables fast O v e r− Voltage Protection (OVP). Once an OVP has been detected, the IC permanently latches−off.
Finally, the continuous feedback signal monitoring implemented with an over−current fault protection circuitry (OCP) makes the final design rugged and reliable.
Features
Free−Running Borderline/Critical Mode
Quasi−Resonant Operation
Current−Mode with Adjustable Skip−Cycle Capability
No Auxiliary Winding V
Operation
CC
Auto−Recovery Over Current Protection
Latching Over Voltage Protection
External Latch Triggering, e.g. Via Over−Temperature
Signal
500 mA Peak Current Source/Sink Capability
Internal 4.0 ms Soft−Start
Internal 5.0 s Minimum T
OFF
Adjustable Skip Level
Internal Temperature Shutdown
Direct Optocoupler Connection
SPICE Models Available for TRANsient Analysis
Typical Applications
AC/DC Adapters for Notebooks, etc.
Offline Battery Chargers
Consumer Electronics (DVD Players, Set−Top Boxes,
TVs, etc.)
Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
8
1
SO−8
D1, D2 SUFFIX
CASE 751
© Semiconductor Components Industries, LLC, 2005
October, 2005 − Rev. 2
MARKING DIAGRAM
8
DAP6 ALYW
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet.
PIN CONNECTIONS
Dmg
18
FB
2
3
CS
Gnd
4
(Top View)
1 Publication Order Number:
HV NC
7
V
6
CC
5
Drv
DAP006/D
DAP006
OVP &
+
Demag
Universal Network
*Please refer to the application information section
*
Dmg FB
CS Gnd
V
HV
NC
CC
Drv
8 7 6 5
+
Y1 Type
1 2 3 4
12 V @ 1.0 A
+
Ground
Figure 1. Typical Application
PIN FUNCTION DESCRIPTION
Pin No.
1 Demag Core reset detection and OVP The auxiliary FLYBACK signal ensures discontinuous operation and
2 FB Sets the peak current setpoint By connecting an optocoupler to this pin, the peak current setpoint is
3 CS Current sense input and skip
4 Gnd The IC ground − 5 Drv Driving pulses The driver’s output to an external MOSFET. 6 V 7 NC This unconnected pin ensures adequate creepage distance. 8 HV High−voltage pin Connected to the high−voltage rail, this pin injects a constant current into
Pin Name
CC
Function
cycle level selection
Supplies the IC
Description
offers a fixed overvoltage detection level of 7.2 V.
adjusted accordingly to the output power demand. By bringing this pin below the internal skip level, device shuts off.
This pin senses the primary current and routes it to the internal comparator via an L.E.B. By inserting a resistor in series with the pin, you control the level at which the skip operation takes place.
This pin is connected to an external bulk capacitor of typically 10 F.
the VCC bulk capacitor.
http://onsemi.com
2
DAP006
4.5 s Delay
HV
V
CC
Ground
OVP
7.0
mA
PON
+
2.6 V
+
− +
12 V, 10 V,
5.3 V (fault)
To Internal
Supply
Fault
Mngt.
*S and R are level triggered whereas S is edge
triggered. R has priority over the other inputs.
/2.77
+
Demag
5.0 s
Blanking
S
S* R*
Overload?
5.0 s
Timeout
Q
Q
R
+
Timeout Reset
− +
+ 50 mV
V
CC
Soft−start = 5.0 ms
1.0 V
Demag
10 V
Driver: src = 20
sink = 10
/3
200 a
when Drv
is OFF
380 ns
L.E.B.
Demag
Drv
FB
CS
Figure 2. Internal Circuit Architecture
MAXIMUM RATINGS
Rating
Continuous Power Supply or Drive Voltage Transient Power Supply Voltage
Duration < 10 ms, I
VCC
< 10 mA
Maximum Voltage on all other pins except Pin 8 (HV), Pin 6 (VCC) and
Pin 5 (Drv)
Maximum Current into all pins except VCC (6), HV (8) and Demag (1) when 10 V
ESD diodes are activated Maximum Current in Pin 1 Idem +3.0/−2.0 mA Thermal Resistance, Junction−to−Case R Thermal Resistance, Junction−to−Air, SOIC version R Maximum Junction Temperature TJ Temperature Shutdown 155 °C Hysteresis in Shutdown 30 °C Storage Temperature Range −60 to +150 °C ESD Capability, HBM Model (All pins except VCC and HV) 2.0 kV ESD Capability, Machine Model 200 V Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) decoupled to ground with 10 F Minimum Voltage on Pin 8 (HV), Pin 6 (VCC) decoupled to ground with 10 F
Symbol
VCC, Drv
V
CC
Value
18 20
−0.3 to 10 V
5.0 mA
57 °C/W 178 °C/W 150 °C
450 V
40 V
V
HVMAX
V
HVMIN
θ
θ
MAX
J−C J−A
Units
V V
http://onsemi.com
3
DAP006
ELECTRICAL CHARACTERISTICS (For typical values T
V
= 11 V unless otherwise noted)
CC
= 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,
J
Rating Pin Symbol Min Typ Max Unit
DYNAMIC SELF−SUPPLY
Vcc Increasing Level at which the Current Source Turns−off 6 VCC Vcc Decreasing Level at which the Current Source Turns−on 6 VCC Vcc Decreasing Level at which the Latch−off Phase Ends 6 VCC Internal IC Consumption, No Output Load on Pin 5,
F
= 60 kHz, Duty Cycle = TBD
SW
Internal IC Consumption, 1.0 nF Output Load on Pin 5,
F
= 60 kHz, Duty Cycle = TBD
SW
6 ICC1 1.0 1.3
6 ICC2 1.6 2.0
OFF
ON
latch
10.8 12 12.9 V
9.1 10 10.6 V
5.3 V
(Note 1)
(Note 1
Internal IC Consumption in Latch−off Phase 6 ICC3 330
INTERNAL START−UP CURRENT SOURCE (TJ u 0°C)
High−voltage Current Source, VCC = 10 V 8 IC1 4.3 7.0 9.6 mA High−voltage Current Source, VCC = 0 8 IC2 8.0 mA
DRIVE OUTPUT
Output Voltage Rise−time @ CL = 1.0 nF, 10−90% of Output
5 T
r
40 ns
Signal
Output Voltage Fall−time @ CL = 1.0 nF, 10−90% of Output
5 T
f
20 ns
Signal Source Resistance 5 R Sink Resistance 5 R
OH OL
12 20 36 Ω
5.0 10 19 Ω
CURRENT COMPARATOR (Pin 5 Unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 3 3 I Maximum Internal Current Setpoint 3 I Propagation Delay from Current Detection to Gate OFF State 3 T Leading Edge Blanking Duration 3 T
IB
Limit
DEL LEB
0.02
0.92 1.0 1.12 V
100 160 ns
380 ns
Internal Current Offset Injected on the CS Pin during OFF Time 3 Iskip 200
OVERVOLTAGE SECTION (VCC = 11 V)
Sampling Delay after ON Time 1 T OVP Internal Reference Level 1 V
sample
ref
4.5
6.4 7.2 8.0 V
FEEDBACK SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 k)
Internal Pull−up Resistor 2 Rup 20 kΩ Pin 3 to Current Setpoint Division Ratio Iratio 3.3 − Internal Soft−start Tss 5.0 ms
DEMAGNETIZATION DETECTION BLOCK
Input Threshold Voltage (Vpin 1 Decreasing) 1 V Hysteresis (Vpin 1 Decreasing) 1 V
th H
35 50 90 mV
20 mV
Input Clamp Voltage High State (Ipin 1 = 3.0 mA) Low State (Ipin 1 = −2.0 mA)
Demag Propagation Delay 1 T Internal Input Capacitance at Vpin 1 = 1.0 V 1 C Minimum T
(Internal Blanking Delay after TON) 1 T
OFF
Pin 1 Internal Resistance 1 R
1 1
VC
VC
dem
blank
par
H L
8.0
−0.9
10
−0.7
12
−0.5
210 ns
10 pF
5.0
int
28 kΩ
1. Max value at TJ = 0°C.
mA
mA
A
A
A
s
V V
s
http://onsemi.com
4
DAP006
13.2
12.8
12.4
12.0
(V)
11.6
CC(off)
V
11.2
10.8
10.4
1.6
1.4
1.2
(mA)
1.0
CC1
I
0.8
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 1. V
Threshold versus
CC(off)
Temperature
11.2
10.8
10.4
(V)
10
CC(on)
V
9.6
9.2
1251007550250−25
8.8
Figure 2. V
Threshold versus
CC(on)
1251007550250−25
Temperature
2.3
2.1
1.9
1.7
(mA)
CC2
I
1.5
0.6
0.4
12
10
8.0
(mA)
C1
I
6.0
4.0
2.0
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 3. Current Consumption (No Load)
versus Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 5. HV Current Source at VCC = 10 V
versus Temperature
1.3
1251007550250−25
1.1 1251007550250−25
Figure 4. Current Consumption (Loaded by
1 nF) versus Temperature
1.20
1.15
1.10
(V)
1.05
limit
I
1.00
0.95
1251007550250−25
0.90 12550 10075250−25
Figure 6. Maximum Current Setpoint versus
Temperature
http://onsemi.com
5
Loading...
+ 11 hidden pages