ON DAP006 Schematic [ru]

Customer Specific Device from ON Semiconductor

PWM Current−Mode

DAP006

Controller for Free Running
Quasi−Resonant Operation

The DAP006 combines a true current mode modulator
and a demagnetization detector to ensure full borderline/
critical Conduction Mode in any load/line conditions and
minimum drain voltage switching (Quasi−Resonant
operation). Due to its inherent skip cycle capability, the
controller enters burst mode as soon as the power demand
falls below a predetermined level. As this happens at low
peak current, no audible noise can be heard. An internal

5.0 s timer prevents the free−run frequency to exceed the
150 kHz CISPR−22 EMI starting limit while the skip
adjustment capability lets the user select the frequency at
which the burst foldback takes place.

The Dynamic Self−Supply (DSS) drastically simplifies
the transformer design in avoiding the use of an auxiliary
winding. This feature is particularly useful in applications
where the output voltage varies during operation (e.g.
battery chargers). Due to its high−voltage technology, the IC
is directly connected to the high−voltage DC rail. The DSS
also offers a better overload trip point.

The transformer core reset detection is done through an
auxiliary winding which, brought via a dedicated pin, also
enables fast O v e r− Voltage Protection (OVP). Once an OVP
has been detected, the IC permanently latches−off.

Finally, the continuous feedback signal monitoring
implemented with an over−current fault protection circuitry
(OCP) makes the final design rugged and reliable.

Features

• Free−Running Borderline/Critical Mode

Quasi−Resonant Operation

• Current−Mode with Adjustable Skip−Cycle Capability

• No Auxiliary Winding V

Operation

CC

• Auto−Recovery Over Current Protection

• Latching Over Voltage Protection

• External Latch Triggering, e.g. Via Over−Temperature

Signal

• 500 mA Peak Current Source/Sink Capability

• Internal 4.0 ms Soft−Start

• Internal 5.0 s Minimum T

OFF

• Adjustable Skip Level

• Internal Temperature Shutdown

• Direct Optocoupler Connection

• SPICE Models Available for TRANsient Analysis

Typical Applications

• AC/DC Adapters for Notebooks, etc.

• Offline Battery Chargers

• Consumer Electronics (DVD Players, Set−Top Boxes,

TVs, etc.)

• Auxiliary Power Supplies (USB, Appliances, TVs, etc.)

8

1

SO−8

D1, D2 SUFFIX

CASE 751

© Semiconductor Components Industries, LLC, 2005

October, 2005 − Rev. 2

MARKING
DIAGRAM

8

DAP6
ALYW

1

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions
section on page 14 of this data sheet.

PIN CONNECTIONS

Dmg

18

FB

2

3

CS

Gnd

4

(Top View)

1 Publication Order Number:

HV
NC

7

V

6

CC

5

Drv

DAP006/D

DAP006

OVP &

+

Demag

Universal Network

*Please refer to the application information section

*

Dmg
FB

CS
Gnd

V

HV

NC

CC

Drv

8
7
6
5

+

Y1 Type

1
2
3
4

12 V @ 1.0 A

+

Ground

Figure 1. Typical Application

PIN FUNCTION DESCRIPTION

Pin No.

1 Demag Core reset detection and OVP The auxiliary FLYBACK signal ensures discontinuous operation and

2 FB Sets the peak current setpoint By connecting an optocoupler to this pin, the peak current setpoint is

3 CS Current sense input and skip

4 Gnd The IC ground −
5 Drv Driving pulses The driver’s output to an external MOSFET.
6 V
7 NC − This unconnected pin ensures adequate creepage distance.
8 HV High−voltage pin Connected to the high−voltage rail, this pin injects a constant current into

Pin Name

CC

Function

cycle level selection

Supplies the IC

Description

offers a fixed overvoltage detection level of 7.2 V.

adjusted accordingly to the output power demand. By bringing this pin
below the internal skip level, device shuts off.

This pin senses the primary current and routes it to the internal
comparator via an L.E.B. By inserting a resistor in series with the pin, you
control the level at which the skip operation takes place.

This pin is connected to an external bulk capacitor of typically 10 F.

the VCC bulk capacitor.

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2

DAP006

4.5 s
Delay

HV

V

CC

Ground

OVP

7.0

mA

PON

+

2.6 V

+

−
+

12 V, 10 V,

5.3 V (fault)

To Internal

Supply

Fault

Mngt.

*S and R are level triggered whereas S is edge

triggered. R has priority over the other inputs.

/2.77

+−

Demag

5.0 s

Blanking

S

S*
R*

Overload?

5.0 s

Timeout

Q

Q

R

+

−

Timeout Reset

−
+

+
50 mV

V

CC

Soft−start = 5.0 ms

1.0 V

Demag

10 V

Driver: src = 20

sink = 10

/3

200 a

when Drv

is OFF

380 ns

L.E.B.

Demag

Drv

FB

CS

Figure 2. Internal Circuit Architecture

MAXIMUM RATINGS

Rating

Continuous Power Supply or Drive Voltage
Transient Power Supply Voltage

Duration < 10 ms, I

VCC

< 10 mA

Maximum Voltage on all other pins except Pin 8 (HV), Pin 6 (VCC) and

Pin 5 (Drv)

Maximum Current into all pins except VCC (6), HV (8) and Demag (1) when 10 V

ESD diodes are activated
Maximum Current in Pin 1 Idem +3.0/−2.0 mA
Thermal Resistance, Junction−to−Case R
Thermal Resistance, Junction−to−Air, SOIC version R
Maximum Junction Temperature TJ
Temperature Shutdown − 155 °C
Hysteresis in Shutdown − 30 °C
Storage Temperature Range − −60 to +150 °C
ESD Capability, HBM Model (All pins except VCC and HV) − 2.0 kV
ESD Capability, Machine Model − 200 V
Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) decoupled to ground with 10 F
Minimum Voltage on Pin 8 (HV), Pin 6 (VCC) decoupled to ground with 10 F

Symbol

VCC, Drv

V

CC

Value

18
20

− −0.3 to 10 V

− 5.0 mA

57 °C/W
178 °C/W
150 °C

450 V

40 V

V

HVMAX

V

HVMIN

θ

θ

MAX

J−C
J−A

Units

V
V

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3

DAP006

ELECTRICAL CHARACTERISTICS (For typical values T

V

= 11 V unless otherwise noted)

CC

= 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,

J

Rating Pin Symbol Min Typ Max Unit

DYNAMIC SELF−SUPPLY

Vcc Increasing Level at which the Current Source Turns−off 6 VCC
Vcc Decreasing Level at which the Current Source Turns−on 6 VCC
Vcc Decreasing Level at which the Latch−off Phase Ends 6 VCC
Internal IC Consumption, No Output Load on Pin 5,

F

= 60 kHz, Duty Cycle = TBD

SW

Internal IC Consumption, 1.0 nF Output Load on Pin 5,

F

= 60 kHz, Duty Cycle = TBD

SW

6 ICC1 − 1.0 1.3

6 ICC2 − 1.6 2.0

OFF

ON

latch

10.8 12 12.9 V

9.1 10 10.6 V

− 5.3 − V

(Note 1)

(Note 1

Internal IC Consumption in Latch−off Phase 6 ICC3 − 330 −

INTERNAL START−UP CURRENT SOURCE (TJ u 0°C)

High−voltage Current Source, VCC = 10 V 8 IC1 4.3 7.0 9.6 mA
High−voltage Current Source, VCC = 0 8 IC2 − 8.0 − mA

DRIVE OUTPUT

Output Voltage Rise−time @ CL = 1.0 nF, 10−90% of Output

5 T

r

− 40 − ns

Signal

Output Voltage Fall−time @ CL = 1.0 nF, 10−90% of Output

5 T

f

− 20 − ns

Signal
Source Resistance 5 R
Sink Resistance 5 R

OH
OL

12 20 36 Ω

5.0 10 19 Ω

CURRENT COMPARATOR (Pin 5 Unloaded)

Input Bias Current @ 1.0 V Input Level on Pin 3 3 I
Maximum Internal Current Setpoint 3 I
Propagation Delay from Current Detection to Gate OFF State 3 T
Leading Edge Blanking Duration 3 T

IB

Limit

DEL
LEB

− 0.02 −

0.92 1.0 1.12 V

− 100 160 ns

− 380 − ns

Internal Current Offset Injected on the CS Pin during OFF Time 3 Iskip − 200 −

OVERVOLTAGE SECTION (VCC = 11 V)

Sampling Delay after ON Time 1 T
OVP Internal Reference Level 1 V

sample

ref

− 4.5 −

6.4 7.2 8.0 V

FEEDBACK SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 k)

Internal Pull−up Resistor 2 Rup − 20 − kΩ
Pin 3 to Current Setpoint Division Ratio − Iratio − 3.3 − −
Internal Soft−start − Tss − 5.0 − ms

DEMAGNETIZATION DETECTION BLOCK

Input Threshold Voltage (Vpin 1 Decreasing) 1 V
Hysteresis (Vpin 1 Decreasing) 1 V

th
H

35 50 90 mV

− 20 − mV

Input Clamp Voltage
High State (Ipin 1 = 3.0 mA)
Low State (Ipin 1 = −2.0 mA)

Demag Propagation Delay 1 T
Internal Input Capacitance at Vpin 1 = 1.0 V 1 C
Minimum T

(Internal Blanking Delay after TON) 1 T

OFF

Pin 1 Internal Resistance 1 R

1
1

VC

VC

dem

blank

par

H
L

8.0

−0.9

10

−0.7

12

−0.5

− 210 − ns

− 10 − pF

− 5.0 −

int

− 28 − kΩ

1. Max value at TJ = 0°C.

mA

mA

A

A

A

s

V
V

s

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4

DAP006

13.2

12.8

12.4

12.0

(V)

11.6

CC(off)

V

11.2

10.8

10.4

1.6

1.4

1.2

(mA)

1.0

CC1

I

0.8

TEMPERATURE (°C) TEMPERATURE (°C)

Figure 1. V

Threshold versus

CC(off)

Temperature

11.2

10.8

10.4

(V)

10

CC(on)

V

9.6

9.2

1251007550250−25

8.8

Figure 2. V

Threshold versus

CC(on)

1251007550250−25

Temperature

2.3

2.1

1.9

1.7

(mA)

CC2

I

1.5

0.6

0.4

12

10

8.0

(mA)

C1

I

6.0

4.0

2.0

TEMPERATURE (°C) TEMPERATURE (°C)

Figure 3. Current Consumption (No Load)

versus Temperature

TEMPERATURE (°C) TEMPERATURE (°C)

Figure 5. HV Current Source at VCC = 10 V

versus Temperature

1.3

1251007550250−25

1.1
1251007550250−25

Figure 4. Current Consumption (Loaded by

1 nF) versus Temperature

1.20

1.15

1.10

(V)

1.05

limit

I

1.00

0.95

1251007550250−25

0.90
12550 10075250−25

Figure 6. Maximum Current Setpoint versus

Temperature

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5

DAP006

()

OH

R

120

100

(mV)

(th)

V

40
35
30
25
20

15
10

5
0

TEMPERATURE (°C) TEMPERATURE (°C)

Figure 7. Drive Source Resistance versus

Temperature

80

60

40

20

20
18

16
14
12

()

10

OL

R

8.0

6.0

4.0

2.0

1251007550250−25

0

1251007550250−25

Figure 8. Drive Sink Resistance versus

Temperature

8.0

7.5

(V)

7.0

ref

V

6.5

0

1251007550250−25

TEMPERATURE (°C) TEMPERATURE (°C)

Figure 9. Demagnetization Detection

6.0
1251007550250−25

Figure 10. OVP Threshold versus Temperature

Threshold versus Temperature

7.0

6.5

6.0

5.5

(S)

off

5.0

T

4.5

4.0

3.5

Figure 11. Minimum T

TEMPERATURE (°C) TEMPERATURE (°C)

versus Temperature Figure 12. Demagnetization Detection Timeout

off

1251007550250−25

7.0

6.6

6.2

5.8

(S)

5.4

out

T

5.0

4.6

4.2

3.8
12550 10075250−25

versus Temperature

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6

DAP006

8.5

7.5

6.5

5.5

(S)

ss

T

4.5

3.5

2.5

TEMPERATURE (°C)

1251007550250−25

Figure 13. Internal Soft−start versus

Temperature

60

50

40

30

(k)

int

R

20

10

0

TEMPERATURE (°C)

Figure 14. DMG Pin Internal Resistance versus

Temperature

1251007550250−25

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7

DAP006

Application Information

Introduction

The DAP006 implements a standard current mode
architecture where the switch−off time is dictated by the
peak current setpoint whereas the core reset detection
triggers the turn−on event. This component represents the
ideal candidate where low part−count is the key parameter,
particularly in low−cost AC/DC adapters, consumer
electronics, auxiliary supplies, etc. Thanks to its
high−performance High−Voltage technology, the DAP006
incorporates all th e necessary components / features needed
to build a rugged and reliable Switch−Mode Power Supply
(SMPS):

• Transformer core reset detection: borderline / critical

operation is ensured whatever the operating conditions
are. As a result, there are virtually no primary switch
turn−on losses and no secondary diode recovery losses.
The converter also stays a first−order system and
accordingly eases the feedback loop design.

• Quasi−resonant operation: by delaying the turn−on

event, it is possible to re−start the MOSFET in the
minimum of the drain−source wave, ensuring reduced
EMI / video noise perturbations. In nominal power
conditions, the DAP006 operates in Borderline
Conduction Mode (BCM) also called Critical
Conduction Mode.

• Dynamic Self−Supply (DSS): due to its Very High

Voltage Integrated Circuit (VHVIC) technology,
ON Semiconductor’s DAP006 allows for a direct pin
connection to the high−voltage DC rail. A dynamic
current source charges up a capacitor and thus provides
a fully independent VCC level to the DAP006. As a
result, there is no need for an auxiliary winding whose
management is always a problem in variable output
voltage designs (e.g. battery chargers).

• Overvoltage Protection (OVP): by sampling the plateau

voltage on the demagnetization winding, the DAP006
goes into latched fault condition whenever an
over−voltage condition is detected. The controller stays
fully latched in this position until the VCC is cycled
down 4.0 V, e.g. when the user un−plugs the power
supply from the mains outlet and re−plugs it.

• External latch trip point: by externally forcing a level

on the OVP greater than the internal setpoint, it is
possible to latch−off the IC, e.g. with a signal coming
from a temperature sensor.

• Adjustable skip cycle level: by offering the ability to

tailor the level at which the skip cycle takes place, the
designer can make sure that the skip operation only
occurs at low peak current. This point guarantees a

noise−free operation with cheap transformer. This
option also offers the ability to fix the maximum
switching frequency when entering light load
conditions.

• Over Current Protection (OCP): by continuously

monitoring the FB line activity, DAP006 enters burst
mode as soon as the power supply undergoes an
overload. The device enters a safe low power operation
which prevents from any lethal thermal runaway. As
soon as the default disappears, the power supply
resumes operation. Unlike other controllers, overload
detection is performed independently of any auxiliary
winding level. In presence of a bad coupling between
both power and auxiliary windings, the short circuit
detection can be severely affected. The DSS naturally
shields you against these troubles.

Dynamic Self−Supply

The DSS principle is based on the charge/discharge of t h e
VCC bulk capacitor from a low level up to a higher level. We
can easily describe the current source operation with some
simple logical equations:

POWER−ON: IF VCC < V
ON, no output pulses

IF VCC decreasing > V

CCL

output is pulsing
IF VCC increasing < V

CCH

output is pulsing
Typical values are: V

CCH

To better understand the operational principle, Figure 15’s
sketch offers the necessary light.

V

= 2 V

RIPPLE

CC

V

CURRENT SOURCE

10.0 M 30.0 M 50.0 M 70.0 M 90.0 M

Figure 15. The Charge/Discharge Cycle Over a 10 mF

U

ON

V

Capacitor

CC

THEN Current Source is

CCH

THEN Current Source is OFF ,

THEN Current Source is ON,

= 12 V, V

= 12 V

VLOH

Output Pulses

U

VLOL

CCL

= 10 V

= 10 V

OFF

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8

DAP006

k

The DSS behavior actually depends on the internal IC
consumption and the MOSFET’s gate charge Qg. If we
select a MOSFET like the MTP2N60E, Qg equals 22 nC
(max). With a maximum switching frequency selected at
75 kHz, the average power necessary to drive the MOSFET
(excluding the driver efficiency and neglecting various
voltage drops) is:

Fsw ⋅ Qg ⋅ VCC with:

Fsw = maximum switching frequency
Qg = MOSFET’s gate charge
VCC = VGS level applied to the gate

To obtain the output current, simply divide this result by
VCC: I

= FSW ⋅ Qg = 1.6 mA. The total standby power

driver

consumption at no−load will therefore heavily rely on the
internal IC consumption plus the above driving current
(altered by the driver’s efficiency). Suppose that the IC is
supplied from a 350 VDC line. The current flowing through
pin 8 is a direct image of the DAP006 consumption
(neglecting the switching losses of the HV current source).
If I

equals 2.3 mA @ TJ = 60°C, then the power

CC2

dissipated (lost) by the IC is simply: 350 x 2.3 m = 805 mW .
For design and reliability reasons, it would be interested to
reduce this source of wasted power which increase the die
temperature. This can be achieved by using different
methods:

1. Use a MOSFET with lower gate charge Qg.

2. Connect pin through a diode (1N4007 typically) to
one of the mains input. The average value on pin 8

V

becomes

mainsPEAK @ 2



. Our power
contribution example drops to: 223 x 1.8 m =
512 mW. If a resistor is installed between the

mains and the diode, you further force the
dissipation to migrate from the package to the
resistor. The resistor value should account for
low−line startups.

MAINS

12

HV

C

bulk

1
2
3
4

1N4007

5

8

6

7
6
5

When using Figure 16 option, it is important to check the
absence of any negative ringing that could occur on pin 8.
The resistor in series should help to damp any parasitic LC
network that would ring when suddenly applying the power
to the IC. Also, since the power disappears during 20 ms
(half−wave rectification), CVCC should be calculated to
supply the IC during these holes in the supply

3. Permanently force the VCC level above V

CCH

with
an auxiliary winding. It will automatically
disconnect the internal start−up source and the IC
will be fully self−supplied from this winding.
Again, the total power drawn from the mains will
significantly decrease. Make sure the auxiliary
voltage never exceeds the 16 V limit.

Skipping Cycle Mode

The DAP006 automatically skips switching cycles when
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so−called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 17) and
follows the following formula:

1

@ Lp@ Ip2@ Fsw @ D

2

burst

with:

Lp = primary inductance
Fsw = switching frequency within the burst
Ip = peak current at which skip cycle occurs
D

= burst width / burst recurrence

burst

300 M

200 M

100 M

MAX PEAK
CURRENT

0

WIDTH

NORMAL CURRENT

MODE OPERATION

SKIP CYCLE

CURRENT LIMIT

Figure 16. A simple diode naturally reduces the

average voltage on pin 8

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RECURRENCE

315.4 U 882.7 U 1.450 M 2.017 M 2.585 M

Figure 17. The skip cycle takes place at low pea

currents which guaranties noise free operation

9

DAP006

DRIVER

DRIVER = HIGH ? I = 0
DRIVER = LOW ? I = 200 A

R

3

RESET

Figure 18. A patented method allows for skip level

selection via a series resistor inserted in series

+

−

2

+

with the current

skip

R

sense

The skip level selection is done through a simple resistor
inserted between the current sense input and the sense
element. Every time the DAP006 output driver goes low, a

200 A source forces a current to flow through the sense pin
(Figure 18): when the driver is high, the current source if off
and the current sense information is normally processed. As
soon as the driver goes low, the current source delivers
200 μA and develops a ground referenced voltage across
R

. If this voltage is below the feedback voltage, the

skip

current sense comparator stays in the low state and the
internal latch can be triggered by the next clock cycle. Now ,
if because of a low load mode the feedback voltage is below
R

level, then the current sense comparator permanently

skip

resets the latch and the next clock cycle (given by the
demagnetization detection) is ignored: we are skipping
cycles as shown by Figure 17. As soon as the feedback
voltage goes up again, there can be two situations: the
recurrent period is small and a new demagnetization
detection (next wave) signal triggers the DAP006. To the
opposite, in low output power conditions, no more ringing
waves are present on the drain and the toggling of the current
sense comparator alone initiates a new cycle start. Figure 19
depicts these two different situations.

DEMAG RE−START CURRENT SENSE RE−START

Figure 19. When the primary natural ringing becomes too low, the current sense

initiates a new cycle when FB passes the skip level

Demagnetization Detection

The core reset detection is done by monitoring the voltage
activity on the auxiliary winding. This voltage features a
FLYBACK polarity. The typical detection level is fixed at
50 mV as exemplified by Figure 20.

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7.0

5.0

3.0

1.0

−1.0

10

POSSIBLE

RE−STARTS

0 V

Figure 20. Core reset detection is done through a

dedicated auxiliary winding monitoring

50 mV

DAP006

TO INTERNAL

x

OMPARATOR

R

int

R

+ R

esd

= 28 k

int

Figure 21. Internal Pad Implementation

R

esd

1

ESD2 ESD1

R

1

4

dem

52

4

Au

3

An internal timer prevents any re−start within 5.0 s
further to the driver going−low transition. This prevents the
switching frequency to exceed (1 / TON + 5.0 s) but also
avoid false leakage inductance tripping at turn−off. In some
cases, the leakage inductance kick is so energetic, that a
slight filtering is necessary.

The DAP006 demagnetization detection pad features a
specific component arrangement as detai l e d by F i gure 21. In
this picture, the zener diodes network protect the IC against
any potential ESD discharge that could appear on the pins.
The first ESD diode connected to the pad, exhibits a parasitic
capacitance. When this parasitic capacitance (10 pF
typically) is combined with R

, a re−start delay is created

dem

and the possibility to switch right in the drain−source wave
exists. This guarantees QR operation with all the associated
benefits (low EMI, no turn−on losses etc.). R

should be

dem

calculated to limit the maximum current flowing through
pin 1 to less than +3/−2 mA: If during turn−on, the auxiliary
winding delivers 30 V (at the highest line level), then the
minimum R

value is defined by: (30 + 0.7)/3 mA =

dem

10.2 kΩ. This value will be further increased to introduce a
re−start delay and also a slight filtering in case of high
leakage energy.

Figure 22 portrays a typical VDS shot at nominal output
power.

400

300

Overvoltage Protection

The overvoltage protection works by sampling the plateau
voltage 4.5 s after the turn−off sequence. This delay
guarantees a clean plateau, providing that the leakage
inductance ringing has been fully damped. If this would not
be the case, the designer should install a small RC damper
across the transformer primary inductance connections.
Figure 23 shows where the sampling occurs on the auxiliary
winding.

7.0

5.0

3.0

1.0

0 V

−1.0

Figure 23. A voltage sample is taken 4.5 ms after

the turn−off sequence

SAMPLING HERE

When an OVP condition has been detected, the DAP006
enters a latch−off phase and stops all switching operations.
The controller stays fully latched in this position and the
DSS is still active, keeping the VCC between 10/12 V as in
normal operations. This state lasts until the VCC is cycled
down 4.0 V, e.g. when the user un−plugs the power supply
from the mains outlet.

By default, the OVP comparator is biased to a 2.6 V
reference level and pin1 is routed via a divide by 2.77
network. As a result, when V

reaches 7.2 V, the OVP

pin1

comparator is triggered. The threshold can thus be adjusted
by either modifying the power winding to auxiliary winding
turn ratios to match this 7.2 V level or insert a resistor from
pin1 to ground to cope with your design requirement.

200

100

0

42.0 U 56.0 U 70.0 U 84.0 U 98.0 U

Figure 22. The DAP006 Operates in

Borderline / Critical Operation

Latching Off the DAP006

In certain cases, it can be very convenient to externally
shut down permanently the DAP006 via a dedicated signal,
e.g. coming from a temperature sensor. The reset occurs
when the user un−plugs the power supply from the mains
outlet. T o trigger the latch−off, a simple PNP transistor c a n
do the work, as Figure 24 shows.

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11

R

dem

1

Thermistor

Figure 24. A simple transistor arrangement

triggers the latch−off as soon as the temperature

2
3
4

exceeds a given setpoint

8
7
6
5

C

VCC

Aux.
Winding

Shutting Off the DAP006

Shutdown can easily be implemented through a simple
NPN bipolar transistor as depicted by Figure 25. When OFF,
Q1 is transparent to the operation. When forward biased, the
transistor pulls the FB pin to ground (V

≈ 200 mV) and

CE(sat)

permanently disables the IC. A small time constant on the
transistor base will avoid false triggering (Figure 25).

DAP006

1

ON/OFF

10 k

Figure 25. A simple bipolar transistor totally

disables the IC

23

10 nF

Q1

2

1

3
4

8
7
6
5

Power Dissipation

The SOIC package offers a R

of 178°C/W when

J−A

wired on a min pad area. Adding some copper surface
around the PCB footprint will help decrease this number:
12 mm x 12 mm to drop R

down to 100°C/W with 35 

J−A

copper thickness (1 oz.) or 6.5 mm x 6.5 mm with 70 
copper thickness (2 oz.). Care must be taken to not exceed
the maximum dissipated power that can be computed using:

T

* T

+

Jmax

P

max

125°C, TA = 70°C and the min R

R

J * A

Amax

which is 310 mW for T

J−A

=

Jmax

. The main power

DAP006

dissipation (excluding the ohmic discharge losses in the
driver stage) is given by P = ICC x VCC. ICC corresponds to
the internal IC consumption at a given switching frequency
F

sw−max

driving current. If we assume that our system operates at
90 kHz from a 13 V VCC level and considering an internal
consumption of 1.0 mA, then the maximum gate charge Q

shall be less than:
250 nC. If larger MOSFETs are required, or if one wants to

lower TJ, please refer to AND8069 available to download
from www.onsemi.com/pub/ncp1200.

Overload Operation

controlled (e.g. wall adapters delivering raw DC level), it is
interesting to implement a true short−circuit protection. A
short−circuit actually forces the output voltage to be at a low
level, preventing a bias current to circulate in the
optocoupler LED. As a result, the FB pin level is pulled up
to 4.2 V, as internally imposed by the IC. The peak current
setpoint goes to the maximum and the supply delivers a
rather high power with all the associated effects. Please note
that this can also happen in case of feedback loss, e.g. a
broken optocoupler. To account for this situation, DAP006
hosts a dedicated overload detection circuitry. Once
activated, this circuitry imposes to deliver pulses in a burst
manner with a low duty−cycle. The system recovers when
the fault condition disappears.

the maximum until the output voltage reaches its target and
the feedback loop takes over. This period of time depends on
normal output load conditions and the maximum peak
current allowed by the system. The time−out used by this IC
works with the VCC decoupling capacitor: as soon as the
VCC decreases from the U
device internally watches for an overload current situation.
If this condition is still present when the U
reached, the controller stops the driving pulses, prevents the
self−supply current source to restart and puts all the circuitry
in standby, consuming as little as 330 A typical (ICC3
parameter). As a result, the VCC level slowly discharges
toward 0. When this level crosses 5.3 V typical, the
controller enters a new startup phase by turning the current
source on: VCC rises toward 12 V and again delivers output
pulses at the U
been removed before U
continues its normal operation. Otherwise, a new fault cycle
takes place. Figure 26 shows the evolution of the signals in
presence of a fault.

(the maximum is the worst case) plus the MOSFET

P

max

* I

V

Q

CCmax

v

g

F

CC1

sw * max

or a Q

gmax

less than

In applications where the output current is purposely not

During the start−up phase, the peak current is pushed to

level (typically 12 V) the

VLOH

level is

VLOL

crossing point. If the fault condition has

VLOH

approaches, then the IC

VLOL

g

http://onsemi.com

12

12 V

10 V

5.3 V

DAP006

V

CC

REGULATION

OCCURS HERE

LATCH−OFF

PHASE

DRV

DRIVER

PULSES

INTERNAL

FAULT FLAG

FAULT IS
RELAXED

FAULT OCCURS HERESTARTUP PHASE

Figure 26.

Soft−Start

The DAP006 features an internal 4 ms soft−start to soften
the constraints occurring in the power supply during
start−up. It is activated during the power on sequence. As
soon as VCC reaches V

, the peak current is gradually

CC(off)

increased from nearly zero up to the maximum clamping
level (e.g. 1.0 V). The soft−start is also activated during the
over current burst (OCP) sequence. Every restart attempt is
followed by a soft−start activation. Generally speaking, the
soft−start will be activated when VCC ramps up either from
zero (fresh power—on sequence) or 5.3 V, the latch—off
voltage occurring during OCP.

Calculating the Vcc Capacitor

As the above section describes, the fall down sequence
depends upon the VCC level: how long does it take for the
VCC line to go from 12 V to 10 V? The required time depends
on the start−up sequence of your system, i.e. when you first
apply the power to the IC. The corresponding transient fault
duration due to the output capacitor charging must be less
than the time needed to discharge from 12 V to 10 V,
otherwise the supply will not properly start. The test consists
in either simulating or measuring in the lab how much time
the system takes to reach the regulation at full load. Let’s
suppose that this time corresponds to 6.0 ms. Therefore a
VCC fall time of 10 ms could be well appropriated in order
to not trigger the overload detection circuitry. If the
corresponding IC consumption, including the MOSFET

TIME

TIME

TIME

If the fault is relaxed during the Vcc
natural fall down sequence, the IC
automatically resumes.
If the fault still persists when Vcc
reached U
cuts everything off until recovery.

, then the controller

VLOL

drive, establishes at 1.6 mA (e.g. with a 10 nC Qg), we can
calculate the required capacitor using the following

formula: t +

V @ C

, with ΔV = 2.0 V. Then for a wanted

i

Δt of 10 ms, C equals 9.0F or 22F for a standard value.
When an overload condition occurs, the IC blocks its
internal circuitry and its consumption drops to 330 A
typical. This happens at VCC = 10 V and it remains stuck
until VCC reaches 5.3 V: we are in latch−off phase. Again,
using the calculated 22 F and 600 A current consumption,
this latch−off phase lasts: (10 − 5.3) x 22   313 ms.

Protecting Pin 8 Against Negative Spikes

As any CMOS controller, DAP006 is sensitive to negative
voltages that could appear on its pins. T o avoid any adverse
latch−up of the IC, we strongly recommend to insert a
resistor in series with pin 8 or apply Figure 2 trick. This
resistor (or this diode in case of Figure 2) prevents from
adversely latching the controller in case of negative spikes
appearing on the bulk capacitor during the power−off
sequence. A typical value of 6.8 k/0.5 W is suitable. When
using an auxiliary winding, this resistor does not dissipate
any power since it only sees current during the startup
sequence and during overload.

http://onsemi.com

13

DAP006

Operation Shots

Below are some oscilloscope shots captured at
Vin = 120 VDC with a transformer featuring an 800 H
primary inductance.

Figure 27.

This plot gathers waveforms captured at three different
operating points:

1st upper plot: free run, valley switching operation,
P

= 26 W

out

2nd middle plot: min T

clamps the switching frequency

off

and selects the second valley
3rd lowest plot: the skip slices the second valley pattern

and will further expand the burst as P

goes low

out

This picture explains how the 200 A internal offset

current creates the skip cycle level.

VCC (5 V/div)

V

(5 V/div)

GATE

Figure 29.

The short−circuit protection forces the IC to enter burst in

presence of a secondary overload.

V

(5 V/div)

GATE

200 A X R

Current Sense Pin (200 mV/div)

SKIP

V

Rsense

(200 mV/div)

Figure 28.

ORDERING INFORMATION

Device Type Marking Package Shipping

SCY99006R2 DAP006 DAP6 SOIC−8 2500/Tape & Reel

http://onsemi.com

14

(SO−8)

−Y−

−Z−

DAP006

PACKAGE DIMENSIONS

D1, D2 SUFFIX

CASE 751−07

M

Y

N

ISSUE AG

X 45

_

M

K

J

−X−
A

58

B

1

S

0.25 (0.010)

4

M

G

C

SEATING
PLANE

0.10 (0.004)

H

D

0.25 (0.010) Z

M

Y

SXS

SOLDERING FOOTPRINT*

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8

____

N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

INCHES

1.52

0.060

7.0

0.275

0.6

0.024

4.0

0.155

1.270

0.050

SCALE 6:1

ǒ

inches

mm

Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

The product described herein (DAP006), may be covered by one or more of the following U.S. patents: 6,385,060; 6,385,061. There may
be other patents pending.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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15

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For additional information, please contact your
local Sales Representative.

DAP006/D