Controller for Free Running
Quasi−Resonant Operation
The DAP006 combines a true current mode modulator
and a demagnetization detector to ensure full borderline/
critical Conduction Mode in any load/line conditions and
minimum drain voltage switching (Quasi−Resonant
operation). Due to its inherent skip cycle capability, the
controller enters burst mode as soon as the power demand
falls below a predetermined level. As this happens at low
peak current, no audible noise can be heard. An internal
5.0 s timer prevents the free−run frequency to exceed the
150 kHz CISPR−22 EMI starting limit while the skip
adjustment capability lets the user select the frequency at
which the burst foldback takes place.
The Dynamic Self−Supply (DSS) drastically simplifies
the transformer design in avoiding the use of an auxiliary
winding. This feature is particularly useful in applications
where the output voltage varies during operation (e.g.
battery chargers). Due to its high−voltage technology, the IC
is directly connected to the high−voltage DC rail. The DSS
also offers a better overload trip point.
The transformer core reset detection is done through an
auxiliary winding which, brought via a dedicated pin, also
enables fast O v e r− Voltage Protection (OVP). Once an OVP
has been detected, the IC permanently latches−off.
Finally, the continuous feedback signal monitoring
implemented with an over−current fault protection circuitry
(OCP) makes the final design rugged and reliable.
Features
• Free−Running Borderline/Critical Mode
Quasi−Resonant Operation
• Current−Mode with Adjustable Skip−Cycle Capability
• No Auxiliary Winding V
Operation
CC
• Auto−Recovery Over Current Protection
• Latching Over Voltage Protection
• External Latch Triggering, e.g. Via Over−Temperature
See detailed ordering and shipping information in the package dimensions
section on page 14 of this data sheet.
PIN CONNECTIONS
Dmg
18
FB
2
3
CS
Gnd
4
(Top View)
1Publication Order Number:
HV
NC
7
V
6
CC
5
Drv
DAP006/D
DAP006
OVP &
+
Demag
Universal Network
*Please refer to the application information section
*
Dmg
FB
CS
Gnd
V
HV
NC
CC
Drv
8
7
6
5
+
Y1 Type
1
2
3
4
12 V @ 1.0 A
+
Ground
Figure 1. Typical Application
PIN FUNCTION DESCRIPTION
Pin No.
1DemagCore reset detection and OVPThe auxiliary FLYBACK signal ensures discontinuous operation and
2FBSets the peak current setpointBy connecting an optocoupler to this pin, the peak current setpoint is
3CSCurrent sense input and skip
4GndThe IC ground−
5DrvDriving pulsesThe driver’s output to an external MOSFET.
6V
7NC−This unconnected pin ensures adequate creepage distance.
8HVHigh−voltage pinConnected to the high−voltage rail, this pin injects a constant current into
Pin Name
CC
Function
cycle level selection
Supplies the IC
Description
offers a fixed overvoltage detection level of 7.2 V.
adjusted accordingly to the output power demand. By bringing this pin
below the internal skip level, device shuts off.
This pin senses the primary current and routes it to the internal
comparator via an L.E.B. By inserting a resistor in series with the pin, you
control the level at which the skip operation takes place.
This pin is connected to an external bulk capacitor of typically 10 F.
the VCC bulk capacitor.
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2
DAP006
4.5 s
Delay
HV
V
CC
Ground
OVP
7.0
mA
PON
+
2.6 V
+
−
+
12 V, 10 V,
5.3 V (fault)
To Internal
Supply
Fault
Mngt.
*S and R are level triggered whereas S is edge
triggered. R has priority over the other inputs.
/2.77
+−
Demag
5.0 s
Blanking
S
S*
R*
Overload?
5.0 s
Timeout
Q
Q
R
+
−
Timeout Reset
−
+
+
50 mV
V
CC
Soft−start = 5.0 ms
1.0 V
Demag
10 V
Driver: src = 20
sink = 10
/3
200 a
when Drv
is OFF
380 ns
L.E.B.
Demag
Drv
FB
CS
Figure 2. Internal Circuit Architecture
MAXIMUM RATINGS
Rating
Continuous Power Supply or Drive Voltage
Transient Power Supply Voltage
Duration < 10 ms, I
VCC
< 10 mA
Maximum Voltage on all other pins except Pin 8 (HV), Pin 6 (VCC) and
Pin 5 (Drv)
Maximum Current into all pins except VCC (6), HV (8) and Demag (1) when 10 V
ESD diodes are activated
Maximum Current in Pin 1Idem+3.0/−2.0mA
Thermal Resistance, Junction−to−CaseR
Thermal Resistance, Junction−to−Air, SOIC versionR
Maximum Junction TemperatureTJ
Temperature Shutdown−155°C
Hysteresis in Shutdown−30°C
Storage Temperature Range−−60 to +150°C
ESD Capability, HBM Model (All pins except VCC and HV)−2.0kV
ESD Capability, Machine Model−200V
Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) decoupled to ground with 10 F
Minimum Voltage on Pin 8 (HV), Pin 6 (VCC) decoupled to ground with 10 F
Symbol
VCC, Drv
V
CC
Value
18
20
−−0.3 to 10V
−5.0mA
57°C/W
178°C/W
150°C
450V
40V
V
HVMAX
V
HVMIN
θ
θ
MAX
J−C
J−A
Units
V
V
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3
DAP006
ELECTRICAL CHARACTERISTICS (For typical values T
V
= 11 V unless otherwise noted)
CC
= 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,
J
RatingPinSymbolMinTypMaxUnit
DYNAMIC SELF−SUPPLY
Vcc Increasing Level at which the Current Source Turns−off6VCC
Vcc Decreasing Level at which the Current Source Turns−on6VCC
Vcc Decreasing Level at which the Latch−off Phase Ends6VCC
Internal IC Consumption, No Output Load on Pin 5,
F
= 60 kHz, Duty Cycle = TBD
SW
Internal IC Consumption, 1.0 nF Output Load on Pin 5,
F
= 60 kHz, Duty Cycle = TBD
SW
6ICC1−1.01.3
6ICC2−1.62.0
OFF
ON
latch
10.81212.9V
9.11010.6V
−5.3−V
(Note 1)
(Note 1
Internal IC Consumption in Latch−off Phase6ICC3−330−
INTERNAL START−UP CURRENT SOURCE (TJ u 0°C)
High−voltage Current Source, VCC = 10 V8IC14.37.09.6mA
High−voltage Current Source, VCC = 08IC2−8.0−mA
DRIVE OUTPUT
Output Voltage Rise−time @ CL = 1.0 nF, 10−90% of Output
5T
r
−40−ns
Signal
Output Voltage Fall−time @ CL = 1.0 nF, 10−90% of Output
5T
f
−20−ns
Signal
Source Resistance5R
Sink Resistance5R
OH
OL
122036Ω
5.01019Ω
CURRENT COMPARATOR (Pin 5 Unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 33I
Maximum Internal Current Setpoint3I
Propagation Delay from Current Detection to Gate OFF State3T
Leading Edge Blanking Duration3T
IB
Limit
DEL
LEB
−0.02−
0.921.01.12V
−100160ns
−380−ns
Internal Current Offset Injected on the CS Pin during OFF Time3Iskip−200−
OVERVOLTAGE SECTION (VCC = 11 V)
Sampling Delay after ON Time1T
OVP Internal Reference Level1V