ON CS51031 Schematic [ru]

CS51031
Fast P−Ch FET Buck Controller
The CS51031 is a switching controller for use in DC−DC converters. It can be used in the buck topology with a minimum number of external components. The CS51031 consists of a V monitor for controlling the state of the device, 1.0 A power driver for controlling the gate of a discrete P−Channel transistor, fixed frequency oscillator, short circuit protection timer, programmable Soft−Start, precision reference, fast output voltage monitoring comparator, and output stage driver logic with latch.
The high frequency oscillator allows the use of small inductors and output capacitors, minimizing PC board area and systems cost. The programmable Soft−Start reduces current surges at startup. The short circuit protection timer significantly reduces the duty cycle to approximately 1/30 of its cycle during short circuit conditions.
Features
1.0 A Totem Pole Output Driver
High Speed Oscillator (700 kHz max)
No Stability Compensation Required
Lossless Short Circuit Protection
V
Monitor
CC
2.0% Precision Reference
Programmable Soft−Start
Wide Ambient Temperature Range:
Industrial Grade: −40°C to 85°CCommercial Grade: 0°C to 70°C
Pb−Free Packages are Available
5.0 V−12 V
C
IN
47 mF
MP
1
V
GATE
V
GATE
V
C
MBRS360
D
1
IRF7416
CC
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8
1
SOIC−8 D SUFFIX CASE 751
MARKING DIAGRAM
8
51031
ALYWx
G
1
51031 = Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week x = Continuation of Device Code
G = Pb−Free Package
x = Y or G
PIN CONNECTIONS
PGND
C
C
OSC
470 pF
© Semiconductor Components Industries, LLC, 2005
October, 2005 − Rev. 11
OSC
GND
Figure 1. Typical Application Diagram
CS
CS51031
V
V
FB
RV
100 W CV
0.1 mF
R
1.5 kW
A
CS
0.1 mF
R
2.5 kW
C
0.1 mF
1
V
GATE
L
4.7 mH
B
V
O
3.3 V @ 3 A
See detailed ordering and shipping information in the package
C
O
100 mF × 2
1 Publication Order Number:
dimensions section on page 2 of this data sheet.
C
OSC
GND
ORDERING INFORMATION
V
C
CSPGND
V
V
FB
CS51031/D
CS51031
ORDERING INFORMATION
Operating
Device
CS51031YD8 CS51031YD8G SOIC−8
Temperature Range
Package Shipping
SOIC−8 98 Units / Rail
98 Units / Rail
(Pb−Free) CS51031YDR8 SOIC−8 2500 / Tape & Reel CS51031YDR8G SOIC−8
−40°C < TA < 85°C
2500 / Tape & Reel
(Pb−Free) CS51031GD8 CS51031GD8G SOIC−8
CS51031GDR8 SOIC−8 2500 / Tape & Reel
0°C < TA < 70°C
CS51031GDR8G SOIC−8
SOIC−8 98 Units / Rail
98 Units / Rail
(Pb−Free)
2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MAXIMUM RATINGS
Rating Value Unit
Power Supply Voltage, V Driver Supply Voltage, V Driver Output Voltage, V C
, CS, VFB (Logic Pins) 6.0 V
OSC
Peak Output Current 1.0 A Steady State Output Current 200 mA Operating Junction Temperature, T Operating Temperature Range, T Storage Temperature Range, T
J
A
S
ESD (Human Body Model) 2.0 kV Lead Temperature Soldering: Wave Solder: (through hole styles only) (Note 1)
Reflow (SMD styles only) (Note 2)
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
1. 10 sec. maximum.
2. 60 sec. max above 183°C.
20 V 20 V 20 V
150 °C
−40 to 85 °C
−65 to 150 °C
260 peak 230 peak
°C °C
PACKAGE LEAD DESCRIPTION
Package Pin Number Pin Symbol Function
1 V
GATE
Driver pin to gate of external P−Ch FET. 2 PGND Output power stage ground connection. 3 C
OSC
Oscillator frequency programming capacitor. 4 GND Logic ground. 5 V 6 V
FB CC
Feedback voltage input.
Logic supply voltage. 7 CS Soft−Start and fault timing capacitor. 8 V
C
Driver supply voltage.
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2
CS51031
ELECTRICAL CHARACTERISTICS (Specifications apply for 4.5 V
16 V, 3.0 V VC 16 V;
Industrial Grade: −40°C < TA < 85°C; −40°C < TJ < 125°C: Commercial Grade: 0 °C < TA < 70°C; 0°C < TJ < 125°C, unless otherwis e specified.)
Characteristic Test Conditions Min Typ Max Unit
Oscillator VFB = 1.2 V
Frequency C Charge Current 1.4 V < V Discharge Current 2.7 V > V Maximum Duty Cycle 1 − (t
Short Circuit Timer
Charge Current 1.0 V < VCS < 2.0 V 175 264 325 Fast Discharge Current 2.55 V > VCS > 2.4 V 40 66 80 Slow Discharge Current 2.4 V > VCS > 1.5 V 4.0 6.0 10
= 470 pF 160 200 240 kHz
OSC
< 2.0 V 110
COSC
> 2.0 V 660
COSC
) 80.0 83.3 %
OFF/tON
VFB = 1.0 V; CS = 0.1 mF; V
COSC
= 2.0 V
mA mA
mA mA mA
Start Fault Inhibit Time 0 V < VCS < 2.5 V 0.70 0.85 1.40 ms Valid Fault Time 2.6 V > VCS > 2.4 V 0.2 0.3 0.45 ms GATE Inhibit Time 2.4 V > VCS > 1.5 V 9.0 15 23 ms Fault Duty Cycle 2.5 3.1 4.6 %
CS Comparator VFB = 1.0 V
Fault Enable CS Voltage 2.5 V Max CS Voltage VFB = 1.5 V 2.6 V Fault Detect Voltage VCS when GATE goes high 2.4 V Fault Inhibit Voltage Minimum V
CS
1.5 V Hold Off Release Voltage VFB = 0 V 0.4 0.7 1.0 V Regulator Threshold Voltage Clamp VCS = 1.5 V 0.725 0.866 1.035 V
VFB Comparators V
Regulator Threshold Voltage TJ = 25°C (Note 3)
Fault Threshold Voltage TJ = 25°C (Note 3)
= VCS = 2.0 V
COSC
TJ = −40 to 125°C
TJ = −40 to 125°C
1.225
1.210
1.12
1.10
1.250
1.250
1.15
1.15
1.275
1.290
1.17
1.19
V V
V
V Threshold Line Regulation 4.5 V ≤ VCC 16 V 6.0 15 mV Input Bias Current VFB = 0 V 1.0 4.0
mA Voltage Tracking (Regulator Threshold − Fault Threshold Voltage) 70 100 120 mV Input Hysteresis Voltage 4.0 20 mV
Power Stage VCC = VC = 10 V; VFB = 1.2 V
GATE DC Low Saturation Voltage V GATE DC High Saturation Voltage V Rise Time C Fall Time C
= 1.0 V; 200 mA Sink 1.2 1.5 V
COSC
= 2.7 V; 200 mA Source; VC = V
COSC
= 1.0 nF; 1.5 V < V
GATE
= 1.0 nF; 9.0 V > V
GATE
GATE GATE
GATE
< 9.0 V 25 60 ns > 1.5 V 25 60 ns
1.5 2.1 V
VCC Monitor
Turn−On Threshold 4.200 4.400 4.600 V Turn−Off Threshold 4.085 4.300 4.515 V Hysteresis 65 130 200 mV
Current Drain
I
I
C
Shutdown I
4.5 V < VCC < 16 V, Gate switching 4.5 6.0 mA
3.0 V < VC < 16 V, Gate non−switching 2.7 4.0 mA VCC = 4.0 500 900
mA
3. Guaranteed by design, not 100% tested in production.
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3
CS51031
V
V
REF
RG
I
C
C
OSC
7I
C
+
V
V
V
= 3.3 V
REF
I
T
CS
I
T
55
VCCOK
G3
I
T
5
3.3 V
+
+
+
2.5 V1.5 V
V
REF
CS Comparator
+
A2
+
2.5 V1.5 V
2.4 V
Oscillator Comparator
A1
− A3
+
+
G1
G2
Comp
G4
G5
Slow Discharge Comparator
V
GATE
Flip−Flop
R
F2
S
Hold Off
Comp
Fault
1.15 V
+
+
R
F1
S
Slow Discharge
Flip−Flop
Q
Q
+
Q
Q
A6
0.7 V +
V
FB
Comparator
1.25 V
+
CS Charge Sense Comparator
A4
+
+
+
2.3 V
C
V
GATE
PGND
V
FB
GND
Figure 2. Block Diagram
CIRCUIT DESCRIPTION
THEORY OF OPERATION
Control Scheme
The CS51031 monitors the output voltage to determine when to turn on the P−Ch FET. If VFB falls below the internal reference voltage of 1.25 V during the oscillator’s charge cycle, the P−Ch FET is turned on and remains on for the
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duration of the charge time. The P−Ch FET gets turned off and remains off during the oscillator’s discharge time with the maximum duty cycle to 80%. It requires 7.0 mV typical, and 20 mV maximum ripple on the VFB pin is required to operate. This method of control does not require any loop stability compensation.
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