The CS51031 is a switching controller for use in DC−DC
converters. It can be used in the buck topology with a minimum
number of external components. The CS51031 consists of a V
monitor for controlling the state of the device, 1.0 A power driver for
controlling the gate of a discrete P−Channel transistor, fixed frequency
oscillator, short circuit protection timer, programmable Soft−Start,
precision reference, fast output voltage monitoring comparator, and
output stage driver logic with latch.
The high frequency oscillator allows the use of small inductors and
output capacitors, minimizing PC board area and systems cost. The
programmable Soft−Start reduces current surges at startup. The short
circuit protection timer significantly reduces the duty cycle to
approximately 1/30 of its cycle during short circuit conditions.
Features
• 1.0 A Totem Pole Output Driver
• High Speed Oscillator (700 kHz max)
• No Stability Compensation Required
• Lossless Short Circuit Protection
• V
Monitor
CC
• 2.0% Precision Reference
• Programmable Soft−Start
• Wide Ambient Temperature Range:
♦ Industrial Grade: −40°C to 85°C
♦ Commercial Grade: 0°C to 70°C
• Pb−Free Packages are Available
5.0 V−12 V
C
IN
47 mF
MP
1
V
GATE
V
GATE
V
C
MBRS360
D
1
IRF7416
CC
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8
1
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
51031
ALYWx
G
1
51031 = Device Code
A= Assembly Location
L= Wafer Lot
Y= Year
W= Work Week
x= Continuation of Device Code
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MAXIMUM RATINGS
RatingValueUnit
Power Supply Voltage, V
Driver Supply Voltage, V
Driver Output Voltage, V
C
, CS, VFB (Logic Pins)6.0V
OSC
CC
C
GATE
Peak Output Current1.0A
Steady State Output Current200mA
Operating Junction Temperature, T
Operating Temperature Range, T
Storage Temperature Range, T
J
A
S
ESD (Human Body Model)2.0kV
Lead Temperature Soldering: Wave Solder: (through hole styles only) (Note 1)
Reflow (SMD styles only) (Note 2)
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 10 sec. maximum.
2. 60 sec. max above 183°C.
20V
20V
20V
150°C
−40 to 85°C
−65 to 150°C
260 peak
230 peak
†
°C
°C
PACKAGE LEAD DESCRIPTION
Package Pin NumberPin SymbolFunction
1V
GATE
Driver pin to gate of external P−Ch FET.
2PGNDOutput power stage ground connection.
3C
OSC
Oscillator frequency programming capacitor.
4GNDLogic ground.
5V
6V
FB
CC
Feedback voltage input.
Logic supply voltage.
7CSSoft−Start and fault timing capacitor.
8V
C
Driver supply voltage.
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2
CS51031
ELECTRICAL CHARACTERISTICS (Specifications apply for 4.5 ≤ V
≤ 16 V, 3.0 V ≤ VC ≤ 16 V;
CC
Industrial Grade: −40°C < TA < 85°C; −40°C < TJ < 125°C: Commercial Grade: 0 °C < TA < 70°C; 0°C < TJ < 125°C, unless otherwis e specified.)
CharacteristicTest ConditionsMinTypMaxUnit
OscillatorVFB = 1.2 V
FrequencyC
Charge Current1.4 V < V
Discharge Current2.7 V > V
Maximum Duty Cycle1 − (t
Short Circuit Timer
Charge Current1.0 V < VCS < 2.0 V175264325
Fast Discharge Current2.55 V > VCS > 2.4 V406680
Slow Discharge Current2.4 V > VCS > 1.5 V4.06.010
3. Guaranteed by design, not 100% tested in production.
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3
CS51031
V
V
REF
RG
I
C
C
OSC
7I
C
+
−
V
CC
V
CC
V
= 3.3 V
REF
I
T
CS
I
T
55
VCCOK
G3
I
T
5
3.3 V
+
−
+
−
+
2.5 V1.5 V
−
V
REF
CS
Comparator
+
A2
−
+
2.5 V1.5 V
−
2.4 V
Oscillator
Comparator
A1
−
A3
+
+
−
G1
G2
Comp
G4
G5
Slow Discharge
Comparator
V
GATE
Flip−Flop
R
F2
S
Hold Off
Comp
−
Fault
1.15 V
+
+
−
R
F1
S
Slow Discharge
Flip−Flop
Q
Q
+
−
Q
Q
A6
0.7 V
+
−
V
FB
Comparator
−
1.25 V
+
CS Charge
Sense
Comparator
A4
+
+
−
+
−
−
2.3 V
C
V
GATE
PGND
V
FB
GND
Figure 2. Block Diagram
CIRCUIT DESCRIPTION
THEORY OF OPERATION
Control Scheme
The CS51031 monitors the output voltage to determine
when to turn on the P−Ch FET. If VFB falls below the internal
reference voltage of 1.25 V during the oscillator’s charge
cycle, the P−Ch FET is turned on and remains on for the
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duration of the charge time. The P−Ch FET gets turned off
and remains off during the oscillator’s discharge time with
the maximum duty cycle to 80%. It requires 7.0 mV typical,
and 20 mV maximum ripple on the VFB pin is required to
operate. This method of control does not require any loop
stability compensation.
4
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