The CS51031 is a switching controller for use in DC−DC
converters. It can be used in the buck topology with a minimum
number of external components. The CS51031 consists of a V
monitor for controlling the state of the device, 1.0 A power driver for
controlling the gate of a discrete P−Channel transistor, fixed frequency
oscillator, short circuit protection timer, programmable Soft−Start,
precision reference, fast output voltage monitoring comparator, and
output stage driver logic with latch.
The high frequency oscillator allows the use of small inductors and
output capacitors, minimizing PC board area and systems cost. The
programmable Soft−Start reduces current surges at startup. The short
circuit protection timer significantly reduces the duty cycle to
approximately 1/30 of its cycle during short circuit conditions.
Features
• 1.0 A Totem Pole Output Driver
• High Speed Oscillator (700 kHz max)
• No Stability Compensation Required
• Lossless Short Circuit Protection
• V
Monitor
CC
• 2.0% Precision Reference
• Programmable Soft−Start
• Wide Ambient Temperature Range:
♦ Industrial Grade: −40°C to 85°C
♦ Commercial Grade: 0°C to 70°C
• Pb−Free Packages are Available
5.0 V−12 V
C
IN
47 mF
MP
1
V
GATE
V
GATE
V
C
MBRS360
D
1
IRF7416
CC
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8
1
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
51031
ALYWx
G
1
51031 = Device Code
A= Assembly Location
L= Wafer Lot
Y= Year
W= Work Week
x= Continuation of Device Code
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MAXIMUM RATINGS
RatingValueUnit
Power Supply Voltage, V
Driver Supply Voltage, V
Driver Output Voltage, V
C
, CS, VFB (Logic Pins)6.0V
OSC
CC
C
GATE
Peak Output Current1.0A
Steady State Output Current200mA
Operating Junction Temperature, T
Operating Temperature Range, T
Storage Temperature Range, T
J
A
S
ESD (Human Body Model)2.0kV
Lead Temperature Soldering: Wave Solder: (through hole styles only) (Note 1)
Reflow (SMD styles only) (Note 2)
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 10 sec. maximum.
2. 60 sec. max above 183°C.
20V
20V
20V
150°C
−40 to 85°C
−65 to 150°C
260 peak
230 peak
†
°C
°C
PACKAGE LEAD DESCRIPTION
Package Pin NumberPin SymbolFunction
1V
GATE
Driver pin to gate of external P−Ch FET.
2PGNDOutput power stage ground connection.
3C
OSC
Oscillator frequency programming capacitor.
4GNDLogic ground.
5V
6V
FB
CC
Feedback voltage input.
Logic supply voltage.
7CSSoft−Start and fault timing capacitor.
8V
C
Driver supply voltage.
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2
CS51031
ELECTRICAL CHARACTERISTICS (Specifications apply for 4.5 ≤ V
≤ 16 V, 3.0 V ≤ VC ≤ 16 V;
CC
Industrial Grade: −40°C < TA < 85°C; −40°C < TJ < 125°C: Commercial Grade: 0 °C < TA < 70°C; 0°C < TJ < 125°C, unless otherwis e specified.)
CharacteristicTest ConditionsMinTypMaxUnit
OscillatorVFB = 1.2 V
FrequencyC
Charge Current1.4 V < V
Discharge Current2.7 V > V
Maximum Duty Cycle1 − (t
Short Circuit Timer
Charge Current1.0 V < VCS < 2.0 V175264325
Fast Discharge Current2.55 V > VCS > 2.4 V406680
Slow Discharge Current2.4 V > VCS > 1.5 V4.06.010
3. Guaranteed by design, not 100% tested in production.
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3
CS51031
V
V
REF
RG
I
C
C
OSC
7I
C
+
−
V
CC
V
CC
V
= 3.3 V
REF
I
T
CS
I
T
55
VCCOK
G3
I
T
5
3.3 V
+
−
+
−
+
2.5 V1.5 V
−
V
REF
CS
Comparator
+
A2
−
+
2.5 V1.5 V
−
2.4 V
Oscillator
Comparator
A1
−
A3
+
+
−
G1
G2
Comp
G4
G5
Slow Discharge
Comparator
V
GATE
Flip−Flop
R
F2
S
Hold Off
Comp
−
Fault
1.15 V
+
+
−
R
F1
S
Slow Discharge
Flip−Flop
Q
Q
+
−
Q
Q
A6
0.7 V
+
−
V
FB
Comparator
−
1.25 V
+
CS Charge
Sense
Comparator
A4
+
+
−
+
−
−
2.3 V
C
V
GATE
PGND
V
FB
GND
Figure 2. Block Diagram
CIRCUIT DESCRIPTION
THEORY OF OPERATION
Control Scheme
The CS51031 monitors the output voltage to determine
when to turn on the P−Ch FET. If VFB falls below the internal
reference voltage of 1.25 V during the oscillator’s charge
cycle, the P−Ch FET is turned on and remains on for the
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duration of the charge time. The P−Ch FET gets turned off
and remains off during the oscillator’s discharge time with
the maximum duty cycle to 80%. It requires 7.0 mV typical,
and 20 mV maximum ripple on the VFB pin is required to
operate. This method of control does not require any loop
stability compensation.
4
CS51031
FB
2.6 V
V
V
Startup
The CS51031 has an externally programmable Soft−Start
feature that allows the output voltage to come up slowly,
preventing voltage overshoot on the output.
At startup, the voltage on all pins is zero. As VCC rises, the
VC voltage along with the internal resistor RG keeps the
P−Ch FET off. As VCC and VC continue to rise, the oscillator
capacitor (C
(CS) charges via internal current sources. C
) and the Soft−Start/Fault Timing capacitor
OSC
gets charged
OSC
by the current source IC and CS gets charged by the IT source
combination described by:
ICS+ I
ǒ
*
T
55
)
Ǔ
5
I
I
T
T
The internal Holdoff Comparator ensures that the external
P−Ch FET is off until VCS > 0.7 V, preventing the GATE
flip−flop (F2) from being set. This allows the oscillator to
reach its operating frequency before enabling the drive
output. Soft−Start is obtained by clamping the V
FB
comparator’s (A6) reference input to approximately 1/2 of
the voltage at the CS pin during startup, permitting the
control loop and the output voltage to slowly increase. Once
the CS pin charges above the Holdoff Comparator trip point
of 0.7 V, the low feedback to the VFB Comparator sets the
GATE flip−flop during C
GATE flip−flop is set, V
’s charge cycle. Once the
OSC
goes low and turns on the
GATE
P−Ch FET. When VCS exceeds 2.3 V, the CS charge sense
comparator (A4) sets the VFB comparator reference to
1.25 V completing the startup cycle.
Lossless Short Circuit Protection
The CS51031 has “lossless” short circuit protection since
there is no current sense resistor required. When the voltage
at the CS pin (the fault timing capacitor voltage) reaches
2.5 V during startup, the fault timing circuitry is enabled by
A2. During normal operation the CS voltage is 2.6 V . During
a short circuit or a transient condition, the output voltage
moves lower and the voltage at VFB drops. If VFB drops
below 1.15 V, the output of the fault comparator goes high
and the CS51031 goes into a fast discharge mode. The fault
timing capacitor, CS, discharges to 2.4 V. If the VFB voltage
is still below 1.15 V when the CS pin reaches 2.4 V, a valid
fault condition has been detected. The slow discharge
comparator output goes high and enables gate G5 which sets
the slow discharge flip−flop. The V
flip−flop resets and
GATE
the output switch is turned off. The fault timing capacitor is
slowly discharged to 1.5 V. The CS51031 then enters a
normal startup routine. If the fault is still present when the
fault timing capacitor voltage reaches 2.5 V, the fast and
slow discharge cycles repeat as shown in figure 3.
If the VFB voltage is above 1 .15 V w hen C S r eaches 2 .4 V
a fault condition is not detected, normal operation resumes
and CS charges back to 2.6 V. This reduces the chance of
erroneously detecting a load transient as a fault condition.
V
CS
2.4 V
1.5 V
0.7 V
0 V
GATE
1.25 V
1.15 V
V
FB
S1
START
STARTNORMAL OPERATION
Figure 3. Voltage on Start Capacitor (VGS), the Gate (V
Feedback Loop (V
S2S1
), During Startup, Normal and Fault Conditions
S2
S3
td1T
t
FAULT
S3
FAULT
GATE
S1
t
RESTART
), and in the
S2
S3
td2t
FAULT
2.5
S3
0 V
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5
CS51031
Buck Regulator Operation
A block diagram of a typical buck regulator is shown in
Figure 4. If we assume that the output transistor is initially
off, and the system is in discontinuous operation, the
inductor current IL is zero and the output voltage is at its
nominal value. The current drawn by the load is supplied by
the output capacitor CO. When the voltage across CO drops
below the threshold established by the feedback resistors R1
Q
V
IN
C
IN
1
D
1
Control
Feedback
Figure 4. Buck Regulator Block Diagram
and R2 and the reference voltage V
, the power transistor
REF
Q1 switches on and current flows through the inductor to the
output. The inductor current rises at a rate determined by
(V
IN
− V
)/L. The duty cycle (or “on” time) for the
OUT
CS51031 is limited to 80%. If output voltage remains higher
than nominal during the entire C
change time, the Q1
OSC
does not turn on, skipping the pulse.
L
R
1
C
O
R
2
R
LOAD
APPLICATIONS INFORMATION
CS51031 DESIGN EXAMPLE
Specifications 12 V to 5.0 V, 3.0 A Buck Controller
• V
= 12 V ±20% (i.e. 14.4 V max, 12 V nom, 9.6 V
IN
min)
• V
• I
= 5.0 V ±2%
OUT
= 0.3 A to 3.0 A
OUT
• Output ripple voltage < 50 mV max
• Efficiency > 80%
• f
= 200 kHz
SW
1) Duty Cycle Estimates
Since the maximum duty cycle D, of the CS51031 is
limited to 80% min, it is necessary to estimate the duty cycle
for the various input conditions over the complete operating
range.
The duty cycle for a buck regulator operating in a
continuous conduction mode is given by:
V
) V
where:
V
SAT
TJ 100°C.
= R
DS(ON)
D +
× I
VIN* V
max and R
OUT
OUT
SAT
F
DS(ON)
is the value at
If VF = 0.60 V and V
= 0.60 V then the above equation
SAT
becomes:
D
MAX
D
MIN
2) Switching Frequency and On and Off Time
Calculations
Given that fSW = 200 kHz and D
T +
T
ON(max)
T
ON(min)
T
OFF(max)
3) Oscillator Capacitor Selection
+ T D
+ T D
+ T
ON(min)
The switching frequency is set by C
5.6
+
+ 0.62
9.0
5.6
+
f
MAX
MIN
+ 0.40
13.8
= 0.80
MAX
1.0
+ 5.0 ms
SW
+ 5.0 ms 0.62 ^ 3.0 ms
+ 5.0 ms0.40 ^ 2.0 ms
+ 5.0 ms * 2.0 ms + 3.0 ms
, whose value is
OSC
given by:
C
OSC
in pF +
F
SW
ǒ
1 )
95 10
F
SW
3 10
)6
30 10
ǒ
*
6
F
SW
2
3
Ǔ
Ǔ
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6
CS51031
R
ǒ
1.25
ǒ
1.25
4) Inductor Selection
The inductor value is chosen for continuous mode
operation down to 0.3 Amps.
The ripple current DI = 2 × I
(
V
+
OUT
L
min
) V
)
T
D
DI
OFF(max)
min = 2 × 0.3 A = 0.6 A.
OUT
5.6 V 3.0 ms
+
0.6 A
+ 28 mH
This is the minimum value of inductor to keep the ripple
current < 0.6 A during normal operation.
A smaller inductor will result in larger ripple current.
Ripple current at a minimum off time is:
DI +
(
V
OUT
) V
F
L
)
MIN
T
OFF(min)
5.6 V 2.0 ms
+
28 mH
+ 0.4 A
The core must not saturate with the maximum expected
current, here given by:
I
+ I
MAX
5) Output Capacitor
) DIń2 + 3.0 A ) 0.4 Ań2 + 3.2 A
OUT
The output capacitor and the inductor form a low pass
filter. The output capacitor should have a low ESL and ESR.
Low impedance aluminum electrolytic, tantalum or organic
semiconductor capacitors are a good choice for an output
capacitor. Low impedance aluminum are less expensive.
Solid tantalum chip capacitors are available from a number
of suppliers and are the best choice for surface mount
applications.
The output capacitor limits the output ripple voltage. The
CS51031 needs a maximum of 20 mV of output ripple for
the feedback comparator to change state. If we assume that
all the inductor ripple current flows through the output
capacitor and that it is an ideal capacitor (i.e. zero ESR), the
minimum capacitance needed to limit the output ripple to
50 mV peak−to−peak is given by:
C +
8.0 fSW DV
DI
+
8.0 (200 103Hz
0.6 A
) (
50 10*3V
+ 7.5mF
)
The minimum ESR needed to limit the output voltage
ripple to 50 mV peak−to−peak is:
ESR +
DV
DI
50 10
+
0.6 A
*3
+ 83 mW
The output capacitor should be chosen so that its ESR is
less than 83 mW.
During the minimum off time, the ripple current is 0.4 A
and the output voltage ripple will be:
DV + ESR DI + 83m W 0.4 + 33 mV
Divider
6) V
FB
V
OUT
+ 1.25 V
R1) R2
ǒ
R2
Ǔ
+ 1.25 V
R1
ǒ
R2
) 1.0
Ǔ
The input bias current to the comparator is 4.0 mA. The
resistor divider current should be considerably higher than
this to ensure that there is sufficient bias current. If we
choose the divider current to be at least 250 times the bias
current this permits a divider current of 1.0 mA and
simplifies the calculations.
5.0 V
1.0 mA
+ R1 ) R2 + 5.0 KW
Let R2 = 1.0 K
Rearranging the divider equation gives:
V
1 + R2
7) Divider Bypass Capacitor C
OUT
* 1.0Ǔ+ 1.0 kW
RR
5.0 V
* 1.0Ǔ+ 3.0 kW
Since the feedback resistors divide the output voltage by
a factor of 4.0, i.e. 5.0 V/1.25 V = 4.0, it follows that the
output ripple is also divided by four. This would require that
the output ripple be at least 60 mV (4.0 × 15 mV) to trip the
feedback comparator. We use a capacitor CRR to act as an
AC short.
The ripple voltage frequency is equal to the switching
frequency so we choose CRR = 1.0 nF.
8) Soft−Start and Fault Timing Capacitor CS
CS performs several important functions. First it provides
a delay time for load transients so that the IC does not enter
a fault mode every time the load changes abruptly. Secondly
it disables the fault circuitry during startup, it also provides
Soft−Start b y clamping the reference voltage during startup,
allowing it to rise slowly, and, finally it controls the hiccup
short circuit protection circuitry. This reduces the duty cycle
to approximately 0.035 during short circuit conditions.
An important consideration in calculating CS is that it’s
voltage does not reach 2.5 V (the voltage at which the fault
detect circuitry is enabled) before VFB reaches 1.15 V
otherwise the power supply will never start.
If the VFB pin reaches 1.15 V, the fault timing comparator
will discharge CS and the supply will not start. For the V
FB
voltage to reach 1.15 V the output voltage must be at least
4 × 1.15 = 4.6 V.
If we choose an arbitrary startup time of 900 ms, the value
of CS is:
CS
900 ms 264 mA
+
min
t
Startup
2.5 V
CS 2.5 V
+
I
Charge
+ 950 nF ^ 0.1 mF
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7
CS51031
The fault time is the sum of the slow discharge time the
fast dischar g e time and the recharge time. It is dominated by
the slow discharge time.
The first parameter is the slow discharge time, it is the time
for the CS capacitor to discharge from 2.4 V to 1.5 V and is
given by:
)
5
where I
t
SlowDischarge(t)
Discharge
is 6.0 mA typical.
t
SlowDischarge(t)
CS (2.4 V* 1.5 V
+
I
Discharge
+ CS 1.5 10
The fast discharge time occurs when a fault is first
detected. The C S c ap aci to r i s d i sc har ge d f r om 2.5 V t o 2 .4 V.
)
where I
t
FastDischarge(t)
FastDischarge
is 66 mA typical.
t
FastDischarge(t)
CS (2.5 V * 2.4 V
+
I
FastDischarge
+ CS 1515
The recharge time is the t ime f or CS to charge from 1.5 V
to 2.5 V.
)
where I
t
Charge(t)
is 264 mA typical.
Charge
t
Charge(t)
CS (2.5 V * 1.5 V
+
I
Charge
+ CS 3787
The fault time is given by:
5
t
+ CS (3787) 1515 ) 1.5 10
Fault
t
+ CS (1.55 10
Fault
5
)
)
For this circuit
t
+ 0.1 10*6 1.55 105+ 15.5 ms
Fault
A larger value of CS will increase the fault time out time
but will also increase the Soft−Start time.
9) Input Capacitor
The input capacitor reduces the peak currents drawn from
the input supply and reduces the noise and ripple voltage on
the VCC and VC pins. This capacitor must also ensure that
the VCC remains above the UVLO voltage in the event of an
output short circuit. A low ESR capacitor of at least 10 0 mF
is good. A ceramic surface mount capacitor should also be
connected between VCC and ground to filter high frequency
noise.
10) MOSFET Selection
The CS51031 drives a P−Channel MOSFET. The V
GATE
pin swings from GND to VC. The type of P−Ch FET used
depends on the operating conditions but for input voltages
below 7.0 V a logic level FET should be used.
A P−Ch FET with a continuous drain current (ID) rating
greater than the maximum output current is required.
The Gate−to−Source voltage VGS and the Drain−to
Source Breakdown Voltage should be chosen based on the
input supply voltage.
The power dissipation due to the conduction losses is
given by:
OUT
2
R
DS(ON)
D
PD+ I
where
R
DS(ON)
is the value at TJ+ 100°C
The power dissipation of the P−Ch FET due to the
switching losses is given by:
(
PD+ 0.5 VIN I
OUT
)
t
f
r
SW
where tr = Rise Time.
11) Diode Selection
The flyback or catch diode should be a Schottky diode
because of i t ’s fast switching ability and low forward voltage
drop. The current rating must be at least equal to the
maximum output current. The breakdown voltage should be
at least 20 V for this 12 V application.
The diode power dissipation is given by:
PD+ I
OUT
V
D
(
1.0 * D
min
)
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8
CS51031
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AG
−Y−
−Z−
−X−
A
58
B
1
S
0.25 (0.010)
4
M
M
Y
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
PACKAGE THERMAL DATA
ParameterSOIC−8Unit
R
q
JC
R
q
JA
Typical45°C/W
Typical165°C/W
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9
ǒ
inches
mm
Ǔ
CS51031
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
CS51031/D
10
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