ON CM1293A-04SO Schematic [ru]

CM1293A-04SO

4-Channel
Low Capacitance
ESD Protection Array

Product Description

CM1293A−04SO has been designed to provide ESD protection for
electronic components or subsystems requiring minimal capacitive
loading. This device is ideal for protecting systems with high data and
clock rates or for circuits requiring low capacitive loading. Each ESD
channel consists of a pair of diodes in series that steer the positive or
negative ESD current pulse to either the positive (V
supply rail. A Zener diode is embedded between V
helps protect the V

rail against ESD strikes. This device protects

CC

) or negative (VN)

P

and V

P

N

which

against ESD pulses up to 8 kV contact discharge) per the
IEC 61000−4−2 Level 4 standard.

This device is particularly well−suited for protecting systems using
high−speed ports such as USB2.0, IEEE1394 (FireWire



, i.LINKt),
Serial ATA, DVI, HDMI, and corresponding ports in removable
storage, digital camcorders, DVD−RW drives and other applications
where extremely low loading capacitance with ESD protection are
required in a small package footprint.

Features

 Four Channels of ESD Protection
 Provides ESD Protection to IEC61000−4−2

 8 kV Contact Discharge

 Low Loading Capacitance of 2.0 pF Max
 Low Clamping Voltage
 Channel I/O to I/O Capacitance 1.5 pF Typical
 Zener Diode Protects Supply Rail and Eliminates the Need for

External By−Pass Capacitors

 Each I/O Pin Can Withstand over 1000 ESD Strikes*
 This Device is Pb−Free and is RoHS Compliant**

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SC−74
SO SUFFIX
CASE 318F

BLOCK DIAGRAM

CH2CH1 CH3 CH4

CM1293A−04SO

MARKING DIAGRAM

XXXMG

G

1

XXX = Specific Device Code
M = Date Code
G = Pb−Free Package

(Note: Microdot may be in either location)

VP

VN

Applications

 DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,

LCD Displays

 Serial ATA Ports in Desktop PCs and Hard Disk Drives
 PCI Express Ports
 General Purpose High−Speed Data Line ESD Protection

**Standard test condition is IEC61000−4−2 level 4 test circuit with each pin

subjected to 8 kV contact discharge for 1000 pulses. Discharges are timed at
1 second intervals and all 1000 strikes are completed in one continuous test run.
The part is then subjected to standard production test to verify that all of the
tested parameters are within spec after the 1000 strikes.

**For additional information on our Pb−Free strategy and soldering details,

please download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2012

January, 2012 − Rev. 0

1 Publication Order Number:

ORDERING INFORMATION

Device Package Shipping

CM1293A−04SO

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

SC−74

(Pb−Free)

Tape & Reel

CM1293A−04SO/D

†

3,000 /

CM1293A−04SO

Table 1. PIN DESCRIPTIONS

Pin Name Type Description

1 CH1 I/O ESD Channel

2 V

N

3 CH2 I/O ESD Channel

4 CH3 I/O ESD Channel

5 V

P

GND Negative Voltage Supply Rail

PWR Positive Voltage Supply Rail

PACKAGE/PINOUT DIAGRAM

Top View

CH1 CH4

V

CH2

635

N

4−Channel SC−74

V

P

CH3

6 CH4 I/O ESD Channel

SPECIFICATIONS

Table 2. ABSOLUTE MAXIMUM RATINGS

Parameter Rating Units

Operating Supply Voltage (VP − VN) 6.0 V

Operating Temperature Range –40 to +85 C

Storage Temperature Range –65 to +150 C

DC Voltage at any Channel Input (VN − 0.5) to (VP + 0.5) V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

Table 3. STANDARD OPERATING CONDITIONS

Parameter Rating Units

Operating Temperature Range –40 to +85 C

Package Power Rating 225 mW

Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)

Symbol

V

I

V

I

LEAK

C

DC

V

ESD

Operating Supply Voltage (VP−VN) 3.3 5.5 V

P

Operating Supply Current (VP−VN) = 3.3 V 8.0

P

Diode Forward Voltage I

F

Channel Leakage Current T

Channel Input Capacitance At 1 MHz, V

IN

Channel I/O to I/O Capacitance 1.5 pF

IO

ESD Protection

Peak Discharge Voltage at any
Channel Input, in System

Contact Discharge per
IEC 61000−4−2 Standard

V

Channel Clamp Voltage

CL

Positive Transients
Negative Transients

R

DYN

Dynamic Resistance

Positive Transients
Negative Transients

1. All parameters specified at T

2. Standard IEC 61000−4−2 with C

3. These measurements performed with no external capacitor on V

Parameter Conditions Min Ty p Max Units

= 8 mA, T

F

= 25C, V

A

T

= 25C (Notes 2 and 3) 8

A

T

= 25C, I

A

(Note 3)

= 25C 0.90 V

A

= 5 V, V

P

= 3.3 V, V

P

= 1A, tP = 8/20 mS

PP

= 0 V 0.1 1.0

N

= 0 V, V

N

= 1.65 V 2.0 pF

IN

+9.9
–1.6

T

= 25C, I

A

(Note 3)

= 1A, tP = 8/20 mS

PP

0.96

0.5

= –40C to +85C unless otherwise noted.

A

Discharge

= 150 pF, R

= 330 W, VP = 3.3 V, VN grounded.

Discharge

.

P

mA

mA

kV

V

W

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CM1293A−04SO

PERFORMANCE INFORMATION

Input Channel Capacitance Performance Curves

Figure 1. Typical Variation of CIN vs. V

IN

(f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN, 255C)

(f = 1 MHz, V

Figure 2. Typical Variation of C

= 30 mV, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN)

IN

vs. Temp

IN

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