CM1293A
2 and 4-Channel
Low Capacitance
ESD Protection Arrays
Product Description
The CM1293A family of diode arrays has been designed to provide
ESD protection for electronic components or subsystems requiring
minimal capacitive loading. These devices are ideal for protecting
systems with high data and clock rates or for circuits requiring low
capacitive loading. Each ESD channel consists of a pair of diodes in
series that steer the positive or negative ESD current pulse to either the
positive (V
between V
) or negative (VN) supply rail. A Zener diode is embedded
P
and V
P
which helps protect the VCC rail against ESD
N
strikes. The CM1293A protects against ESD pulses up to ±8kV
contact discharge) per the IEC 61000−4−2 Level 4 standard.
This device is particularly well−suited for protecting systems using
high−speed ports such as USB2.0, IEEE1394 (FireWire
®
, i.LINKt),
Serial ATA, DVI, HDMI, and corresponding ports in removable
storage, digital camcorders, DVD−RW drives and other applications
where extremely low loading capacitance with ESD protection are
required in a small package footprint.
Features
• Two and Four Channels of ESD Protection
• Provides ESD Protection to IEC61000−4−2
♦ ±8 kV Contact Discharge
• Low Loading Capacitance of 2.0 pF Max
• Low Clamping Voltage
• Channel I/O to I/O Capacitance 1.5 pF Typical
• Zener Diode Protects Supply Rail and Eliminates the Need for
External By−Pass Capacitors
• Each I/O Pin Can Withstand over 1000 ESD Strikes*
• These Devices are Pb−Free and are RoHS Compliant
Applications
• DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,
LCD Displays
• Serial ATA Ports in Desktop PCs and Hard Disk Drives
• PCI Express Ports
• General Purpose High−Speed Data Line ESD Protection
*Standard test condition is IEC61000−4−2 level 4 test circuit with each pin
subjected to ±8 kV contact discharge for 1000 pulses. Discharges are timed at
1 second intervals and all 1000 strikes are completed in one continuous test run.
The part is then subjected to standard production test to verify that all of the
tested parameters are within spec after the 1000 strikes.
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SOT−143
SR SUFFIX
CASE 318A
V
P
CH1
V
N
CM1293A−02SR
CM1293A−02SO
MARKING DIAGRAM
XXX MG
XXX = Specific Device Code
M = Date Code
G = Pb−Free Package
(*Note: Microdot may be in either location)
ORDERING INFORMATION
Device Package Shipping
CM1293A−02SR
CM1293A−02SO
CM1293A−04MR
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
SC−74
SO SUFFIX
CASE 318F
BLOCK DIAGRAM
CH2
G
SOT143−4
(Pb−Free)
SC−74
(Pb−Free)
MSOP−10
(Pb−Free)
MSOP−10
MR SUFFIX
CASE 846AE
CH4 V
CH1 CH2
CM1293A−04MR
XXX MG
G
Tape & Reel
Tape & Reel
Tape & Reel
P
V
N
3,000 /
3,000 /
4,000 /
CH3
†
© Semiconductor Components Industries, LLC, 2012
July, 2012 − Rev. 8
1 Publication Order Number:
CM1293A/D
CM1293A
Table 1. PIN DESCRIPTIONS
2−Channel, 4−Lead SOT143−4 Package (CM1293A−02SR)
Pin Name Type Description
1 V
N
2 CH1 I/O ESD Channel
3 CH2 I/O ESD Channel
4 V
P
2−Channel, SC−74 Package (CM1293A−02SO)
Pin Name Type Description
1 NC − No Connect
2 VN GND Negative Voltage Supply Rail
3 CH1 I/O ESD Channel
4 CH2 I/O ESD Channel
5 NC − No Connect
6 VP PWR Positive Voltage Supply Rail
4−Channel, 10−Lead MSOP−10 Package (CM1293A−04MR)
Pin Name Type Description
1 CH1 I/O ESD Channel
2 NC − No Connect
3 V
P
4 CH2 I/O ESD Channel
5 NC − No Connect
6 CH3 I/O ESD Channel
7 NC − No Connect
8 V
N
9 CH4 I/O ESD Channel
10 NC − No Connect
GND Negative Voltage Supply Rail
PWR Positive Voltage Supply Rail
PWR Positive Voltage Supply Rail
GND Negative Voltage Supply Rail
PACKAGE/PINOUT DIAGRAM
Top View
VN (1)
D636
CH1 (2)
4−Lead SOT143−4
Top View
NC (1) VP (6)
633
VN (2)
CH1 (3)
2−Channel SC−74
Top View
CH1
NC
V
CH2
P
D641
NC
10−Lead MSOP−10
(4)
V
P
CH2 (3)
NC (5)
CH2 (4)
NC
CH4
V
N
NC
CH3
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2
CM1293A
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter Rating Units
Operating Supply Voltage (VP − VN) 6.0 V
Operating Temperature Range –40 to +85 °C
Storage Temperature Range –65 to +150 °C
DC Voltage at any Channel Input (VN − 0.5) to (VP + 0.5) V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter Rating Units
Operating Temperature Range –40 to +85 °C
Package Power Rating
SOT143−4 Package (CM1293A−02SR)
SC−74 Package (CM1293A−02SO)
MSOP−10 Package (CM1293A−04MR)
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
V
I
V
Operating Supply Voltage (VP−VN) 3.3 5.5 V
P
Operating Supply Current (VP−VN) = 3.3 V 8.0
P
Diode Forward Voltage
F
Top Diode
Bottom Diode
I
LEAK
C
DC
V
ESD
Channel Leakage Current T
Channel Input Capacitance At 1 MHz, V
IN
Channel I/O to I/O Capacitance 1.5 pF
IO
ESD Protection − Peak Discharge
Voltage at any Channel Input, in System
Contact Discharge per
IEC 61000−4−2 Standard
Human Body Model, MIL−STD−883,
Method 3015
V
Channel Clamp Voltage
CL
Positive Transients
Negative Transients
R
DYN
Dynamic Resistance
Positive Transients
Negative Transients
1. All parameters specified at T
2. Standard IEC 61000−4−2 with C
3. Human Body Model per MIL−STD−883, Method 3015, C
4. These measurements performed with no external capacitor on V
Parameter Conditions Min Ty p Max Units
I
= 8 mA, T
F
= 25°C, V
A
T
= 25°C (Notes 2 and 4)
A
= 25°C (Notes 3 and 4)
T
A
T
= 25°C, I
A
(Note 4)
T
= 25°C, I
A
(Note 4)
= –40°C to +85°C unless otherwise noted.
A
Discharge
= 150 pF, R
Discharge
Discharge
A
P
P
PP
PP
= 330 W, VP = 3.3 V, VN grounded.
= 100 pF, R
.
P
= 25°C
= 5 V, V
= 3.3 V, V
= 1A, tP = 8/20 mS
= 1A, tP = 8/20 mS
= 0 V ±0.1 ±1.0
N
= 0 V, V
N
Discharge
225
225
400
0.60
0.60
= 1.65 V 2.0 pF
IN
0.80
0.80
±8
±15
+9.9
–1.6
0.96
0.5
= 1.5 kW, VP = 3.3 V, VN grounded.
mW
mA
V
0.95
0.95
mA
kV
V
W
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3
PERFORMANCE INFORMATION
Input Channel Capacitance Performance Curves
CM1293A
Figure 1. Typical Variation of CIN vs. V
IN
(f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN, 255C)
(f = 1 MHz, V
Figure 2. Typical Variation of C
= 30 mV, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN)
IN
vs. Temp
IN
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4
CM1293A
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (nominal conditions unless specified otherwise, 50 Environment)
Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, V
= 3.3 V)
P
Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, V
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5
= 3.3 V)
P
CM1293A
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically a
connector) and the ESD protection device. Refer to Figure 5, which illustrates an example of a positive ESD pulse striking an
input channel. The parasitic series inductance back to the power supply is represented by L
line being protected is:
and L2. The voltage VCL on the
1
V
where I
= Fwd voltage drop of D
CL
is the ESD current pulse, and V
ESD
1
+ V
SUPPLY
SUPPLY
+ L1 x d(I
) / dt+ L2 x d(I
ESD
is the positive supply voltage.
ESD
) / dt
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(I
approximated by DI
increment in V
CL
/Dt, or 30/(1x10−9). So just 10 nH of series inductance (L
ESD
!
Similarly for negative ESD pulses, parasitic series inductance from the V
1
pin to the ground rail will lead to drastically
N
and L
combined) will lead to a 300 V
2
)/dt can be
ESD
increased negative voltage on the line being protected.
The CM1293 has an integrated Zener diode between V
L
on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when
2
V
is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 μF ceramic chip
P
capacitor be connected between V
and the ground plane.
P
and VN. This greatly reduces the effect of supply rail inductance
P
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V
pin of the Protection
P
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
L
2
V
P
PATH OF ESD CURRENT PULSE I
POSITIVE SUPPLY RAIL
ESO
V
CC
0.22 mF
V
N
D
1
D
2
ONE
CHANNEL
L
1
CHANNEL
INPUT
0 A
25 A
LINE BEING
PROTECTED
V
CL
GROUND RAIL
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
CHASSIS GROUND
Figure 5. Application of Positive ESD Pulse between Input Channel and Ground
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6
CM1293A
PACKAGE DIMENSIONS
SOT−143
CASE 318A−06
ISSUE U
D
e
A
E1
D
GAUGE
PLANE
E
L2
L
SEATING
PLANE
DETAIL A
b1
3X
e1
B
TOP VIEW
A
A1
SIDE VIEW
b
0.20 DC
c
C
M
SEATING
PLANE
0.10
A-B
H
C
DETAIL A
END VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIM
UM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO
TRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS,
AND GATE BURRS SHALL NOT EXCEED 0.25 PER SIDE.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION. INTERLEAD FLASH AND PROTRUSION SHALL
NOT EXCEED 0.25 PER SIDE.
5. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H.
6. DATUMS A AND B ARE DETERMINED AT DATUM H.
MILLIMETERS
DIMDMIN MAX
A 0.80 1.12
A1 0.01 0.15
b 0.30 0.51
b1 0.76 0.94
c 0.08 0.20
2.80 3.05
c
E 2.10 2.64
E1 1.20 1.40
e 1.92 BSC
e1 0.20 BSC
L 0.35 0.70
L2 0.25 BSC
RECOMMENDED
SOLDERING FOOTPRINT*
1.92
4X
0.75
2.70
0.20
0.96
DIMENSIONS: MILLIMETERS
3X
0.54
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
0.05 (0.002)
SCALE 2:1
H
E
e
A1
D
1
23
CM1293A
PACKAGE DIMENSIONS
SC−74
CASE 318F−05
ISSUE N
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
456
E
b
A
C
L
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. 318F−01, −02, −03, −04 OBSOLETE. NEW
STANDARD 318F−05.
DIMAMIN NOM MAX MIN
A1 0.01 0.06 0.10 0.001
b 0.25 0.37 0.50 0.010
c 0.10 0.18 0.26 0.004
D 2.90 3.00 3.10 0.114
E 1.30 1.50 1.70 0.051
e 0.85 0.95 1.05 0.034
L
H
E
MILLIMETERS
0.90 1.00 1.10 0.035
0.20 0.40 0.60 0.008
2.50 2.75 3.00 0.099 0.108 0.118
0° 10° 0° 10°
− −
INCHES
NOM MAX
0.039 0.043
0.002 0.004
0.015 0.020
0.007 0.010
0.118 0.122
0.059 0.067
0.037 0.041
0.016 0.024
SOLDERING FOOTPRINT*
2.4
0.094
0.95
ǒ
inches
0.037
0.95
0.037
mm
Ǔ
1.9
0.074
0.7
0.028
1.0
0.039
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
CM1293A
PACKAGE DIMENSIONS
MSOP 10, 3x3
CASE 846AE−01
ISSUE O
SYMBOL MIN NOM MAX
A
A1
A2
b
c
D
E1E
E
E1
0.00
0.75
0.17
0.13
2.90
4.75
2.90
e
L
0.40
0.05
0.85
3.00
4.90
3.00
0.50 BSC
0.60
L1 0.95 REF
L2
θ
0º 8º
0.25 BSC
1.10
0.15
0.95
0.27
0.23
3.10
5.05
3.10
0.80
DETAIL A
TOP VIEW
D
A2
A
A1
eb
c
END VIEW
q
SIDE VIEW
L2
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L
L1
DETAIL A
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i.LINK is a trademark of Sony Corporation.
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CM1293A/D
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