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CM1216-06SM
Datasheet (ON) [ru]
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Datasheet CM1216-06MR, CM1216-06SM, CM1216-08MR Datasheet (ON) [ru]

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CM1216
6 and 8-Channel Low Capacitance ESD Arrays
Product Description
N) supply rail. The CM1216 protects against ESD pulses
±15 kV per the IEC 61000−4−2 standard.
This device is particularly well−suited for protecting systems using high−speed ports such as USB2.0, IEEE1394 (Firewire Serial ATA, DVI, HDMI and corresponding ports in removable storage, digital camcorders, DVD−RW drives and other applications where extremely low loading capacitance with ESD protection are required in a small package footprint.
Features
• Six and Eight Channels of ESD Protection
• Provides ±15 kV ESD Protection on Each Channel per the
IEC 61000−4−2 ESD Requirements
• Channel Loading Capacitance of 1.6 pF Typical
• Channel I/O to GND Capacitance Difference of 0.04 pF Typical
• Mutual Capacitance of 0.13 pF Typical
• Minimal Capacitance Change with Temperature and Voltage
• Each I/O Pin Can Withstand Over 1000 ESD Strikes
• SOIC and MSOP Packages
• These Devices are Pb−Free and are RoHS Compliant
Applications
• IEEE1394 Firewire
®
Ports at 400 Mbps / 800 Mbps
• DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,
LCD Displays
• Serial ATA Ports in Desktop PCs and Hard Disk Drives
• PCI Express Ports
• General Purpose High−Speed Data Line ESD Protection
®
, iLinkt),
P) or
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SOIC−8
SM SUFFIX
CASE 751AC
CH6 V
CH1 CH2 CH3
CH8 V
MARKING DIAGRAM
XXXXX
AYWWG
G
ORDERING INFORMATION
Device Package Shipping
CM1216−06SM SOIC
†For information on tape and reel specifications,
including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
MSOP−8
MR SUFFIX
CASE 846AD
BLOCK DIAGRAM
CH5 CH4
P
V
N
CM1216−06SM CM1216−06MR
CH7 CH6 CH5
CH2CH1 CH4CH3
XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package
P
CM1216−08MR
(Pb−Free)
MSOP
(Pb−Free)
MSOP
(Pb−Free)
MSOP−10
MR SUFFIX
CASE 846AE
2500/Tape & Reel
4000/Tape & ReelCM1216−06MR
4000/Tape & ReelCM1216−08MR
V
†
N
© Semiconductor Components Industries, LLC, 2011
February, 2011 − Rev. 3
1 Publication Order Number:
CM1216/D
CM1216
PACKAGE / PINOUT DIAGRAMS
Top View
CH1 CH2
V
CH3
1
E166
2 3
N
4
CH6
8 7
V
P
CH5
6
CH4
5
CH1 CH2
V
CH3
8−Pin SOIC−8
Table 1. PIN DESCRIPTIONS
Pin Name
CH1 1 1 1 I/O ESD Channel
CH2 2 2 2 I/O ESD Channel
CH3 4 4 3 I/O ESD Channel
CH4 5 5 4 I/O ESD Channel
V
N
CH5 6 6 6 I/O ESD Channel
CH6 8 8 7 I/O ESD Channel
V
P
CH7 − − 9 I/O ESD Channel
CH8 − − 10 I/O ESD Channel
MSOP−8 SOIC−8 MSOP−10
Pin No. Pin No. Pin No.
3 3 5 GND Negative voltage supply rail
7 7 8 PWR Positive voltage supply rail
Top View
1 2 3
N
4
8−Pin MSOP−8
E166
CH1
CH6
8 7
V
P
CH5
6
CH4
5
CH2 CH3 CH4
V
N
Type Description
Top View
1
10
E168
2
9
3
8
4
7
10−Pin MSOP−10
CH8 CH7 V
P
CH6 CH556
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter Rating Units
Operating Supply Voltage (VP−VN) 6 V
Diode Forward DC Current 20
DC Voltage at any Channel Input (VN−0.5) to (VP+0.5) V
Operating Temperature Range
Ambient Junction
−40 to +85
−40 to +125
Storage Temperature Range −40 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter Rating Units
Temperature Range (Ambient) −40 to +85 °C
Package Power Rating
MSOP8 Package (CM1216−06MR) SOIC8 Package (CM1216−06SM) MSOP10 Package (CM1216−08MR)
400 600 400
mA
°C
mW
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2
CM1216
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
V
I
V
I
LEAK
C
DC
C
MUTUAL
V
ESD
V
CL
R
DYN
1. All parameters specified at TA = −40°C to +85°C unless otherwise noted.
2. Standard IEC 61000−4−2 with C
3. From I/O pins to V
Parameter
Operating Supply Voltage
P
(V
)
P−VN
Operating Supply Current (VP−VN) = 3.3 V 8
P
Diode Forward Voltage
F
Top Diode
IF = 20 mA; T
Bottom Diode
Channel Leakage Current T
Channel Input Capacitance At 1 MHz, V
IN
Channel Input Capacitance Matching 0.04 pF
IN
= 25°C; V
A
(Note 2)
Mutual Capacitance (VP−VN) = 3.3 V 0.13 pF
ESD Protection
Peak Discharge Voltage at any
T
= 25°C
A
(Notes 2 and 3) channel input, in system, contact discharge per IEC 61000−4−2 standard
Channel Clamp Voltage
Positive Transients
I
PP
= 1 A, t
Negative Transients
Dynamic Resistance
Positive transients
I
PP
= 1 A, t
Negative transients
or V
only. VP bypassed to V
P
N
Discharge
= 150 pF, R
N
with low ESR 0.2 mF ceramic capacitor.
= 330 W, VP = 3.3 V, VN grounded.
Discharge
A
P
= 3.3 V, V
P
= 8/20 mS; T
P
= 8/20 mS; T
P
Conditions
= 25°C
= 5 V, V
Min Typ Max Units
3.3 5.5 V
0.6
0.8
0.6
0.8
= 0 V ±0.1 ±1.0
N
= 0 V, V
N
= 1.65 V
IN
1.6 2.0 pF
±15
= 25°C
A
+9.0
−1.5
= 25°C
A
0.6
0.4
mA
V
0.95
0.95
mA
kV
V
W
PERFORMANCE CHARACTERISTICS
Figure 1. Typical Variation of CIN vs. V
(f = 1 MHz, VP= 3.3 V, VN = 0 V, 0.1 mF Chip Capacitor between VP and VN, TA = 255C)
IN
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3
CM1216
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground, which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power supply is represented by L
and L2. The voltage VCL on the line being protected is:
1
V
where I
= Fwd voltage drop of D
CL
is the ESD current pulse, and V
ESD
1
+ V
SUPPLY
SUPPLY
+ L1 x d(I
) / dt + L2 x d(I
ESD
is the positive supply voltage.
ESD
) / dt
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(I approximated by DI increment in V
CL
/Dt, or 30/(1x10−9). So just 10 nH of series inductance (L
ESD
!
Similarly for negative ESD pulses, parasitic series inductance from the V
1
pin to the ground rail will lead to drastically
N
and L
combined) will lead to a 300 V
2
)/dt can be
ESD
increased negative voltage on the line being protected.
The CM1213 has an integrated Zener diode between V L
on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when
2
V
is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 μF ceramic chip
P
capacitor be connected between V
and the ground plane.
P
and VN. This greatly reduces the effect of supply rail inductance
P
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V
pin of the Protection
P
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance.
Additional Information
See also ON Semiconductor Application Note, “Design Considerations for ESD Protection”, in the Applications section.
L
1
POSITIVE SUPPLY
PATH OF ESD CURRENT PULSE (IESD)
D
1
C
ONE
1
CHANNEL
D
2
CHANNEL
INPUT
LINE BEING PROTECTED
GROUND RAIL
SYSTEM OR CIRCUITRY
BEING PROTECTED
CHASSIS GROUND
Figure 2. Application of Positive ESD Pulse between Input Channel and Ground
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CM1216
PACKAGE DIMENSIONS
SOIC−8 EP
CASE 751AC−01
ISSUE B
2 X
LOCATION
8 X
SEATING
PLANE
C0.10
PIN ONE
C
D
A
E1
D
14
e
B
TOP VIEW
C0.10
C0.10
SIDE VIEW
SOLDERING FOOTPRINT*
2 X
A-B
C0.10
D
58
EXPOSED
PAD
F
58
E
8 X b
C
2 X
C0.20
BOTTOM VIEW
A-B0.25 D
14
DETAIL A
G
AA
END VIEW
c
GAUGE PLANE
H
b1
A
A2
L
A1
0.25
(L1)
DETAIL A
q
c1
SECTION A−A
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS (ANGLES IN DEGREES).
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE
0.08 MM TOTAL IN EXCESS OF THE “b” DIMENSION AT MAXIMUM MATERIAL CONDITION.
4. DATUMS A AND B TO BE DETERMINED AT DATUM PLANE H.
MILLIMETERS
h
(b)
DIM MIN MAX
A 1.35 1.75 A1 0.00 0.10 A2 1.35 1.65
b 0.31 0.51 b1 0.28 0.48
c 0.17 0.25 c1 0.17 0.23
D 4.90 BSC
E 6.00 BSC E1 3.90 BSC
e 1.27 BSC
L 0.40 1.27 L1 1.04 REF
F 2.24 3.20
G 1.55 2.51
h 0.25 0.50
q 0 8
__
2.72
0.107
1.52
0.060 Exposed
Pad
7.0
0.275
0.024
2.03
0.08
0.6
4.0
0.155
1.270
0.050
SCALE 6:1
ǒ
inches
mm
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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CM1216
PACKAGE DIMENSIONS
MSOP 8, 3x3
CASE 846AD−01
ISSUE O
SYMBOL
A
A1
A2
b
c
E1E
D
E
E1
e
L
L1 0.95 REF
L2
θ
TOP VIEW
D
A2
A
MIN NOM MAX
1.10
0.05
0.75
0.22
0.13
2.90
4.80
2.90
0.40
0.10
0.85
3.00
4.90
3.00
0.65 BSC
0.60
0.25 BSC
0.15
0.95
0.38
0.23
3.10
5.00
3.10
0.80
0º 6º
DETAIL A
A1 e b
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187.
c
q
L2
L
L1
DETAIL A
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CM1216
PACKAGE DIMENSIONS
MSOP 10, 3x3
CASE 846AE−01
ISSUE O
SYMBOL MIN NOM MAX
A
A1
A2
b
c
E1E
D
E
E1
0.00
0.75
0.17
0.13
2.90
4.75
2.90
e
L
0.40
0.05
0.85
3.00
4.90
3.00
0.50 BSC
0.60
L1 0.95 REF
L2
θ
0º 8º
0.25 BSC
1.10
0.15
0.95
0.27
0.23
3.10
5.05
3.10
0.80
DETAIL A
TOP VIEW
D
A2
A
c
END VIEW
A1 e b
q
SIDE VIEW
L2
Notes:
(1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187.
L
L1
DETAIL A
FireWire is a registered trademark of Apple Computer. Inc. iLink is a trademark of S. J. Electro Systems, Inc.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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CM1216/D
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