ON CM1213A-01SO, CM1213A-02SO, CM1213A-02SR, CM1213A-04MR, CM1213A-04S7 Schematic [ru]

CM1213A

1, 2 and 4-Channel
Low Capacitance
ESD Protection Arrays

Product Description

The CM1213A family of diode arrays has been designed to provide
ESD protection for electronic components or subsystems requiring
minimal capacitive loading. These devices are ideal for protecting
systems with high data and clock rates or for circuits requiring low
capacitive loading. Each ESD channel consists of a pair of diodes in
series which steer the positive or negative ESD current pulse to either
the positive (V
embedded between V
protects the V

) or negative (VN) supply rail. A Zener diode is

P

and VN, offering two advantages. First, it

P

rail against ESD strikes, and second, it eliminates the

CC

SOT23−3

SO SUFFIX

CASE 318

need for a bypass capacitor that would otherwise be needed for
absorbing positive ESD strikes to ground. The CM1213A will protect
against ESD pulses up to 8 kV per the IEC 61000−4−2 standard.

These devices are particularly well−suited for protecting systems
using high−speed ports such as USB 2.0, IEEE1394 (Firewire



,
iLinkt), Serial ATA, DVI, HDMI and corresponding ports in
removable storage, digital camcorders, DVD−RW drives and other
applications where extremely low loading capacitance with ESD
protection are required in a small package footprint.

Features

 One, Two, and Four Channels of ESD Protection

Note: For 6 and 8−channel Devices, See the CM1213 Datasheet

1

 Provides ESD Protection to IEC61000−4−2 Level 4

 8 kV Contact Discharge

 Low Channel Input Capacitance of 0.85 pF Typical
 Minimal Capacitance Change with Temperature and Voltage

(Note: Microdot may be in either location)

 Channel Input Capacitance Matching of 0.02 pF Typical is Ideal for

Differential Dignals

 Zener Diode Protects Supply Rail and Eliminates the Need for

External By−pass Capacitors

 Each I/O Pin Can Withstand Over 1000 ESD Strikes*

Device Package Shipping

CM1213A−01SO SOT23−3

CM1213A−02SR

 These Devices are Pb−Free and are RoHS Compliant**

Applications

 USB2.0 Ports at 480 Mbps in Desktop PCs, Notebooks and Peripherals
 IEEE1394 Firewire



Ports at 400 Mbps/800 Mbps

 DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,

LCD Displays

 Serial ATA Ports in Desktop PCs and Hard Disk Drives
 PCI Express Ports
 General Purpose High−Speed Data Line ESD Protection

**Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to 8 kV contact discharge for 1000 pulses. Discharges

are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production
test to verify that all of the tested parameters are within spec after the 1000 strikes.

**For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting

Techniques Reference Manual, SOLDERRM/D.

CM1213A−02SO

CM1213A−04S7

CM1213A−04MR

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

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SOT143

SR SUFFIX

CASE 527AF

SC70−6

S7 SUFFIX

CASE 419AD

MARKING DIAGRAM

XXXMG

G

XXX = Specific Device Code
M = Date Code
G = Pb−Free Package

ORDERING INFORMATION

(Pb−Free)

SOT143−4

(Pb−Free)

SC−74

(Pb−Free)

SC70−6

(Pb−Free)
MSOP−10

(Pb−Free)

MSOP−10

MR SUFFIX

CASE 846AE

XXXMG

1

Tape & Reel

Tape & Reel

Tape & Reel

Tape & Reel

Tape & Reel

SC−74
SO SUFFIX
CASE 318F

G

†

3,000 /

3,000 /

3,000 /

3,000 /

4,000 /

 Semiconductor Components Industries, LLC, 2012

January, 2012 − Rev. 8

1 Publication Order Number:

CM1213A/D

CM1213A

BLOCK DIAGRAM

V

P

CH1

V

N

CM1213A−01SO

V

P

CH1

V

N

CM1213A−02SR
CM1213A−02SO

CH2

CH4 V

CH1 CH2

CH3

P

V

N

CM1213A−04MR

CM1213A−04S7

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2

CM1213A

Table 1. PIN DESCRIPTIONS

1−Channel, 3−Lead SOT23−3 Package (CM1213A−01SO)

Pin Name Type Description

1 CH1 I/O ESD Channel

2 V

3 V

P

N

2−Channel, 4−Lead SOT143−4 Package (CM1213A−02SR)

Pin Name Type Description

1 V

N

2 CH1 I/O ESD Channel

3 CH2 I/O ESD Channel

4 V

P

2−Channel, SC−74 Package (CM1213A−02SO)

Pin Name Type Description

1 NC − No Connect

2 VN GND Negative Voltage Supply Rail

3 CH1 I/O ESD Channel

4 CH2 I/O ESD Channel

5 NC − No Connect

6 VP PWR Positive Voltage Supply Rail

4−Channel, 6−Lead SC70−6 (CM1213A−04S7)

Pin Name Type Description

1 CH1 I/O ESD Channel

2 V

N

3 CH2 I/O ESD Channel

4 CH3 I/O ESD Channel

5 V

P

6 CH4 I/O ESD Channel

4−Channel, 10−Lead MSOP−10 Package (CM1213A04MR)

Pin Name Type Description

1 CH1 I/O ESD Channel

2 NC − No Connect

3 V

P

4 CH2 I/O ESD Channel

5 NC − No Connect

6 CH3 I/O ESD Channel

7 NC − No Connect

8 V

N

9 CH4 I/O ESD Channel

10 NC − No Connect

PWR Positive Voltage Supply Rail

GND Negative Voltage Supply Rail

GND Negative Voltage Supply Rail

PWR Positive Voltage Supply Rail

GND Negative Voltage Supply Rail

PWR Positive Voltage Supply Rail

PWR Positive Voltage Supply Rail

GND Negative Voltage Supply Rail

PACKAGE/PINOUT DIAGRAMS

Top View

CH1 (1)

VP (2)

VN (1)

CH1 (2)

NC (1) VP (6)

VN (2)

CH1 (3)

CH1 1

CH2

CH1

NC

CH2

NC

1

231

3

2

3−Lead SOT23−3

Top View

1

4

D232

23

4−Lead SOT143−4

Top View

1

6

2

5

34

6−Lead SC−74

Top View

6 CH4

D38233

V

2

N

5

34

6−Lead SC70−6

Top View

1

10

D238

2

9

3

V

P

8

4

7

10−Lead MSOP−10

(3)

V

N

(4)

V

P

CH2 (3)

NC (5)

CH2 (4)

V

P

CH3

NC
CH4
V

N

NC
CH356

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3

CM1213A

SPECIFICATIONS

Table 2. ABSOLUTE MAXIMUM RATINGS

Parameter Rating Units

Operating Supply Voltage (VP − VN) 6.0 V

Operating Temperature Range –40 to +85 C

Storage Temperature Range –65 to +150 C

DC Voltage at any channel input (VN − 0.5) to (VP + 0.5) V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

Table 3. STANDARD OPERATING CONDITIONS

Parameter Rating Units

Operating Temperature Range –40 to +85 C

Package Power Rating

SOT23−3, SOT143−4, SC−74, and SC70−6 Packages
MSOP−10 Package

Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note1)

Symbol

V

I

V

Operating Supply Voltage (VP−VN) 3.3 5.5 V

P

Operating Supply Current (VP−VN) = 3.3 V 8.0

P

Diode Forward Voltage

F

Top Diode
Bottom Diode

I

LEAK

C

DC

V

ESD

Channel Leakage Current T

Channel Input Capacitance At 1 MHz, V

IN

Channel Input Capacitance Matching At 1 MHz, V

IN

ESD Protection − Peak Discharge
Voltage at any channel input, in system

Contact discharge per

IEC 61000−4−2 standard T

V

Channel Clamp Voltage

CL

Positive Transients
Negative Transients

R

DYN

Dynamic Resistance

Positive Transients
Negative Transients

1. All parameters specified at T

2. Standard IEC 61000−4−2 with C

3. These measurements performed with no external capacitor on V

Parameter Conditions Min Ty p Max Units

I

= 8 mA; T

F

= 25C; V

A

(Note 2)

(Note 2)

= 25C (Notes 2 and 3) 8

A

T

= 25C, I

A

(Note 2)

I

PP

Any I/O pin to Ground

A

P

P

PP

= 1A, tP = 8/20 mS

(Note 2)

= –40C to +85C unless otherwise noted.

A

Discharge

= 150 pF, R

= 330 W, VP = 3.3 V, VN grounded.

Discharge

(V

P

= 25C

= 5 V, V

P

= 3.3 V, V

= 3.3 V, V

= 1A, tP = 8/20 mS

floating).

P

= 0 V 0.1 1.0

N

= 0 V, V

N

= 0 V, V

N

= 1.65 V

IN

= 1.65 V

IN

225
400

0.60

0.60

0.80

0.80

0.85 1.2 pF

0.02 pF

+10
–1.7

0.9

0.5

mW

mA

V

0.95

0.95

mA

kV

V

W

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4

PERFORMANCE INFORMATION

Input Channel Capacitance Performance Curves

CM1213A

Figure 1. Typical Variation of CIN vs. V

IN

(f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN, 255C)

(f = 1 MHz, V

Figure 2. Typical Variation of C

= 30 mV, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN)

IN

vs. Temp

IN

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5

CM1213A

PERFORMANCE INFORMATION (Cont’d)

Typical Filter Performance (nominal conditions unless specified otherwise, 50 Ohm Environment)

Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, VP=3.3 V)

Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, VP=3.3 V)

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6

CM1213A

APPLICATION INFORMATION

Design Considerations

In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically
a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground,
which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power
supply is represented by L

and L2. The voltage VCL on the line being protected is:

1

V

= Fwd Voltage Drop of D

CL

where I

is the ESD current pulse, and V

ESD

1

+ V

SUPPLY

SUPPLY

+ L1 x d(I

) / dt + L2 x d(I

ESD

is the positive supply voltage.

ESD

) / dt

An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(I
approximated by DI
increment in V

CL

/Dt, or 30/(1x10−9). So just 10 nH of series inductance (L

ESD

!

Similarly for negative ESD pulses, parasitic series inductance from the V

1

pin to the ground rail will lead to drastically

N

and L

combined) will lead to a 300 V

2

)/dt can be

ESD

increased negative voltage on the line being protected.

The CM1213A has an integrated Zener diode between V
L

on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when

2

is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 mF ceramic chip

V

P

capacitor be connected between V

and the ground plane.

P

and VN. This greatly reduces the effect of supply rail inductance

P

As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V

pin of the Protection

P

Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.

Additional Information

See also ON Semiconductor Application Note “Design Considerations for ESD Protection”, in the Applications section.

L

2

V

P

PATH OF ESD CURRENT PULSE I

POSITIVE SUPPLY RAIL

ESO

V

CC

0.22 mF

V

N

D

1

D

2

ONE
CHANNEL
OF
CM1213

L

1

CHANNEL

INPUT

25 A

0 A

LINE BEING
PROTECTED

V

GROUND RAIL

CL

SYSTEM OR
CIRCUITRY

BEING
PROTECTED

CHASSIS GROUND

Figure 5. Application of Positive ESD Pulse between Input Channel and Ground

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7

CM1213A

PACKAGE DIMENSIONS

SOT−23 (TO−236)

CASE 318−08

ISSUE AP

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

D

H

SEE VIEW C

E

c

0.25

3

E

12

b

e



A

L

A1

L1

VIEW C

2. CONTROLLING DIMENSION: INCH.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.

DIMAMIN NOM MAX MIN

A1 0.01 0.06 0.10 0.001

b 0.37 0.44 0.50 0.015
c 0.09 0.13 0.18 0.003
D 2.80 2.90 3.04 0.110
E 1.20 1.30 1.40 0.047
e 1.78 1.90 2.04 0.070
L 0.10 0.20 0.30 0.004

L1

H

MILLIMETERS

0.89 1.00 1.11 0.035

0.35 0.54 0.69 0.014 0.021 0.029

2.10 2.40 2.64 0.083 0.094 0.104

E

0 −−− 10 0 −−− 10

INCHES

NOM MAX

0.040 0.044

0.002 0.004

0.018 0.020

0.005 0.007

0.114 0.120

0.051 0.055

0.075 0.081

0.008 0.012

SOLDERING FOOTPRINT

0.95

0.037

0.9

0.035

0.8

0.031

0.95

0.037

SCALE 10:1

2.0

0.079

ǒ

inches

mm

Ǔ

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8

CM1213A

PACKAGE DIMENSIONS

SOT−143, 4 Lead

CASE 527AF−01

ISSUE A

D

e

43

E1 E

12

e1

TOP VIEW

b

A2

A

SYMBOL

A

A1

A2

b

b2

c

D

E

E1 1.20 1.401.30

e

e1 0.20 BSC

L

L1

L2 0.25

θ

q

MIN NOM MAX

0.80

0.05

0.75

0.30

0.76

0.08

2.80

2.10

0.40

0° 8°

0.90

2.90

1.92 BSC

0.50

0.54 REF

1.22

0.15

1.07

0.50

0.89

0.20

3.04

2.64

0.60

c

L2

b2

A1

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC TO-253.

L

L1

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9

CM1213A

PACKAGE DIMENSIONS

SC−88 (SC−70 6 Lead), 1.25x2

CASE 419AD−01

ISSUE A

D

ee

TOP VIEW

q1

E1

A2

SYMBOL MIN NOM MAX

A

A1

A2 0.80 1.00

b

c

E

D

E

E1

e

L

L1

L2

θ

θ1

A

q

0.80

0.00

0.15

0.10

1.80

1.80

1.15

0.26

2.00

2.10

1.25

0.65 BSC

0.36

0.42 REF

0.15 BSC

0º 8º

4º 10º

1.10

0.10

0.30

0.18

2.20

2.40

1.35

0.46

q1

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-203.

b

A1

L
L1

L2

c

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10

0.05 (0.002)

SCALE 2:1

H

E

e

A1

D

1

23

CM1213A

PACKAGE DIMENSIONS

SC−74

CASE 318F−05

ISSUE M

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. MAXIMUM LEAD THICKNESS INCLUDES

LEAD FINISH THICKNESS. MINIMUM LEAD

456

E

b



A

C

L

THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.

4. 318F−01, −02, −03, −04 OBSOLETE. NEW

STANDARD 318F−05.

DIMAMIN NOM MAX MIN

A1 0.01 0.06 0.10 0.001

b 0.25 0.37 0.50 0.010
c 0.10 0.18 0.26 0.004
D 2.90 3.00 3.10 0.114
E 1.30 1.50 1.70 0.051
e 0.85 0.95 1.05 0.034
L

H

E



MILLIMETERS

0.90 1.00 1.10 0.035

0.20 0.40 0.60 0.008

2.50 2.75 3.00 0.099 0.108 0.118
0 10 0 10

− −

INCHES

NOM MAX

0.039 0.043

0.002 0.004

0.015 0.020

0.007 0.010

0.118 0.122

0.059 0.067

0.037 0.041

0.016 0.024

SOLDERING FOOTPRINT*

2.4

0.094

0.95

1.9

0.074

0.7

0.028

1.0

0.039

SCALE 10:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

0.037

0.037

ǒ

inches

0.95

mm

Ǔ

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11

CM1213A

PACKAGE DIMENSIONS

MSOP 10, 3x3

CASE 846AE−01

ISSUE O

SYMBOL MIN NOM MAX

A

A1

A2

b

c

D

E1E

E

E1

e

L

0.00

0.75

0.17

0.13

2.90

4.75

2.90

0.40

0.05

0.85

3.00

4.90

3.00

0.50 BSC

0.60

L1 0.95 REF

L2

θ

0º 8º

0.25 BSC

1.10

0.15

0.95

0.27

0.23

3.10

5.05

3.10

0.80

DETAIL A

TOP VIEW

D

A2

A

A1

eb

c

END VIEW

q

SIDE VIEW

L2

Notes:

(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.

L

L1

DETAIL A

FireWire is a registered trademark of Apple Computer, Inc.
iLink is a trademark of S. J. Electro Systems, Inc.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Email: [e-mail]

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Phone: [phone]

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Phone: 81−3−5817−1050

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Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local
Sales Representative

CM1213A/D