CM1213
6 and 8-Channel
Low Capacitance ESD
Protection Arrays
Product Description
The CM1213 family of diode arrays has been designed to provide
ESD protection for electronic components or sub−systems requiring
minimal capacitive loading. These devices are ideal for protecting
systems with high data and clock rates or for circuits requiring low
capacitive loading. Each ESD channel consists of a pair of diodes in
series which steer the positive or negative ESD current pulse to either
the positive (V
embedded between V
protects the V
need for a bypass capacitor that would otherwise be needed for
absorbing positive ESD strikes to ground. The CM1213 will protect
against ESD pulses up to ±8 kV per the IEC 61000−4−2 standard.
These devices are particularly well−suited for protecting systems
using high−speed ports such as USB2.0, IEEE1394 (Firewire
iLinkt), Serial ATA, DVI, HDMI and corresponding ports in
removable storage, digital camcorders, DVD−RW drives and other
applications where extremely low loading capacitance with ESD
protection are required in a small package footprint.
Features
• 6 or 8 Channels of ESD Protection
Note: For 1, 2, and 4 Channel Devices, See the CM1213A Datasheet
• Provides ESD Protection to IEC61000−4−2 Level 4
• ±8 kV Contact Discharge
• Low Channel Input Capacitance of 1.0 pF Typical
• Minimal Capacitance Change with Temperature and Voltage
• Channel Input Capacitance Matching of 0.02 pF Typical is Ideal for
Differential Signals
• Mutual Capacitance between Signal Pin and Adjacent Signal Pin
−0.11 pF Typical
• Zener Diode Protects Supply Rail and Eliminates the Need for
External By−pass Capacitors
• Each I/O Pin Can Withstand Over 1000 ESD Strikes*
• Available in SOIC and MSOP
• These Devices are Pb−Free and are RoHS Compliant
Applications
• USB2.0 Ports at 480 Mbps in Desktop PCs, Notebooks
and Peripherals
• IEEE1394 Firewire
• DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,
LCD Displays
• Serial ATA Ports in Desktop PCs and Hard Disk Drives
• PCI Express Ports
• General Purpose High−speed Data Line ESD Protection
• Handheld PCs/PDAs
) or negative (VN) supply rail. A Zener diode is
P
CC
and VN, offering two advantages. First, it
P
rail against ESD strikes, and second, it eliminates the
®
Ports at 400 Mbps / 800 Mbps
®
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SOIC−8
SM SUFFIX
CASE 751AC
CH6 V
MSOP−8
MR SUFFIX
CASE 846AD
BLOCK DIAGRAMS
CH5 CH4
P
,
CH1 CH2 CH3
CH8 V
CH2CH1 CH4CH3
ORDERING INFORMATION
Device Package Shipping
CM1213−06SM SOIC−8
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
V
N
CM1213−06SM
CM1213−06MR
CH7 CH6 CH5
P
V
N
CM1213−08MR
(Pb−Free)
MSOP−8
(Pb−Free)
MSOP−10
(Pb−Free)
MSOP−10
MR SUFFIX
CASE 846AE
†
2500/Tape & Reel
4000/Tape & ReelCM1213−06MR
4000/Tape & ReelCM1213−08MR
*Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to ±8 kV contact discharge for 1000 pulses. Discharges
are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production
test to verify that all of the tested parameters are within spec after the 1000 strikes.
© Semiconductor Components Industries, LLC, 2013
June, 2013 − Rev. 5
1 Publication Order Number:
CM1213/D
CM1213
Table 1. PIN DESCRIPTIONS
6−Channel, 8−Lead MSOP−8/SOIC−8 Packages
Pin Name Type Description
1 CH1 I/O ESD Channel
2 CH2 I/O ESD Channel
3 V
N
4 CH3 I/O ESD Channel
5 CH4 I/O ESD Channel
6 CH5 I/O ESD Channel
7 V
P
8 CH6 I/O ESD Channel
8−Channel, 10−Lead MSOP−10 Package
Pin Name Type Description
1 CH1 I/O ESD Channel
2 CH2 I/O ESD Channel
3 CH3 I/O ESD Channel
4 CH4 I/O ESD Channel
5 V
N
6 CH5 I/O ESD Channel
7 CH6 I/O ESD Channel
8 V
P
9 CH7 I/O ESD Channel
10 CH8 I/O ESD Channel
GND Negative voltage supply rail
PWR Positive voltage supply rail
GND Negative voltage supply rail
PWR Positive voltage supply rail
PACKAGE / PINOUT DIAGRAMS
Top View
1
CH1
CH2
V
N
CH3
8−Lead SOIC−8
CH1
CH2
V
N
CH3
8−Lead MSOP−8
CH1
CH2
CH3
CH4
V
N
10−Lead MSOP−10
8
D136
2
7
3
6
4
5
Top View
1
8
D137
2
7
3
6
4
5
Top View
1
10
D138
2
9
3
8
4
7
56
CH6
V
P
CH5
CH4
CH6
V
P
CH5
CH4
CH8
CH7
V
P
CH6
CH5
GENERIC MARKING DIAGRAMS
CM1213−06MR CM1213−08MRCM1213−06SM
D136
YYWW
XXXX
D137
XXXXX
YYWW
XXXXX = Lot Number
YY = Year
WW = Work Week
D138
XXXXX
YYWW
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2
CM1213
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter Rating Units
Operating Supply Voltage (VP − VN) 6.0 V
Operating Temperature Range −40 to +85 °C
Storage Temperature Range −65 to +150 °C
DC Voltage at any channel input (VN − 0.5) to (VP + 0.5) V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter Rating Units
Operating Temperature Range −40 to +85 °C
Package Power Rating
MSOP−8 Package (CM1213−06MR)
MSOP−10 Package (CM1213−08MR)
SOIC−8 Package (CM1213−06SM)
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
V
V
Operating Supply Voltage (VP−VN) 3.3 5.5 V
P
I
Operating Supply Current (VP−VN) = 3.3 V 8.0
P
Diode Forward Voltage
F
Top Diode
Bottom Diode
I
LEAK
C
DC
C
MUTUAL
V
ESD
Channel Leakage Current T
Channel Input Capacitance At 1 MHz, V
IN
Channel Input Capacitance Matching At 1 MHz, V
IN
Mutual Capacitance between signal pin
and adjacent signal pin
ESD Protection
Peak Discharge Voltage at any
channel input, in system
Contact discharge per
IEC 61000−4−2 standard
V
Channel Clamp Voltage
CL
Positive Transients
Negative Transients
R
DYN
Dynamic Resistance
Positive Transients
Negative Transients
1. All parameters specified at T
2. Human Body Model per MIL−STD−883, Method 3015, C
3. Standard IEC 61000−4−2 with C
4. These measurements performed with no external capacitor on V
Parameter Conditions Min Typ Max Units
I
= 8 mA; T
F
= 25°C; V
A
At 1 MHz, V
T
= 25°C (Notes 3 and 4) ±8
A
T
= 25°C, I
A
(Note 4)
I
= 1 A, tP = 8/20 mS
PP
Any I/O pin to Ground (Note 4)
= −40°C to +85°C unless otherwise noted.
A
Discharge
= 150 pF, R
Discharge
Discharge
= 25°C
A
= 5 V, V
P
= 3.3 V, V
P
= 3.3 V, V
P
= 3.3 V, V
P
= 1 A, tP = 8/20 mS
PP
= 100 pF, R
= 330 W, VP = 3.3 V, VN grounded.
(V
P
floating).
P
400
400
600
0.60
0.60
= 0 V ±0.1 ±1.0
N
= 0 V, V
N
= 0 V, V
N
= 0 V, V
N
= 1.65 V 1.0 1.5 pF
IN
= 1.65 V 0.02 pF
IN
= 1.65 V 0.11 pF
IN
0.80
0.80
+8.8
−1.4
0.7
0.4
= 1.5 KW, VP = 3.3 V, VN grounded.
Discharge
mW
mA
V
0.95
0.95
mA
kV
V
W
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3
PERFORMANCE INFORMATION
Input Channel Capacitance Performance Curves
CM1213
Figure 1. Typical Variation of CIN vs. V
IN
(f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 mF Chip Capacitor between VP and VN, 255C)
(f = 1 MHz, V
Figure 2. Typical Variation of C
= 30 mV, VP = 3.3 V, VN = 0 V, 0.1 mF Chip Capacitor between VP and VN)
IN
vs. Temp
IN
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4
CM1213
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (Nominal Conditions unless Specified Otherwise, 50 Ohm Environment)
Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, VP=3.3 V)
Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, VP=3.3 V)
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5
CM1213
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically
a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground,
which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to power
supply is represented by L
and L2. The voltage VCL on the line being protected is:
1
V
where I
= Fwd voltage drop of D
CL
is the ESD current pulse, and V
ESD
1
+ V
SUPPLY
SUPPLY
+ L1 x d(I
) / dt + L2 x d(I
ESD
is the positive supply voltage.
ESD
) / dt
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(I
approximated by DI
increment in V
CL
/Dt, or 30/(1x10−9). So just 10 nH of series inductance (L
ESD
!
Similarly for negative ESD pulses, parasitic series inductance from the V
1
pin to the ground rail will lead to drastically
N
and L
combined) will lead to a 300 V
2
)/dt can be
ESD
increased negative voltage on the line being protected.
The CM1213 has an integrated Zener diode between V
L
on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when
2
is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 mF ceramic chip
V
P
capacitor be connected between V
and the ground plane.
P
and VN. This greatly reduces the effect of supply rail inductance
P
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V
pin of the Protection
P
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also ON Semiconductor Application Note, “Design Considerations for ESD Protection”, in the Applications section.
L
2
V
P
PATH OF ESD CURRENT PULSE I
POSITIVE SUPPLY RAIL
ESO
V
CC
0.22 mF
V
N
D
1
D
2
ONE
CHANNEL
OF
CM1213
L
1
CHANNEL
INPUT
0 A
25 A
LINE BEING
PROTECTED
V
GROUND RAIL
CL
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
CHASSIS GROUND
Figure 5. Application of Positive ESD Pulse between Input Channel and Ground
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6
CM1213
PACKAGE DIMENSIONS
SOIC−8 EP
CASE 751AC
ISSUE B
2 X
LOCATION
8 X
SEATING
PLANE
C0.10
PIN ONE
C
D
A
E1
D
14
e
B
TOP VIEW
C0.10
C0.10
SIDE VIEW
SOLDERING FOOTPRINT*
2 X
A-B
C0.10
D
58
EXPOSED
PAD
F
58
E
8 X b
C
2 X
C0.20
BOTTOM VIEW
A-B0.25 D
14
DETAIL A
G
AA
END VIEW
c
GAUGE
PLANE
H
b1
A
A2
L
A1
0.25
(L1)
DETAIL A
q
c1
SECTION A−A
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS (ANGLES
IN DEGREES).
3. DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE
0.08 MM TOTAL IN EXCESS OF THE “b”
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
4. DATUMS A AND B TO BE DETERMINED
AT DATUM PLANE H.
MILLIMETERS
h
(b)
DIM MIN MAX
A 1.35 1.75
A1 0.00 0.10
A2 1.35 1.65
b 0.31 0.51
b1 0.28 0.48
c 0.17 0.25
c1 0.17 0.23
D 4.90 BSC
E 6.00 BSC
E1 3.90 BSC
e 1.27 BSC
L 0.40 1.27
L1 1.04 REF
F 2.24 3.20
G 1.55 2.51
h 0.25 0.50
q 0 8
__
2.72
0.107
1.52
0.060
Exposed
Pad
7.0
0.275
0.024
2.03
0.08
0.6
4.0
0.155
1.270
0.050
SCALE 6:1
mm
ǒ
inches
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
CM1213
PACKAGE DIMENSIONS
MSOP 8, 3x3
CASE 846AD
ISSUE O
SYMBOL
A
A1
A2
b
c
E1E
D
E
E1
e
L
L1 0.95 REF
L2
θ
TOP VIEW
D
A2
A
MIN NOM MAX
1.10
0.05
0.75
0.22
0.13
2.90
4.80
2.90
0.40
0.10
0.85
3.00
4.90
3.00
0.65 BSC
0.60
0.25 BSC
0.15
0.95
0.38
0.23
3.10
5.00
3.10
0.80
0º 6º
DETAIL A
A1 e b
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
c
q
L2
L
L1
DETAIL A
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CM1213
PACKAGE DIMENSIONS
MSOP 10, 3x3
CASE 846AE
ISSUE O
SYMBOL MIN NOM MAX
A
A1
A2
b
c
E1E
D
E
E1
e
L
0.00
0.75
0.17
0.13
2.90
4.75
2.90
0.40
0.05
0.85
3.00
4.90
3.00
0.50 BSC
0.60
L1 0.95 REF
L2
θ
0º 8º
0.25 BSC
1.10
0.15
0.95
0.27
0.23
3.10
5.05
3.10
0.80
DETAIL A
TOP VIEW
D
A2
A
c
A1
eb
SIDE VIEW
END VIEW
q
L2
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L
L1
DETAIL A
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
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CM1213/D
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